CN104980147A

CN104980147A - Continuous time difference measuring method and continuous time difference measuring device

Info

Publication number: CN104980147A
Application number: CN201410136100.7A
Authority: CN
Inventors: 刘伯安
Original assignee: Individual
Current assignee: Individual
Priority date: 2014-04-08
Filing date: 2014-04-08
Publication date: 2015-10-14
Anticipated expiration: 2034-04-08
Also published as: CN104980147B

Abstract

The present invention provides an equal time delay signal conversion method and device which can realize the continuous measurement of the duration time of a high level or a low level of an electronic signal and the time interval of the rising edge-to-rising edge or falling edge-to-falling edge, also provides a method and device applying to the flight time measurement, the laser ranging and the like, and also provides some methods and devices applying to the serial data reception, thereby reducing the sensitivity to the clock frequency, the distortion, the jitter and the like, and enabling a serial data reception device to be more reliable and to be easy to realize.

Description

A kind of method of consecutive hours difference measurements and device

Technical field

The present invention relates generally to method and the device of time difference measurement (0000), the method of such as time difference sampling and device, the method for time difference continuous measurement and device etc., comprise pulse width measuring, pulse cycle, Serial data receiving, flight time measurement etc.Specifically, the present invention relates to a kind of high speed, high accuracy, the method for consecutive hours difference measurements (0000) of wide-range and device, based on the method and device can low cost, high performancely realize multiple measurement mechanism and system, meet the demands such as pulse ranging, flight time measurement, serial data communication.

Background technology

The time of occurrence of perception natural phenomena and precedence understand one of natural basic means, time difference measurement (0000) is the necessary means of detecting period and order, generally, the speed, precision, range, cost etc. of time difference measurement (0000) require to be not quite similar, often can not take into account, such as, precision and the range of high speed measurement are restricted, speed and the range of high-acruracy survey are restricted, the speed of wide range measure and limited precision system, high speed, high accuracy, wide-range mean higher cost, etc.

The invention provides method and the device of a kind of time difference measurement (0000), the requirements such as high speed, high accuracy, wide-range, low cost can be taken into account, meet multiple application demand.

Accompanying drawing explanation

Below first the accompanying drawing of specification of the present invention is simply introduced, and then in conjunction with these accompanying drawings, each enforcement example of the present invention is introduced, principle of the present invention and feature are described.

In figures in the following:

Fig. 1 is the schematic diagram of preferred embodiment measured signal N=8 annular frequency division (0110) circuit and the sequential realized according to method of the present invention;

Fig. 2 is synchronized sampling (0130) circuit of preferred embodiment M signal (0116) and the schematic diagram of sequential that realize according to method of the present invention;

Fig. 3 is the middle schematic diagram triggering (0136) sequential of preferred embodiment realized according to method of the present invention.

Embodiment

First method of the present invention is described below, then the preferred embodiment circuit needed for application the inventive method is described, then the preferred embodiment device of application the inventive method is described.

In the accompanying drawings, the substrate of MOS transistor is not marked, and the agreement equal earth connection GND of substrate of nmos pass transistor, the substrate of PMOS transistor all meet power vd D.

In accompanying drawing and this specification, the gating signal of latch (0040) represents with E (EP, EN), when EP be high level (H), EN be low level (L) time, the output Q (QP, QN) of latch (0040) equals input D (DP, DN), when EP be low level (L), EN be high level (H) time, the output Q (QP, QN) of latch (0040) is constant.

In accompanying drawing and this specification, many signals of telecommunication are all diphase signals, and XXXP represents positive phase signals to agreement, XXXN represents negative signal, XXX or XXX (P/N) represents diphase signal, and XXX is a character string containing upper case or lower case character and numeral, multiple signals in groups in this way, use XXX<m:0>P respectively, XXX<m:0>N, XXX<m:0>, XXX<m:0> (P/N) represents m+1 signal of full group, m+1 the signal of complete group of high level or Low level effective is represented respectively with XXX<m:0>P/N, use XXX<x>P respectively, XXX<x>N, XXX<x> represents each signal in signal group or individual signals, each or the individual signals in the signal group of high level or Low level effective is represented respectively with XXX<x>P/N, sometimes <m:0> is also used to represent m+1 circuit module in groups.

In the following description:

1, transition (0020) refers to analog signal from a relatively stable voltage to the Rapid Variable Design of another relatively stable voltage;

2, overturning (0030) is that digital signal is from low level (L) to high level (H) or from high level (H) to the Rapid Variable Design of low level (L);

3, pulse duration (0400) refers to that measured signal (0010) is in low level (L) or is in the duration of high level (H);

4, the pulse period (0500) refer to measured signal (0010) adjacent twice from low level (L) to high level (H) or time interval of overturning from high level (H) to low level (L) (0030);

5, the flight time (0600) refers to the time interval between one or many upset (0030) to an initial upset (0036) of measured signal (0010), as initial upset (0036) then must be embedded in measured signal (0010) from another signal;

6, duration or the time interval are generally from analog signal transition (0020) or digital signal overturn the mid point of (0030) process, and the mid point to analog signal transition (0020) or digital signal upset (0030) process terminates.

In time difference measurement (0000) device, need ranging pulse width (0400) or pulse period (0500) or flight time (0600), generally the method for analog-and digital-mixing is all taked to measure, namely with clock, sampling is carried out to measured signal (0010) and obtain synchronized sampling (0130), the pulse duration (0400) of synchronized sampling (0130) or pulse period (0500) or flight time (0600) is measured with digital method, forward position time difference (0050) of measured signal (0010) and synchronized sampling (0130) and rear along the time difference (0060) is measured respectively by analogy method, the pulse duration (0400) of measured signal (0010) or pulse period (0500) or flight time (0600) can be obtained, the difference of method is time difference measurement (0000) and clock sampling (0130) method and the restriction to measured signal (0010).

In order to take into account high speed, high accuracy, the requirement of wide region time difference measurement (0000), method of the present invention is not direct but indirectly measures the pulse duration (0400) of measured signal (0010) or pulse period (0500) or flight time (0600), both pulse duration (0400) single in measured signal (0010) or pulse period (0500) or flight time (0600) can have been measured, also can the pulse duration (0400) of continuous measurement measured signal (0010) and (or) pulse period (0500) and (or) flight time (0600), export continuous measurement result or export average measurements, not only can meet the demand of pulse ranging, the demand receiving serial data can also be met.

Conversion such as delay time signal such as grade (0100) is carried out to measured signal (0010), etc. the multiple M signal of the generation of time delay (0116), clock sampling (0130) is carried out to M signal (0116) and obtains intermediate samples (0134) signal, time difference measurement (0000) is carried out to M signal (0116) and intermediate samples (0134), indirectly obtaining the pulse duration (0400) of measured signal (0010) and (or) pulse period (0500) and (or) flight time (0600), is the core of the inventive method.

One, the delay time signal conversion such as

This section illustrates that the present invention carries out waiting method and the device of delay time signal conversion (0100).

Fig. 1 is the schematic diagram of N=8 annular frequency division (0110) circuit and sequential, and wherein S (SP, SN) is measured signal (0010).

An even number N=8 latch (0040) 0112/0:N/2-1 and 0114/0:N/2-1 forms one except N annular frequency division (0110) circuit, Fractional-N frequency measured signal (0010), corresponding measured signal (0010) rising overturns (risetransition, 0032) M signal (0116) is RT<0:N/2-1> (RT<0:N/2-1>P, RT<0:N/2-1>N), decline upset (the fall transition of corresponding measured signal (0010), 0034) M signal (0116) is FT<0:N/2-1> (FT<0:N/2-1>P, FT<0:N/2-1>N).

The sequential that the M signals (0116) such as measured signal (0010) and RT<0:N/2-1>, FT<0:N/2-1> are corresponding is also shown in Fig. 1, for concise description, measured signal (0010) S is painted as has equal pulse duration (0400) and pulse period (0500), the pulse duration (0400) of in fact measured signal (0010) S and pulse period (0500) often unequal and change at random.

The clock cycle (0050) is represented with T, clock can be single phase clock AK (AKP, AKN), also can be diphasic clock AK (AKP, AKN), BK (BKP, BKN), can also be four clock AK (AKP, AKN), BK (BKP, BKN), CK (CKP, CKN), DK (DKP, DKN), their cycle is all T, the phase difference of diphasic clock AK and BK is T/2, and the phase difference of four phase clock AK and BK, BK and CK, CK and DK, DK and AK is all T/4.

Fig. 2 is clock synchronous (0170) circuit of the present invention's clock sampling M signal (0116) and the schematic diagram of sequential, eT<n> (eT<n>P, eT<n>N) be RT<0:N/2-1>, one of M signals such as FT<0:N/2-1> (0116), kK (kKP, kKN) AK is represented, BK, CK, one of DK isochronon, latch (0040) 0132/0:3 cascade forms clock synchronous (0170) circuit and produces intermediate samples (0134) signal, intermediate samples (0134) signal ekm<n> (ekm<n>P, ekm<n>N), in, e is R, F represents that the M signal (0116) of input is RT<n> respectively, FT<n> etc., k are A, B, C, D represents that the clock carrying out sampling is AK respectively, BK, CK, DK, m are 0, 1, 2, 3 represent that intermediate samples (0134) is the output of latch (0132/0:3) etc. respectively, and n is that one of 0 to N/2-1 represents the M signal (0116) of input or the sequence number of intermediate samples (0134).

With PT, AT, DT, WT represents the settling time (0042) of latch (0040) respectively, retention time (0044), time of delay (0046), minimum gating (0048) etc., the pulse duration (0400) of clock cycle (0050) T and measured signal (0010) S must be greater than minimum gating (0048) WT, ek0<n> is DT to PT+0.5*T relative to the Delay Variation scope of eT<n> respectively, ek1<n> is DT+PT to DT+PT+1.0*T relative to the Delay Variation scope of eT<n> respectively, ek2<n> is DT+PT+0.5*T to DT+PT+1.5*T relative to the Delay Variation scope of eT<n> respectively, ek3<n> is DT+PT+1.0*T to DT+PT+2.0*T relative to the Delay Variation scope of eT<n> respectively.

Ek0<n> is selected to trigger (0136) as centre, general wrong upset pulse, ek1<n> is selected to trigger (0136) as centre, accidental wrong upset pulse, ek2<n> is selected to trigger (0160) as centre, substantially can eliminate and overturn pulse by mistake, if need higher reliability, then ek3<n> must be selected to trigger (0136) as centre.

Represent middle respectively with ekT<n> and trigger (0136), then ekT<n>=ek2<nGrea tT.GreaT.GT/ek3<n>, wherein the implication of e, k, n is identical with the implication of e, k, n in ek0<n>, ek1<n>, ek2<n>, ek3<n> etc.Method of the present invention needs to carry out middle triggering (0136) time difference measurement (0000) relative to M signal (0116) by analogy method, and the excursion of the time difference is DT+PT+0.5*T to DT+PT+1.5*T or DT+PT+1.0*T to DT+PT+2.0*T.Divider ratio in Fig. 1 is even number N=8, N is variable, this is the upset interval long enough in order to make M signal (0116), guarantee to complete the time difference measurement (0000) that once undertaken by analogy method and for next time difference measurement (0000) ready.

By method of the present invention, conversion such as delay time signal such as grade (0100) is carried out to measured signal (0010), even if pulse duration (0400) is less than the clock cycle (0050), also guarantee to obtain middle triggering (0136) ekT<n>, latch (0040) as identical with synchronized sampling (0130) electric routing parameter in annular frequency division (0110) is formed, take measures to make these latchs (0040) load also identical simultaneously, then the instantaneous time difference of (0136) and the fractional part of local clock cycles T ratio are triggered in M signal (0116) and centre, equivalent with the instantaneous time difference of measured signal (0010) and local sampling clock, the approximate error of equivalence is relatively little mainly from the time of delay (0046) of latch (0040) and the inconsistent of gating signal time of advent, the component number of annular frequency division (0110) and synchronized sampling (0130) circuit is less, therefore inconsistent and gating signal time of advent latch delay time (0046), the error brought such as inconsistent was less.

The present invention carries out waiting the feature of the method for delay time signal conversion and device as follows to measured signal (0010):

1, after the input and output homophase cascade of the N number of latch of variable even number again head and the tail inverter stages be unified into ring form one except N annular frequency dividing circuit, Fractional-N frequency is carried out to measured signal S, the Position Number of latch is 0 to N-1, the gating port E of even number position latch is with connecting measured signal, it exports is the M signal RT<n> that corresponding measured signal rising overturns, the gating port E of odd positions latch is anti-phase connects measured signal, it exports is the M signal FT<n> that corresponding measured signal decline overturns, the low level of measured signal or the duration of high level must be greater than the minimum gating (0048) of latch, S is input signal, RT<n> and FT<n> is output signal,

2, clock synchronizer is formed, by single phase clock AK or diphasic clock AK respectively with M=3/4 latch input and output homophase cascade, BK or four phase clock AK, BK, CK, DK is to M signal eT<n> synchronized sampling, the Position Number m of latch is 0 to M-1, the gating port E of even number and odd positions latch homophase and anti-phasely connect clock respectively, the Latch output signal corresponding with m is intermediate samples ek0<n> respectively, ek1<n>, ek2<n>, ek3<n> etc., middle triggering ekT<n>=ek2<nGrea tT.GreaT.GT/ek3<n>, e is R, F represents that the M signal of input is RT<n> respectively, FT<n>, k are A, B, C, that D represents sampling respectively is clock AK, BK, CK, DK etc., the half period of clock must be greater than the minimum gating (0048) of latch, AK, BK, CK, DK etc. are input signals, RAT<n>, FAT<n>, RBT<n>, FBT<n>, RCT<n>, FCT<n>, RDT<n>, FDT<n> etc. are output signals,

3, select latch looping frequency dividing circuit and the synchronized sampling circuit of same circuit and device parameters, and make the load of latch also identical as far as possible, with the error of delay time signal conversions such as reducing;

4, the selection of even number N must ensure between twice upset in M signal RT<n> and FT<n>, can complete middle trigger (0136) relative to the time difference measurement (0000) of M signal (0116) and for next time difference measurement (0000) ready, n span is periodically changed to N/2-1 from 0.

Through carrying out conversion such as delay time signal such as grade to measured signal (0010), obtain to overturn (0032) with the rising of measured signal (0010) and decline and overturn M signal corresponding to (0034) (0116) RT<0:N/2-1>, FT<0:N/2-1> and the middle of correspondence trigger (0136) RAT<n>, FAT<n>, RBT<n>, FBT<n>, RCT<n>, FCT<n>, RDT<n>, FDT<n> etc., M signal (0116) and middle triggering (0136) are used to the instantaneous time difference (0180) of measuring measured signal (0010) and clock, measure pulse duration (0400) and pulse period (0500) or the flight time (0600) of measured signal (0010) and receive serial data etc.

The signal shown in Fig. 1, Fig. 2, Fig. 3 is all diphase signal, this section under the method for preliminary treatment measured signal that describes also can simplify and be operated in single-phase digital signal.The inventive method illustrates and in accompanying drawing, under adopting the place of diphase signal to be all likely operated in monophasic pulses, after this no longer illustrates.Under identical condition, diphase signal circuit working speed is higher, and components and parts and number of connection are comparatively large, and realize cost high, monophasic pulses circuit working speed is lower, components and parts and number of connection less, realize cost low.

Two, the clock synchronous time difference

This section illustrates that the present invention carries out method that the clock synchronous time difference (0200) measures and device.

The clock synchronous time difference (0200), refer to the rising edge of local clock or the trailing edge instantaneous value relative to the time difference of measured signal (0010) rising edge or trailing edge, in specification of the present invention, agreement only considers the situation of rising edge clock, to the situation of clock falling edge, when single phase clock is synchronous, the T/2 that will add deduct the time difference is similar to, when diphasic clock is synchronous, the time difference of AK clock and BK clock is T/2, the trailing edge of AK clock and the rising edge of BK clock, the trailing edge of BK clock and the rising edge of AK clock, during four phase clock samplings, AK clock and CK clock, BK clock and DK clock, CK clock and AK clock, the time differences such as DK clock and BK clock are T/2, the trailing edge of AK clock and the rising edge of CK clock, the trailing edge of BK clock and the rising edge of DK clock, the trailing edge of CK clock and the rising edge of AK clock, the trailing edge of DK clock and the rising edge of BK clock.

The method adopting this specification " waiting delay time signal to change " part to describe and device, conversion such as delay time signal such as grade (0100) is carried out to measured signal (0010), obtain M signal eT<n> etc., by single phase clock AK or diphasic clock AK, BK or four phase clock AK, BK, CK, DK to M signal (0116) synchronized sampling, obtain the centre corresponding with the clock number of phases and trigger (0136) eKT<n> etc., the implication of e, k, N, n etc. is constant.

Time-to-digit converter (0210) is adopted to measure RkT<n> relative to RT<n>, FkT<n> relative to the mid-ambles time differences (0202) such as FT<n> one of or partly or entirely, the time-to-digit converter (0210) measuring the ratio of the mid-ambles time difference (0202) and clock cycle T is simpler and accurate, therefore the measurement result of the mid-ambles time difference (0202) is to represent with the ratio of clock cycle T, RkM<n>*T respectively, FkM<n>*T etc., ratio R kM<n>, FkM<n> etc. are the digital synchronous time difference (0204), the fractional part of the digital synchronous time difference (0204) and the product of clock cycle T are the approximations of the clock synchronous time difference (0200), here k is A, B, C, D represents that the clock of sampling is AK respectively, BK, CK, DK etc.

To the measured signal (0010) periodically repeated, do not remove remaining quantization error (0212), namely continue that this is measured remaining quantization error (0212) to superpose with the input of measuring next time, with time-to-digit converter (0210) the duplicate measurements mid-ambles time difference (0202) multiple cycle, measurement result is average, can reduce the fractional part with the digital synchronous time difference (0204) and the error of the product approximate clock synchronous time difference (0200) of clock cycle T.

The feature that the present invention obtains the method for the clock synchronous time difference (0200) or the mid-ambles time difference (0202) or the digital synchronous time difference (0204) and device is as follows:

1, the clock synchronous time difference (0200), refer to the rising edge of clock or the trailing edge instantaneous value relative to the time difference of measured signal (0010) rising edge or trailing edge, the situation only considering rising edge clock is measured to it, to the situation of clock falling edge, when single phase clock is synchronous, rising edge measurement result is added or deducts T/2, when diphasic clock is synchronous, the trailing edge of AK clock and the rising edge of BK clock, the trailing edge of BK clock and the rising edge of AK clock, during four phase clock samplings, the trailing edge of AK clock and the rising edge of CK clock, the trailing edge of BK clock and the rising edge of DK clock, the trailing edge of CK clock and the rising edge of AK clock, the trailing edge of DK clock and the rising edge of BK clock,

2, the method adopting this specification " waiting delay time signal to change " part to describe and device, conversion such as delay time signal such as grade (0100) is carried out to measured signal (0010), obtain M signal eT<n> etc., by single phase clock AK or diphasic clock AK, BK or four phase clock AK, BK, CK, DK to M signal (0116) synchronized sampling, obtain the centre corresponding with the clock number of phases and trigger (0136) ekT<n> etc., the implication of e, k, N, n etc. is constant;

3, time-to-digit converter (0210) is adopted to measure RkT<n> relative to RT<n>, FkT<n> relative to the mid-ambles time differences (0202) such as FT<n> one of or partly or entirely, the time-to-digit converter (0210) measuring the ratio of the mid-ambles time difference (0202) and clock cycle T is simpler and accurate, therefore the measurement result of the mid-ambles time difference (0202) is to represent with the ratio of clock cycle T, RkM<n>*T respectively, FkM<n>*T etc., ratio R kM<n>, FkM<n> etc. are the digital synchronous time difference (0204), the fractional part of the digital synchronous time difference (0204) and the product of clock cycle T are the approximations of the clock synchronous time difference (0200), here k is A, B, C, D represents that the clock of sampling is AK respectively, BK, CK, DK etc.,

4, to the measured signal (0010) periodically repeated, do not remove remaining quantization error (0212), namely continue that this is measured remaining quantization error (0212) to superpose with the input of measuring next time, with time-to-digit converter (0210) the duplicate measurements mid-ambles time difference (0202) multiple cycle, measurement result is average, can reduce the fractional part with the digital synchronous time difference (0204) and the error of the product approximate clock synchronous time difference (0200) of clock cycle T.

Three, clock count

This section illustrates the square law device of clock count of the present invention (0300).

Clock count (0300) refer to AK, BK, CK, clock count between two upsets of the synchronizing signal (0310) that one of DK isochronon is synchronous, the product of clock count (0300) and clock cycle is the time interval between two upsets, two upsets both can be two upsets in same synchronizing signal (0310), also can be two upsets on two synchronizing signals (0310), each upset can be all rise upset (0032) or the upset (0034) that declines, in chronological order, two upsets are called as forward position respectively and trigger (0312) and rear edge triggering (0314).

In middle triggering (0136) ekT<n> etc., RAT<n> is comprised by the A group signal (0320) of AK clock synchronous, FAT<n> etc., RBT<n> is comprised by the group-b signal (0322) of BK clock synchronous, FBT<n> etc., RCT<n> is comprised by the C group signal (0324) of CK clock synchronous, FCT<n> etc., RDT<n> is comprised by the D group signal (0326) of DK clock synchronous, FDT<n> etc.The method of clock count of the present invention (0300) and device, (0312) is triggered in its forward position and rear edge triggering (0314) is with organizing signal.

Generally, the method obtaining the clock count (0300) that forward position is triggered between (0312) and rear edge triggering (0314) has two kinds:

A separate counters (0306) 1, is set, forward position is triggered (0312) and is started separate counters (0306) counting, separate counters (0306) counting is stopped afterwards along triggering (0314), the count value of separate counters (0306) and clock count (0300), must by its zero setting before starting separate counters (0306) counting next time;

A free counter (0308) 2, is set, free counter (0308) keeping count, the counting of (0312) and rear free counter (0308) of sampling respectively along triggering (0314) is triggered in forward position, obtain forward position counting (0302) and rear edge counting (0304), deduct forward position counting (0302) i.e. clock count (0300) along counting (0304) afterwards, free counter (0308) can must not to be shared by multiple clock count (0300) by zero setting;

3, the maximum count of separate counters (0306) and free counter (0308) must be enough large, to ensure to overflow the clock count (0300) that can not lead to errors.

The feature that the present invention obtains the method for clock count (0300) and device is as follows:

1, clock count (0300) refer to AK, BK, CK, clock count between two upsets of the synchronizing signal (0310) that one of DK isochronon is synchronous, the product of clock count (0300) and clock cycle is the time interval between two upsets, two upsets both can be two upsets in same synchronizing signal (0310), also can be two upsets on two synchronizing signals (0310), each upset can be all rise upset (0032) or the upset (0034) that declines, in chronological order, two upsets are called as forward position respectively and trigger (0312) and rear edge triggering (0314),

3, the RAT<n> synchronous by clock AK, FAT<n> etc. are A group signals (0320), the RBT<n> synchronous by clock BK, FBT<n> etc. are group-b signal (0322), the RCT<n> synchronous by clock CK, FCT<n> etc. are C group signals (0324), the RDT<n> synchronous by clock DK, FDT<n> etc. are D group signals (0326),

4, clock count (0300) is obtained

A) in one of signal groups such as A, B, C, D, select signal to trigger (0312) and rear edge triggering (0314) as forward position;

B) one of select, a separate counters (0306) is set, forward position is triggered (0312) and is started separate counters (0306) counting, separate counters (0306) counting is stopped afterwards along triggering (0314), the count value of separate counters (0306) and clock count (0300), must by its zero setting before starting separate counters (0306) counting next time;

C) selection two, a free counter (0308) is set, free counter (0308) keeping count, the counting of (0312) and rear free counter (0308) of sampling respectively along triggering (0314) is triggered in forward position, obtain forward position counting (0302) and rear edge counting (0304), deduct forward position counting (0302) i.e. clock count (0300) along counting (0304) afterwards, free counter (0308) can must not to be shared by multiple clock count (0300) by zero setting;

D) maximum count of separate counters (0306) and free counter (0308) must be enough large, to ensure to overflow the clock count (0300) that can not lead to errors.

Four, pulse width measuring

This section illustrates method and the device of ranging pulse width (0400) of the present invention.

Pulse duration (0400) refers to that measured signal (0010) is in the duration of low level or high level.

The method adopting this specification " the clock synchronous time difference " part to describe and device, obtain signal RkT<n> relative to signal RT<n>, signal FkT<n> the digital synchronous time difference (0204) RkM<n>, FkM<n> etc. relative to signal FT<n> etc., the implications such as e, k, N, n are constant.

The method adopting this specification " clock count " part to describe and device, the method and the device that obtain synchronizing signal (0310) clock count (0300) corresponding with pulse duration (0400) are as follows:

1, RkT<n> is selected to trigger (0312) respectively as forward position, select FkT<n> following closely respectively as rear along triggering (0314), the high level clock count (0300) of acquisition is RkN<n> respectively;

2, FkT<n> is selected to trigger (0312) respectively as forward position, select RkT<m> following closely respectively as rear along triggering (0314), the low level clock count (0300) of acquisition is FkN<n> respectively;

3, m=mod (n+1, N/2), mod (a, A) represent computing a being carried out to mould A.

RkM<n> is leading edge digital synchronous time difference (0204) of measured signal (0010) high level is also that measured signal (0010) is low level rear along the digital synchronous time difference (0204), FkM<n> is measured signal (0010) the low level leading edge digital synchronous time difference (0204) is also the rear along the digital synchronous time difference (0204) of measured signal (0010) high level, the product of clock count (0300) RkN<n> and clock cycle T is the pulse duration (0400) of the synchronized sampling (0130) of measured signal (0010) high level, the product of clock count (0300) FkN<n> and clock cycle T is the pulse duration (0400) of measured signal (0010) low level synchronized sampling (0130).

Pulse duration (0400) be (clock count+leading edge digital synchronous the time difference-after along the digital synchronous time difference) with the product of clock cycle T, use the signal of single phase clock sampling can obtain the pulse duration (0400) of measured signal (0010), in order to improve precision and the reliability of pulse duration (0400) measurement result, sample with diphasic clock or four phase clocks and measure, using mean breadth (0402) as the measurement result of pulse duration (0400), the wherein measurement of the digital synchronous time difference (0204), both summation again and average can first have been measured respectively, also first can sue for peace and measure again average.

The method of ranging pulse width (0400) of the present invention and the feature of device as follows:

1, pulse duration (0400) refers to that measured signal (0010) is in the duration of low level or high level;

3, the method adopting this specification " the clock synchronous time difference " part to describe and device, obtain signal RkT<n> relative to signal RT<n>, signal FkT<n> the digital synchronous time difference (0204) RkM<n>, FkM<n> etc. relative to signal FT<n> etc., the implications such as e, k, N, n are constant;

4, the method adopting this specification " clock count " part to describe and device

A) RkT<n> is selected to trigger (0312) respectively as forward position, select FkT<n> following closely respectively as rear along triggering (0314), the clock count (0300) of the high level of acquisition is RkN<n> respectively;

B) FkT<n> is selected to trigger (0312) respectively as forward position, select RkT<m> following closely respectively as rear along triggering (0314), the low level clock count (0300) of acquisition is FkN<n> respectively;

C) m=mod (n+1, N/2), mod (a, A) represent computing a being carried out to mould A;

5, pulse duration

A) time difference average is RSM<n>, FSM<n> and counting average is RSN<n>, FSM<n> etc., and RSM<n>, FSM<n> etc. both first can measure summation more respectively and on average also first can sue for peace and measure average again;

B) single phase clock sampling

RSM<n>＝∑ _k＝ARkM<n>

FSM<n>＝∑ _k＝AFkM<n>

RSN<n>＝∑ _k＝ARkN<n>

FSN<n>＝∑ _k＝AFkN<n>

C) diphasic clock sampling

RSM<n>＝0.50*∑ _k＝A,BRkM<n>

FSM<n>＝0.S0*∑ _k＝A,BFkM<n>

RSN<n>＝0.50*∑ _k＝A,BRkN<n>

FSN<n>＝0.50*∑ _k＝A,BFkN<n>

D) four phase clock samplings

RSM<n>＝0.25*∑ _k＝A,B,C,DRkM<n>

FSM<n>＝0.25*∑ _k＝A,B,C,DFkM<n>

RSN<n>＝0.25*∑ _k＝A,B,C,DRkN<n>

FSN<n>＝0.25*∑ _k＝A,B,C,DFkN<n>

E) pulse duration of high level

Hw<n>＝(RSN<n>+RSM<n>-FSM<n>)*T

F) low level pulse duration

Lw<n>＝(FSN<n>+FSM<n>-RSM<m>)*T

Five, pulse cycle

This section illustrates method and the device of ranging pulse cycle (0500) of the present invention.

Pulse period (0500) refer to measured signal (0010) adjacent twice from low from level to high level or from high level to low level upset between the time interval.

The method adopting this specification " clock count " part to describe and device, the method and the device that obtain synchronizing signal (0310) clock count (0300) corresponding with the pulse period (0500) are as follows:

1, RkT<n> is selected to trigger (0312) respectively as forward position, select RkT<m> following closely respectively as rear along triggering (0314), the clock count (0300) obtaining rising edge is RkN<n> respectively;

2, FkT<n> is selected to trigger (0312) respectively as forward position, select FkT<m> following closely respectively as rear along triggering (0314), the clock count (0300) obtaining trailing edge is FkN<n> respectively;

RkM<n> is measured signal (0010) rising edge, and to be also measured signal (0010) trailing edge to the trailing edge cycle to leading edge digital synchronous time difference (0204) in rising edge cycle rear along the digital synchronous time difference (0204), FkM<n> is measured signal (0010) trailing edge, and to be also measured signal (0010) rising edge to the rising edge cycle to leading edge digital synchronous time difference (0204) in trailing edge cycle rear along the digital synchronous time difference (0204), the product of clock count (0300) RkN<n> and clock cycle T is the pulse period (0500) of measured signal (0010) rising edge to the synchronized sampling (0130) in rising edge cycle, the product of clock count (0300) FkN<n> and clock cycle T is the pulse period (0500) of measured signal (0010) trailing edge to the synchronized sampling (0130) in trailing edge cycle.

Pulse period (0500) be (clock count+leading edge digital synchronous the time difference-after along the digital synchronous time difference) with the product of clock cycle T, use the signal of single phase clock sampling can obtain the pulse period (0500) of measured signal (0010), in order to improve the pulse period precision and the reliability of (0500) measurement result, sample with diphasic clock or four phase clocks and measure, using average period (0502) as the measurement result of pulse period (0500), the wherein measurement of the digital synchronous time difference (0204), both summation again and average can first have been measured respectively, also first can sue for peace and measure again average.

The method of ranging pulse cycle (0500) of the present invention and the feature of device as follows:

1, the pulse period (0500) refer to measured signal (0010) adjacent twice from low from level to high level or from high level to low level upset the time interval;

A) RkT<n> is selected to trigger (0312) respectively as forward position, select RkT<m> following closely respectively as rear along triggering (0314), the clock count (0300) of the rising edge of acquisition is RkN<n> respectively;

B) FkT<n> is selected to trigger (0312) respectively as forward position, select FkT<m> following closely respectively as rear along triggering (0314), the clock count (0300) of the trailing edge of acquisition is FkN<n> respectively;

5, the pulse period

B) single phase clock sampling

RSM<n>＝∑ _k＝ARkM<n>

FSM<n>＝∑ _k＝AFkM<n>

RSN<n>＝∑ _k＝ARkN<n>

FSN<n>＝∑ _k＝AFkN<n>

C) diphasic clock sampling

RSM<n>＝0.50*∑ _k＝A,BRkM<n>

FSM<n>＝0.50*∑ _k＝A,BFkM<n>

RSN<n>＝0.50*∑ _k＝A,BRkN<n>

FSN<n>＝0.50*∑ _k＝A,BFkN<n>

D) four phase clock samplings

RSM<n>＝0.25*∑ _k＝A,B,C,DRkM<n>

FSM<n>＝0.25*∑ _k＝A,B,C,DFkM<n>

RSN<n>＝0.25*∑ _k＝A,B,C,DRkN<n>

FSN<n>＝0.25*∑ _k＝A,B,C,DFkN<n>

E) rising edge is to the pulse period of rising edge

Tr2r<n>＝(RSN<n>+RSM<n>-RSM<m>)*T

F) trailing edge is to the pulse period of trailing edge

Tf2f<n>＝(FSN<n>+FSM<n>-FSM<m>)*T

Six, flight time measurement

This section illustrates the method and device that the present invention measures the flight time (0600).

Flight time (0600) refers to that the one or many of measured signal (0010) is turned to the time interval between an initial upset (0036), as initial upset (0036) then must be embedded in measured signal (0010) from another signal.

The method adopting this specification " clock count " part to describe and device, the method and the device that obtain synchronizing signal (0310) clock count (0300) corresponding with the flight time (0600) are as follows:

1, from RkT<n>, FkT<n>, select start trigger (0138) SkT<x> corresponding with initial upset (0036) to trigger (0312) as forward position;

2, select RkT<n> thereafter respectively as rear along triggering (0314), the clock count (0300) of the rising edge of acquisition is RkN<n> respectively;

3, select FkT<n> thereafter respectively as rear along triggering (0314), the clock count (0300) of the trailing edge of acquisition is FkN<n> respectively.

To RkM<n> with synchronously overturning the corresponding digital synchronous time difference (0204) SkM<x>, the sampling of FkM<n>, it is the leading edge digital synchronous time difference (0204), thereafter RkM<n>, FkM<n> is rear along the digital synchronous time difference (0204), to RkT<n> with synchronously overturning corresponding start trigger (0138) SkT<x>, the sampling of FkT<n>, the product of clock count (0300) RkN<n> and clock cycle T is the flight time (0600) of start trigger (0138) to the synchronized sampling (0130) of measured signal (0010) rising edge, the product of clock count (0300) FkN<n> and clock cycle T is the flight time (0600) of start trigger (0138) to measured signal (0010) trailing edge synchronized sampling (0130).

Flight time (0600) be (clock count+leading edge digital synchronous the time difference-after along the digital synchronous time difference) with the product of clock cycle T, use the signal of single phase clock sampling can obtain the flight time (0600) of measured signal (0010), in order to improve the flight time precision and the reliability of (0600) measurement result, sample with diphasic clock or four phase clocks and measure, using mean time of flight (0600) as the measurement result of flight time (0600), the wherein measurement of the digital synchronous time difference (0204), both summation again and average can first have been measured respectively, also first can sue for peace and measure again average.

The method that the present invention measures the flight time (0600) and the feature of device as follows:

1, the flight time (0600) refers to that the one or many of measured signal (0010) is turned to the time interval between an initial upset (0036), as initial upset (0036) then must be embedded in measured signal (0010) from another signal;

A) from RkT<n>, FkT<n>, select start trigger (0138) SkT<x> corresponding with initial upset (0036) to trigger (0312) as forward position;

B) select RkT<n> thereafter respectively as rear along triggering (0314), the clock count (0300) of the rising edge of acquisition is RkN<n> respectively;

C) select FkT<n> thereafter respectively as rear along triggering (0314), the clock count (0300) of the trailing edge of acquisition is FkN<n> respectively;

5, the flight time

B) single phase clock sampling

RSM<n>＝∑ _k＝ARkM<n>

FSM<n>＝∑ _k＝AFkM<n>

RSN<n>＝∑ _k＝ARkN<n>

FSN<n>＝∑ _k＝AFkN<n>

C) diphasic clock sampling

RSM<n>＝0.50*∑ _k＝A,BRkM<n>

FSM<n>＝0.50*∑ _k＝A,BFkM<n>

RSN<n>＝0.50*∑ _k＝A,BRkN<n>

FSN<n>＝0.50*∑ _k＝A,BFkN<n>

D) four phase clock samplings

RSM<n>＝0.25*∑ _k＝A,B,C,DRkM<n>

FSM<n>＝0.25*∑ _k＝A,B,C,DFkM<n>

RSN<n>＝0.25*∑ _k＝A,B,C,DRkN<n>

FSN<n>＝0.25*∑ _k＝A,B,C,DFkN<n>

E) from RSM<n>, FSM<n>, the time difference average SSM<x> corresponding with initial upset (0036) is selected;

F) the initial flight time turning to measured signal rising edge

Ts2r<n>＝(RSN<n>+SSM<x>-RSM<n>)*T

G) the initial flight time turning to measured signal trailing edge

Ts2f<n>＝(FSN<n>+SSM<x>-FSM<n>)*T

Seven, Serial data receiving

This section illustrates that the present invention receives method and the device of serial data (0700).

In electronic system and computer system, serial data transmission is the mode of the data communication be widely used, the bit number sending data in unit interval is called as baud rate (Baudrate), send data side and send data with the baud rate corresponding with local clock frequency, receive data side and receive data with the baud rate corresponding with local clock frequency, because the clock frequency of both sides can not be identical, the sampling clock of recipient has accumulated change phase difference with the data flow received, when baud rate is lower, it is poor that recipient goes to control sampled point elimination accumulated phase by frequency far above the local clock of baud rate, when baud rate is close with recipient's clock frequency, transmit leg will make the data flow of transmission have abundant upset, be embedded in data flow by tranmitting data register, make recipient can produce local sampling clock by clock recovery (Clock Recovery) technology and receive data, method conventional is at present the upset that the method for fgs encoder and (or) scrambler increases in data flow, when baud rate improves constantly, need high accuracy, the reference clock of high stability, also complicated clock recovery device is needed, also need to continue to send data flow when the short time is idle and be in normal operating conditions to keep clock recovery device.

The invention provides the method for several reception serial data, illustrate respectively below.

(1) based on the method for reseptance that level time (0710) is measured

Provide the method for the reception serial data (0700) measured based on level time (0710) of the present invention below.

Level time (0710) refers to that serial data (0700) is in the duration of low level or high level.

The clock cycle of data receiver is represented with U, the clock cycle of recipient is represented with T, the maximum relative error of T and U is represented with ET, the bit period (0052) sending and receive is represented respectively with V*U and V*T, the maximum number bits continuing low level or high level in data flow is represented with G, V and G be all be greater than 0 integer, generally V is 1 to realize the highest message transmission rate.

Regard serial data (0700) as continuous print low level or high level signal stream, then level time (0710) is the integral multiple of V*U, then the maximum of level time (0710) is G*V*U, represent that with i the order that level time (0710) is measured then has:

1, the tranmitting data register cycle is similar to: U=T* (1.0 ± E _t)

2, same level bit number is sent: B (i)≤G

3, transmission level duration: W _t=B (i) * V*U ≌ B (i) * V*T

4, incoming level time measurement:

W_{R} (i) = W (i) * T = \frac{W (i)}{V} * V * T

5, absolute worst error

A) cycle accumulated error: T _t=V*T*B (i) * E _t≤ V*T*G*E _t

B) quantizing time (Quantization) error: T _q=V*T*E _q

C) signal distortion (Distortion) error: T _d=V*T*E _d

D) clock rocks (Jitter) error: T _j=V*T*E _j, comprise the error of receiving-transmitting sides

6, absolute error E _awith bit number D (i) of persistence level:

Expression formula in above-mentioned 6th is exactly the constraints based on the Serial data receiving method that level duration (0710) is measured with feasibility, such as: the relative error E of the clock that ordinary crystal oscillators produces _t<10 ^-5, when G is 1000, have (G*E _t) <0.01 is almost negligible, as (V=1) and the time-to-digit converter adopting 3 bits, then E _q<1/8, in this case, the constraints that correctly can receive serial data is (E _d+ E _j) <0.365.

The feature that the present invention is based on the Serial data receiving method that level time (0710) is measured is as follows:

1, the clock cycle T of given recipient, the clock cycle U of given transmit leg, bit period V*U, serial data continue the maximum number bits G of low level or high level, V and G be greater than 0 integer;

2, the maximum relative error E of given transmit leg and recipient's clock cycle _t, maximum absolute periodic accumulated error T _t=V*T*G*E _t, given maximum absolute time quantizing (Quantization) error T _q=V*T*E _q, maximum absolute signal distortion (Distortion) error T _d=V*T*E _d, maximum absolute clock rocks (Jitter) error T _j=V*T*E _j, E _t, E _q, E _d, E _jall be greater than 0;

3, the transmission bit number of the persistence level of serial data is that B (i) is greater than 0 and is less than or equal to G, the level time of error (0710) is not had to be V*T*B (i), the level time (0710) that continuous measurement serial data is in low level or high level is W (i) * T, W (i) is proportionality coefficient, and i represents measurement order;

4, absolute error E _awith reception bit number D (i) of persistence level:

The method measured based on level time of the present invention (0710) receives serial data, has following advantages:

1, to quantification (Quantization) error E of time measurement _qinsensitive;

2, to distortion (Distortion) error E of data flow _dwith shake (Jitter) error E _jinsensitive;

3, do not need to produce local receive clock with clock recovery circuitry, can receiving data stream at once, do not need to send idle data stream;

4, insensitive to the clock frequency difference of receiving-transmitting sides, the crystal oscillator of low cost can be used to produce reference clock, and multiple serial data channel can share a local PLL frequency doubling clock source;

5, asynchronous serial data communication at a high speed can be realized;

6, Gbps serial receiver and protocol-independent, the data processing relevant with agreement can be carried out under lower clock frequency.

(2) a kind of method of reseptance of measuring based on level time (0710) and device

The method of measurement level time (0710) of the present invention and device, be exactly method and the device of the ranging pulse width (0400) that this specification " pulse width measuring " part describes, the following describes method and the device of the reception serial data measured based on level time (0710).

The method adopting this specification " waiting delay time signal to change " part to describe and device, conversion such as delay time signal such as grade (0100) is carried out to serial data (0700), obtain M signal eT<n> etc., by single phase clock AK or diphasic clock AK, BK or four phase clock AK, BK, CK, DK to M signal (0116) synchronized sampling, obtain the centre corresponding with the clock number of phases and trigger (0136) ekT<n> etc., the implication of e, k, N, n etc. is constant.

The method adopting this specification " clock count " part to describe and device, the method and the device that obtain synchronizing signal (0310) clock count (0300) corresponding with level time (0710) are as follows:

1, RkT<n> is selected to trigger (0312) respectively as forward position, select FkT<n> following closely respectively as rear along triggering (0314), the clock count (0300) of the high level of acquisition is RkN<n> respectively;

RkM<n> is leading edge digital synchronous time difference (0204) of serial data (0700) high level is also that serial data (0700) is low level rear along the digital synchronous time difference (0204), FkM<n> is serial data (0700) the low level leading edge digital synchronous time difference (0204) is also the rear along the digital synchronous time difference (0204) of serial data (0700) high level, the product of clock count (0300) RkN<n> and clock cycle T is the level time (0710) of the synchronized sampling (0130) of serial data (0700) high level, the product of sampling clock counting (0300) FkN<n> and clock cycle T is the level time (0710) of serial data (0700) low level synchronized sampling (0130).

Level time (0710) be (sampling clock counting+leading edge digital synchronous the time difference-after along the digital synchronous time difference) with the product of clock cycle T, use the signal of single phase clock sampling can obtain the level time (0710) of serial data (0700), in order to improve precision and the reliability of level time (0710) measurement result, sample with diphasic clock or four phase clocks and measure, using average time (0712) as the measurement result of level time (0710), the wherein measurement of the digital synchronous time difference (0204), both summation again and average can first have been measured respectively, also first can sue for peace and measure again average.

The method of the reception serial data (0700) measured based on level time (0710) of the present invention and the feature of device as follows:

1, level time (0710) refers to that serial data (0700) is in the duration of low level or high level;

2, the method adopting this specification " waiting delay time signal to change " part to describe and device, conversion such as delay time signal such as grade (0100) is carried out to serial data (0700), obtain M signal eT<n> etc., by single phase clock AK or diphasic clock AK, BK or four phase clock AK, BK, CK, DK to M signal (0116) synchronized sampling, obtain the centre corresponding with the clock number of phases and trigger (0136) ekT<n> etc., the implication of e, k, N, n etc. is constant;

5, level time

B) single phase clock sampling

RSM<n>＝∑ _k＝ARkM<n>

FSM<n>＝∑ _k＝AFkM<n>

RSN<n>＝∑ _k＝ARkN<n>

FSN<n>＝∑ _k＝AFkN<n>

C) diphasic clock sampling

RSM<n>＝0.50*∑ _k＝A,BRkM<n>

FSM<n>＝0.50*∑ _k＝A,BFkM<n>

RSN<n>＝0.50*∑ _k＝A,BRkN<n>

FSN<n>＝0.50*∑ _k＝A,BFkN<n>

D) four phase clock samplings

RSM<n>＝0.25*∑ _k＝A,B,C,DRkM<n>

FSM<n>＝0.25*∑ _k＝A,B,C,DFkM<n>

RSN<n>＝0.25*∑ _k＝A,B,C,DRkN<n>

FSN<n>＝0.25*∑ _k＝A,B,C,DFkN<n>

E) level time of high level

Hw<n>＝(RSN<n>+RSM<n>-FSM<n>)*T

F) low level level time

Lw<n>＝(FSN<n>+FSM<n>-RSM<m>)*T

6, serial data

A) bit period: V*T

B) high level ratio:

Hr<n>＝Hw<n>/V＝(RSN<n>+RSM<n>-FSM<n>)/V

C) low level ratio:

Lr<n>＝Lw<n>/V＝(FSN<n>+FSM<n>-RSM<m>)/V

D) high level bit number: Hn<n>=round (Hr<n>)

E) low level bit number: Ln<n>=round (Lr<n>)

F) round (b) expression rounds up approximate to b.

The method of the reception serial data measured based on level time (0710) and device, the general time-to-digit converter (0210) needing multiple passage.

(3) based on the method for reseptance that the instantaneous time difference (0720) measures

The following describes the method for the reception serial data (0700) measured based on the instantaneous time difference (0720) of the present invention.

The instantaneous time difference (0720) refers to the rising edge of local clock or the trailing edge instantaneous value of the time difference in current time (0722) relative to serial data (0700) rising edge or trailing edge.

The basic constraint (0726) that the method for the reception serial data (0700) measured based on the instantaneous time difference (0720) and device have feasibility is:

1, serial data transmission bit period and to receive the relative difference of bit period enough little, within the scope of special time and specific bit number, accumulated time difference (0724) change is less, clock can stablize sampling (0730), obtains correct serial data (0700);

2, the stable sampling (0730) of clock is all had in any specific time;

3, during clock stable sampling (0730), the instantaneous time difference (0720) is near the mid point (time difference mid point 0734) in its constant interval (time difference interval 0732).

Represent the transmission bit period of data receiver with U, the reception bit period representing data receiver with T, represents the maximum relative error of T and U with ET, represents round (1/ET) with G, G be greater than 0 integer.

Regard serial data (0700) as continuous print low level or high level signal stream, then level time (0710) is the integral multiple of U, the upset of serial data (0700) and receive clock have accumulated time difference (0724), the most short period that accumulated time difference (0724) changes is G*T, as ET<10 ^-5, then G>10 ⁵, namely accumulated time difference (0724) change exceedes the shortest time receiving bit period is T*10 ⁵, meet 1 of basic constraint (0726).

Adopt four phase bit period clock samplings, 2 of basic constraint (0726) can be met.

Synchronized sampling (0130) circuit is adopted to sample to serial data (0700), meet 3 of basic constraint (0726), and arrival time difference interval (0732) and time difference mid point (0734) can be obtained with simple and easy method.

Although basic constraint (0726) is satisfied, adopt four phase bit period clock samplings, the distribution of results of stable sampling (0730) exports in the sampling of four phase bit period clock, also needs the method solving following point:

1, from the sampling of four phase bit period clock exports, current steady sampling (0730) is screened out;

2, current steady sampling (0730) is connected into correct serial data (0700) to export.

The method that the present invention screens out current steady sampling (0730) from the sampling of four phase bit period clock exports is:

1, the upset of serial data (0700) and the instantaneous time difference (0720) of four phase bit period clock is measured respectively;

2, the minimum value MIN and the maximum MAX and median MID that calculate and upgrade whole instantaneous time difference (0720) is continued;

3, the absolute value of the instantaneous time difference (0720) of four phase bit period clock and the difference of median MID or square value is calculated respectively as examination the time difference (0740);

4, the pendulous frequency window of an integer W is set, calculates four phase bit period clock respectively and screen up-to-date W the measured value sum of the time difference (0740) as examination parameter (0742);

5, the examination criterion (0744) of stable sampling (0730) is that examination parameter (0742) is minimum, screens out current steady sampling (0730) to screen criterion (0744) from the sampled data of four phase bit period clock.

Current steady sampling (0730) is connected into correct serial data (0700) output intent by the present invention:

1, one is adopted except Fractional-N frequency device, Fractional-N frequency is carried out to serial data (0700), the cycle of obtaining is serial data (0700) cycle N input grouping (0750) GT doubly, with four phase clocks, GT is sampled respectively, obtain four synchronised grouping (0752) SAT, SBT, SCT, SDT etc. and bit period number NAT, NBT, NCT, NDT etc., must take measures to prevent from the signals such as SAT, SBT, SCT, SDT, occurring upset by mistake;

2, the rising edge of GT or trailing edge is selected to trigger (0760) as input, the minimum period of GT is N*2 bit period, rising edge or the trailing edge of corresponding SAT, SBT, SCT, SDT etc. are synchronous triggering (0762), and the selection of N value must ensure that four synchronised triggering (0762) are all ahead of next input and trigger (0760);

3, every phase clock uses a SI PO shift register (0770), serial data (0700) is its input, four phase clocks are its clock respectively, synchronous triggering (0762) is that its parallel output triggers respectively, QAT, QBT, QCT, QDT are its parallel output respectively, NAT, NBT, NCT, NDT etc. are the bit number of parallel output respectively, and the progression of SI PO shift register (0770) must be greater than the maximum of NAT, NBT, NCT, NDT etc.;

4, when the stable sampling (0730) of certain phase clock, corresponding QAT or QBT or QCT or QDT is exactly correct serial data (0700), input triggers (0760) and latches QAT, QBT, QCT, QDT and NAT, NBT, NCT, NDT etc. simultaneously, therefrom select QT and NT by examination criterion (0744), QT and NT data flow is exactly the grouped data (0780) corresponding with serial data (0700) and bit number thereof.

The feature that the present invention is based on serial data (0700) method of reseptance that the instantaneous time difference (0720) measures is as follows:

1, the instantaneous time difference (0720) refers to the rising edge of sampling clock or the trailing edge instantaneous value of the time difference in current time (0710) relative to serial data (0700) rising edge or trailing edge;

2, the clock in four phase serial data bits cycles is adopted to sample to serial data (0700);

3, the instantaneous time difference (0720) measures and screens criterion (0744)

A) the instantaneous time difference (0720) of the rising edge of serial data (0700) and (or) the rising edge of trailing edge and four phase clocks is measured respectively;

B) minimum value MIN and the maximum MAX and median MID that obtain and upgrade whole instantaneous time difference (0720) is continued;

C) absolute value of the instantaneous time difference (0720) of four phase bit period clock and the difference of median MID or square value is calculated respectively as examination the time difference (0740);

D) the pendulous frequency window of an integer W is set, calculates four phase clocks respectively and screen up-to-date W the measured value sum of the time difference (0740) as examination parameter (0742);

E) the examination criterion (0744) of stable sampling (0730) is that examination parameter (0742) is minimum, screens out current steady sampling (0730) to screen criterion (0744) from the sampled data of four phase clocks;

4, stable sampling (0730) is connected and screens selection (0746)

A) one is adopted except Fractional-N frequency device, Fractional-N frequency is carried out to serial data (0700), the cycle of obtaining is serial data (0700) bit period N input grouping (0750) GT doubly, with four phase clocks, GT is sampled respectively, obtain four synchronised grouping (0752) SAT, SBT, SCT, SDT etc. and bit period number NAT, NBT, NCT, NDT etc., must take measures to prevent from the signals such as SAT, SBT, SCT, SDT, occurring upset by mistake;

B) rising edge of GT or trailing edge is selected to trigger (0760) as input, the minimum period of GT is N*2 bit period, rising edge or the trailing edge of corresponding SAT, SBT, SCT, SDT etc. are synchronous triggering (0762), and the selection of N value must ensure that four synchronised triggering (0762) are all ahead of next input and trigger (0760);

C) every phase clock uses a SI PO shift register (0770), serial data (0700) is its input, four phase clocks are its clock respectively, synchronous triggering (0762) is that its parallel output triggers respectively, QAT, QBT, QCT, QDT are its parallel output respectively, NAT, NBT, NCT, NDT etc. are the bit number of parallel output respectively, and the progression of SI PO shift register (0770) must be greater than the maximum of NAT, NBT, NCT, NDT etc.;

D) when the stable sampling (0730) of certain phase clock, corresponding QAT or QBT or QCT or QDT is exactly correct serial data (0700), input triggers (0760) and latches QAT, QBT, QCT, QDT and NAT, NBT, NCT, NDT etc. simultaneously, therefrom select QT and NT by examination criterion (0744), QT and NT data flow is exactly the grouped data (0780) corresponding with serial data (0700) and bit number thereof.

(4) a kind of method of reseptance of measuring based on the instantaneous time difference (0720) and device

The method of the measurement of the present invention instantaneous time difference (0720) and device, be exactly the method for the measurement clock synchronous time difference (0200) that describes of this specification " the clock synchronous time difference " part and device, the method for the reception serial data (0700) that one of the present invention was measured based on the instantaneous time difference (0720) and the feature of device as follows:

3, the method adopting this specification " the clock synchronous time difference " part to describe and device, obtain signal RkT<n> relative to signal RT<n>, signal FkT<n> is relative to the digital synchronous time difference (0204) RkM<n> of signal FT<n> etc., FkM<n> etc., e, k, N, the implications such as n are constant, measurement can be undertaken by one or more time-to-digit converter timesharing and sampling, to measurement result

A) minimum value MIN and the maximum MAX and median MID that calculate and upgrade whole RkM<n>, FkM<n> etc. is continued;

B) absolute value of RkM<n>, FkM<n> etc. of four phase clocks and the difference of median MID or square value is calculated respectively as examination the time difference (0740);

C) the pendulous frequency window of an integer W is set, calculates four phase clocks respectively and screen up-to-date W the measured value sum of the time difference (0740) as examination parameter (0742);

D) the examination criterion (0744) of stable sampling (0730) is that examination parameter (0742) is minimum, screens out current steady sampling (0730) to screen criterion (0744) from the sampled data of four phase clocks;

4, stable sampling (0730) is connected and screens selection (0746)

A) choose one of RT<n>, FT<n> as input grouping (0750) GT, choose one of corresponding RkT<n>, FkT<n> respectively and obtain SAT, SBT, SCT, SDT bit period number NAT, NBT, NCT, NDT etc. respectively as four synchronised grouping (0752) SAT, SBT, SCT, SDT etc. and the method adopting this specification " clock count " part to describe and device;

B) rising edge of GT or trailing edge is selected to trigger (0760) as input, the minimum period of GT is N*2 bit period, rising edge or the trailing edge of corresponding SAT, SBT, SCT, SDT etc. are synchronous triggering (0762), and the value of N must ensure that four synchronised triggering (0762) are all ahead of next input and trigger (0760);

Claims

1. wait method and the device of delay time signal conversion, comprising:

After the input and output homophase cascade of the N number of latch of a) variable even number again head and the tail inverter stages be unified into ring form one except N annular frequency dividing circuit, Fractional-N frequency is carried out to measured signal S, the Position Number of latch is 0 to N-1, the gating port E of even number position latch is with connecting measured signal, it exports is the M signal RT<n> that corresponding measured signal rising overturns, the gating port E of odd positions latch is anti-phase connects measured signal, it exports is the M signal FT<n> that corresponding measured signal decline overturns, the low level of measured signal or the duration of high level must be greater than the minimum gating time of latch, S is input signal, RT<n> and FT<n> is output signal,

B) clock synchronizer is formed, by single phase clock AK or diphasic clock AK with M=3/4 latch input and output homophase cascade respectively, BK or four phase clock AK, BK, CK, DK is to M signal eT<n> synchronized sampling, the Position Number m of latch is 0 to M-1, the gating port E of even number and odd positions latch homophase and anti-phasely connect clock respectively, the Latch output signal corresponding with m is intermediate samples ek0<n> respectively, ek1<n>, ek2<n>, ek3<n> etc., middle triggering ekT<n>=ek2<nGrea tT.GreaT.GT/ek3<n>, e is R, F represents that the M signal of input is RT<n> respectively, FT<n>, k are A, B, C, that D represents sampling respectively is clock AK, BK, CK, DK etc., the half period of clock must be greater than the minimum gating time of latch, AK, BK, CK, DK etc. are input signals, RAT<n>, FAT<n>, RBT<n>, FBT<n>, RCT<n>, FCT<n>, RDT<n>, FDT<n> etc. are output signals,

C) select latch looping frequency divider and the clock synchronizer of same circuit and device parameters, and make the load of latch also identical as far as possible, with the error of delay time signal conversions such as reducing;

D) selection of even number N must ensure between twice upset in M signal RT<n> and FT<n>, can complete the time difference measurement of middle triggering relative to M signal also for next time difference measurement is ready, n span is periodically changed to N/2-1 from 0.

2. obtain the clock synchronous time difference, the mid-ambles time difference, the method for the digital synchronous time difference and a device, comprising:

A) the clock synchronous time difference (0300), refer to the rising edge of clock or the trailing edge instantaneous value relative to the time difference of measured signal rising edge or trailing edge, the situation only considering rising edge clock is measured to it, to the situation of clock falling edge, when single phase clock is synchronous, rising edge measurement result is added or deducts T/2, when diphasic clock is synchronous, the trailing edge of AK clock and the rising edge of BK clock, the trailing edge of BK clock and the rising edge of AK clock, during four phase clock samplings, the trailing edge of AK clock and the rising edge of CK clock, the trailing edge of BK clock and the rising edge of DK clock, the trailing edge of CK clock and the rising edge of AK clock, the trailing edge of DK clock and the rising edge of BK clock,

B) method as claimed in claim 1 and device is adopted, conversion such as delay time signal such as grade is carried out to measured signal, obtain M signal eT<n> etc., by single phase clock AK or diphasic clock AK, BK or four phase clock AK, BK, CK, DK to M signal synchronized sampling, obtain the centre corresponding with the clock number of phases and trigger ekT<n> etc., the implication of e, k, N, n etc. is constant;

C) time-to-digit converter is adopted to measure RkT<n> relative to RT<n>, FkT<n> relative to the mid-ambles time differences such as FT<n> one of or partly or entirely, the time-to-digit converter measuring the ratio of the mid-ambles time difference and clock cycle T is simpler and accurate, therefore the measurement result of the mid-ambles time difference is to represent with the ratio of clock cycle T, RkM<n>*T respectively, FkM<n>*T etc., ratio R kM<n>, FkM<n> etc. are the digital synchronous time differences, the fractional part of the digital synchronous time difference and the product of clock cycle T are the approximations of the clock synchronous time difference, here k is A, B, C, D represents that the clock of sampling is AK respectively, BK, CK, DK etc.,

D) to the measured signal periodically repeated, do not remove remaining quantization error, namely continue that this is measured remaining quantization error to superpose with the input of measuring next time, measurement result is average with the time-to-digit converter duplicate measurements mid-ambles time difference in multiple cycle,, can reduce by the error of the fractional part of the digital synchronous time difference with the product approximate clock synchronous time difference of clock cycle T.

3. obtain method and the device of clock count, comprising:

A) clock count refer to two of synchronous with one of AK, BK, CK, DK isochronon synchronizing signal overturn between clock count, the product of clock count and clock cycle is the time interval between two upsets, two upsets both can be two upsets in same synchronizing signal, also can be two upsets in two synchronizing signals, each upset can be all rise upset or the upset that declines, in chronological order, two upsets are called as forward position triggering and the triggering of rear edge respectively;

B) method as claimed in claim 1 and device is adopted, conversion such as delay time signal such as grade is carried out to measured signal, obtain M signal eT<n> etc., by single phase clock AK or diphasic clock AK, BK or four phase clock AK, BK, CK, DK to M signal synchronized sampling, obtain the centre corresponding with the clock number of phases and trigger (0160) ekT<n> etc., the implication of e, k, N, n etc. is constant;

C) by the RAT<n> that clock AK is synchronous, FAT<n> etc. are A group signals, the RBT<n> synchronous by clock BK, FBT<n> etc. are group-b signals, the RCT<n> synchronous by clock CK, FCT<n> etc. are C group signals, the RDT<n> synchronous by clock DK, FDT<n> etc. are D group signals,

D) clock count is obtained

I. in one of signal groups such as A, B, C, D, select signal to trigger as forward position and the triggering of rear edge;

Ii. one of select, arrange a separate counters, forward position is triggered and is started separate counters counting, and rear edge is triggered and stopped separate counters counting, the count value of separate counters and clock count, must by its zero setting before starting separate counters counting next time;

Iii. selection two, a free counter is set, free counter keeping count, forward position is triggered and the rear counting along triggering free counter of sampling respectively, obtain forward position counting and rear edge counting, deduct forward position counting and clock count along counting afterwards, free counter can must not to be shared by multiple clock count by zero setting;

Iv. the maximum count of separate counters and free counter must be enough large, to ensure to overflow the clock count that can not lead to errors.

4. the method for ranging pulse width and a device, comprising:

A) pulse duration refers to that measured signal is in the duration of low level or high level;

B) conversion such as delay time signal such as grade is carried out to measured signal, obtain M signal eT<n> etc., by single phase clock AK or diphasic clock AK, BK or four phase clock AK, BK, CK, DK to M signal synchronized sampling, obtain the centre corresponding with the clock number of phases and trigger ekT<n> etc., the implication of e, k, N, n etc. is constant;

C) method as claimed in claim 2 and device is adopted, obtain signal RkT<n> relative to signal RT<n>, signal FkT<n> the digital synchronous time difference RkM<n>, FkM<n> etc. relative to signal FT<n> etc., the implications such as e, k, N, n are constant;

D) method as claimed in claim 3 and device is adopted

I. RkT<n> is selected to trigger respectively as forward position, select FkT<n> following closely respectively as rear along triggering, the clock count of the high level of acquisition is RkN<n> respectively;

Ii. FkT<n> is selected to trigger respectively as forward position, select RkT<m> following closely respectively as rear along triggering, the low level clock count of acquisition is FkN<n> respectively;

Iii.m=mod (n+1, N/2), mod (a, A) represent computing a being carried out to mould A;

E) pulse duration

I. time difference average is RSM<n>, FSM<n> and counting average is RSN<n>, FSM<n> etc., and RSM<n>, FSM<n> etc. both first can measure summation more respectively and on average also first can sue for peace and measure average again;

Ii. single phase clock sampling

RSM<n>＝∑ _k＝ARkM<n>

FSM<n>＝∑ _k＝AFkM<n>

RSN<n>＝∑ _k＝ARkN<n>

FSN<n>＝∑ _k＝AFkN<n>

Iii. diphasic clock sampling

RSM<n>＝0.50*∑ _k＝A,BRkM<n>

FSM<n>＝0.50*∑ _k＝A,BFkM<n>

RSN<n>＝0.50*∑ _k＝A,BRkN<n>

FSN<n>＝0.50*∑ _k＝A,BFkN<n>

Iv. four phase clock samplings

RSM<n>＝0.25*∑ _k＝A,B,C,DRkM<n>

FSM<n>＝0.25*∑ _k＝A,B,C,DFkM<n>

RSN<n>＝0.25*∑ _k＝A,B,C,DRkN<n>

FSN<n>＝0.25*∑ _k＝A,B,C,DFkN<n>

V. the pulse duration of high level

Hw<n>＝(RSN<n>+RSM<n>-FSM<n>)*T

Vi. low level pulse duration

Lw<n>＝(FSN<n>+FSM<n>-RSM<m>)*T

5. the method in ranging pulse cycle and a device, comprising:

A) pulse period refer to measured signal adjacent twice from low from level to high level or from high level to low level upset the time interval;

D) method as claimed in claim 3 and device is adopted

I. RkT<n> is selected to trigger respectively as forward position, select RkT<m> following closely respectively as rear along triggering, the clock count of the rising edge of acquisition is RkN<n> respectively;

Ii. FkT<n> is selected to trigger respectively as forward position, select FkT<m> following closely respectively as rear along triggering, the clock count of the trailing edge of acquisition is FkN<n> respectively;

E) pulse period

Ii. single phase clock sampling

RSM<n>＝∑ _k=ARkM<n>

FSM<n>＝∑ _k＝AFkM<n>

RSN<n>＝∑ _k＝ARkN<n>

FSN<n>＝∑ _k＝AFkN<n>

Iii. diphasic clock sampling

RSM<n>＝0.50*∑ _k＝A,BRkM<n>

FSM<n>＝0.50*∑ _k＝A,BFkM<n>

RSN<n>＝0.50*∑ _k＝A,BRkN<n>

FSN<n>＝0.50*∑ _k＝A,BFkN<n>

Iv. four phase clock samplings

RSM<n>＝0.25*∑ _k＝A,B,C,DRkM<n>

FSM<n>＝0.25*∑ _k＝A,B,C,DFkM<n>

RSN<n>＝0.25*∑ _k＝A,B,C,DRkN<n>

FSN<n>＝0.25*∑ _k＝A,B,C,DFkN<n>

V. rising edge is to the pulse period of rising edge

Tr2r<n>＝(RSN<n>+RSM<n>-RSM<m>)*T

Vi. trailing edge is to the pulse period of trailing edge

Tf2f<n>＝(FSN<n>+FSM<n>-FSM<m>)*T

6. measure method and the device of flight time, comprising:

A) flight time refers to that the one or many of measured signal is turned to the time interval between an initial upset, as initial upset then must be embedded in measured signal from another signal;

C) obtain signal RkT<n> relative to signal RT<n>, signal FkT<n> the digital synchronous time difference RkM<n>, FkM<n> etc. relative to signal FT<n> etc., the implications such as e, k, N, n are constant;

D) method as claimed in claim 3 and device is adopted

I. select from RkT<n>, FkT<n> and overturn corresponding start trigger SkT<x> trigger as forward position with initial;

Ii. select RkT<n> thereafter respectively as rear along triggering, the clock count of the rising edge of acquisition is RkN<n> respectively;

Iii. select FkT<n> thereafter respectively as rear along triggering, the clock count of the trailing edge of acquisition is FkN<n> respectively;

E) flight time

Ii. single phase clock sampling

RSM<n>＝∑ _k＝ARkM<n>

FSM<n>＝∑ _k＝AFkM<n>

RSN<n>＝∑ _k＝ARkN<n>

FSN<n>＝∑ _k＝AFkN<n>

Iii. diphasic clock sampling

RSM<n>＝0.50*∑ _k＝A,BRkM<n>

FSM<n>＝0.50*∑ _k＝A,BFkM<n>

RSN<n>＝0.50*∑ _k＝A,BRkN<n>

FSN<n>＝0.50*∑ _k＝A,BFkN<n>

Iv. four phase clock samplings

RSM<n>＝0.25*∑ _k＝A,B,C,DRkM<n>

FSM<n>＝0.25*∑ _k＝A,B,C,DFkM<n>

RSN<n>＝0.25*∑ _k＝A,B,C,DRkN<n>

FSN<n>＝0.25*∑ _k＝A,B,C,DFkN<n>

V. select from RSM<n>, FSM<n> and overturn corresponding time difference average SSM<x> with initial

Vi. the initial flight time turning to measured signal rising edge

Ts2r<n>＝(RSN<n>+SSM<x>-RSM<n>)*T

Vii. the initial flight time turning to measured signal trailing edge

Ts2f<n>＝(FSN<n>+SSM<x>-FSM<n>)*T

7., based on the Serial data receiving method that level time is measured, comprising:

A) level time refers to that serial data is in the duration of low level or high level;

B) the clock cycle T of given recipient, the clock cycle U of given transmission, bit period V*U, serial data continue the maximum number bits G of low level or high level, V and G be greater than 0 integer;

C) the maximum relative error E of given transmit leg and recipient's clock cycle _t, maximum absolute periodic accumulated error is T _t=V*T*G*E _t, given maximum absolute time quantizing (Quantization) error T _q=V*T*E _q, maximum absolute signal distortion (Distortion) error T _d=V*T*E _d, maximum absolute clock rocks (Jitter) error T _j=V*T*E _j, E _t, E _q, E _d, E _jall be greater than 0;

D) the transmission bit number of the persistence level of serial data is that B (i) is greater than 0 and is less than or equal to G, the level time of error (0610) is not had to be V*T*B (i), the level time (0610) that continuous measurement serial data is in low level or high level is W (i) * T, W (i) is proportionality coefficient, and i represents measurement order;

E) absolute error T _awith reception bit number D (i) of persistence level

8. receive method and the device of serial data, comprising:

B) method as claimed in claim 1 and device is adopted, conversion such as delay time signal such as grade is carried out to serial data, obtain M signal eT<n> etc., by single phase clock AK or diphasic clock AK, BK or four phase clock AK, BK, CK, DK to M signal synchronized sampling, obtain the centre corresponding with the clock number of phases and trigger ekT<n> etc., the implication of e, k, N, n etc. is constant;

D) method as claimed in claim 3 and device is adopted

Ii. FkT<n> is selected to trigger respectively as forward position, select RkT<m> following closely respectively as rear along triggering, obtaining low level clock count is FkN<n> respectively;

E) level time

Ii. single phase clock sampling

RSM<n>＝∑ _k＝ARkM<n>

FSM<n>＝∑ _k＝AFkM<n>

RSN<n>＝∑ _k＝ARkN<n>

FSN<n>＝∑ _k＝AFkN<n>

Iii. diphasic clock sampling

RSM<n>＝0.50*∑ _k＝A,BRkM<n>

FSM<n>＝0.50*∑ _k＝A,BFkM<n>

RSN<n>＝0.50*∑ _k＝A,BRkN<n>

FSN<n>＝0.50*∑ _k＝A,BFkN<n>

Iv. four phase clock samplings

RSM<n>＝0.25*∑ _k＝A,B,C,DRkM<n>

FSM<n>＝0.25*∑ _k＝A,B,C,DFkM<n>

RSN<n>＝0.25*∑ _k＝A,B,C,DRkN<n>

FSN<n>＝0.25*∑ _k＝A,B,C,DFkN<n>

V. the level time of high level

Hw<n>＝(RSN<n>+RSM<n>-FSM<n>)*T

Vi. low level level time

Lw<n>＝(FSN<n>+FSM<n>-RSM<m>)*T

F) serial data

I. bit period: V*T

Ii. high level ratio:

Hr<n>＝Hw<n>/V＝(RSN<n>+RSM<n>-FSM<n>)/V

Iii. low level ratio:

Lr<n>＝Lw<n>/V＝(FSN<n>+FSM<n>-RSM<m>)/V

Iv. high level bit number: Hn<n>=round (Hr<n>)

V. low level bit number: Ln<n>=round (Lr<n>)

Vi.round (b) expression rounds up approximate to b.

9., based on a Serial data receiving method for instantaneous time difference measurement, comprising:

A) the instantaneous time difference refers to that the rising edge of sampling clock or the trailing edge time difference relative to serial data rising edge or trailing edge is at the instantaneous value of current time;

B) clock in four phase serial data bits cycles is adopted to sample to serial data;

C) instantaneous time difference measurement and examination criterion

I. the instantaneous time difference of the rising edge of serial data and (or) the rising edge of trailing edge and four phase clocks is measured respectively;

Ii. the minimum value MIN and the maximum MAX and median MID that obtain and upgrade whole instantaneous time difference is continued;

Iii. the absolute value of the instantaneous time difference of four phase bit period clock and the difference of median MID or square value is calculated respectively as the examination time difference;

Iv., the pendulous frequency window of an integer W is set, calculates four phase clocks respectively and screen the time differences up-to-date W measured value sum as screening parameter;

V. the examination criterion of stable sampling is that examination parameter is minimum, screens out current steady sampling to screen criterion from the sampled data of four phase clocks;

D) stable sampling is connected and screens selection

I. one is adopted except Fractional-N frequency device, Fractional-N frequency is carried out to serial data, the cycle of obtaining is serial data cycle N input grouping GT doubly, with four phase clocks, GT is sampled respectively, obtain four synchronised grouping SAT, SBT, SCT, SDT etc. and obtain its bit period number NAT, NBT, NCT, NDT etc., must take measures to prevent from the signals such as SAT, SBT, SCT, SDT, occurring upset by mistake;

Ii. the rising edge of GT or trailing edge is selected to trigger as input, the minimum period of GT is N*2 bit period, rising edge or the trailing edge of corresponding SAT, SBT, SCT, SDT etc. are synchronous triggerings, and the value of N must ensure that four synchronised triggerings are all ahead of next input and trigger;

Iii. every phase clock uses a SI PO shift register, serial data is its input, four phase clocks are its clock respectively, synchronous triggering is that its parallel output triggers respectively, QAT, QBT, QCT, QDT are its parallel output respectively, NAT, NBT, NCT, NDT etc. are the bit number of parallel output respectively, and the progression of SI PO shift register must be greater than the maximum of NAT, NBT, NCT, NDT etc.;

Iv. when the stable sampling of certain phase clock, corresponding QAT or QBT or QCT or QDT is exactly correct serial data, input triggers and latches QAT, QBT, QCT, QDT and NAT, NBT, NCT, NDT etc. simultaneously, therefrom select QT and NT by examination criterion, QT and NT data flow is exactly the grouped data corresponding with serial data and bit number thereof.

10. receive method and the device of serial data, comprising:

C) method as claimed in claim 1 and device is adopted, obtain signal RkT<n> relative to signal RT<n>, signal FkT<n> is relative to the digital synchronous time difference (0340) RkM<n> of signal FT<n> etc., FkM<n> etc., e, k, N, the implications such as n are constant, measurement can be undertaken by one or more time-to-digit converter timesharing and sampling, to measurement result

I. the minimum value MIN and the maximum MAX and median MID that calculate and upgrade whole RkM<n>, FkM<n> etc. is continued;

Ii. the absolute value of RkM<n>, FkM<n> etc. of four phase clocks and the difference of median MID or square value is calculated respectively as the examination time difference;

Iii., the pendulous frequency window of an integer W is set, calculates four phase clocks respectively and screen up-to-date W the measured value sum of the time difference as examination parameter;

Iv. the examination criterion of stable sampling is that examination parameter is minimum, screens out current steady sampling to screen criterion from the sampling of four phase clocks;

D) stable sampling is connected and screens selection

I. choose one of RT<n>, FT<n> as input grouping GT, choose one of corresponding RkT<n>, FkT<n> respectively as four synchronised grouping SAT, SBT, SCT, SDT etc. and adopt method as claimed in claim 3 and device to obtain bit period number NAT, NBT, NCT, NDT etc. of SAT, SBT, SCT, SDT respectively;

Ii. the rising edge of GT or trailing edge is selected to trigger as input, the minimum period of GT is N*2 bit period, rising edge or the trailing edge of corresponding SAT, SBT, SCT, SDT etc. are synchronous triggerings, and the value of N must ensure that four synchronised triggerings all lag behind corresponding input and trigger but be ahead of next input triggering;