CN104979293B - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
- Publication number
- CN104979293B CN104979293B CN201410138464.9A CN201410138464A CN104979293B CN 104979293 B CN104979293 B CN 104979293B CN 201410138464 A CN201410138464 A CN 201410138464A CN 104979293 B CN104979293 B CN 104979293B
- Authority
- CN
- China
- Prior art keywords
- semiconductor devices
- transistor
- manufacture method
- impervious layer
- diffusion impervious
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, is related to technical field of semiconductors.The manufacture method of the semiconductor devices of the present invention, by being diffused landform engineering after diffusion impervious layer is set（DTE）Processing, can improve the performance of pull-down transistor, keep or even reduce the performance of transmission gate transistor, so as to improve the β ratios of SRAM, therefore can improve the performance of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor devices.
Background technology
In technical field of semiconductors, stress engineering is one of most important factor of device performance lifting.With partly leading
The process node of body technique develops into below 90nm, and influence of the stress to device performance becomes can not be ignored.And for high density
For integrated circuit, the requirement of the performance boost to cmos device is more and more urgent.
In different directions, influence of the stress to the performance of NMOS and PMOS device is different.Fig. 1 is illustrated by answering
Power improves the direction of stress required during the performance of PMOS and NMOS, wherein, Figure 1A is illustrated needed for the performance of lifting NMOS
Stress, Figure 1B illustrate the stress needed for the performance of lifting PMOS.As it can be seen that in X-direction（Orientation）, tensile stress can be with
The performance of NMOS is lifted, compression can lift the performance of PMOS；And in the Y direction（Channel width dimension）, tensile stress both can be with
The performance of NMOS is lifted, the performance of PMOS can also be lifted.
In the prior art, as shown in Fig. 2, diffusion landform engineering（diffusion topography engineering；
DTE）Technology is used for by isolating shallow trench（STI）Apply compression to raceway groove to lift the performance of MOS device.Wherein, scheme
2A is that device is schemed along the TEM of Y-direction, and Fig. 2 B are the stress simulation figure of DTE technologies.However, in this technical solution, due to
The tensile stress that DTE processes are produced in orientation so that PMOS is released in the compression of orientation, thus meeting
Causing the performance of PMOS, there are certain decline.
In the prior art, the requirement of the cell stability to SRAM and cellar area is higher and higher.Normally, SRAM is mono-
Member includes pulling up transistor（PU）, pull-down transistor（PD）And transmission gate transistor（PG）, wherein, pull up transistor as PMOS,
Pull-down transistor and transmission gate transistor are NMOS.SRAM can be shown with high reading and writing speed storage information, Fig. 3
A kind of typical structure of sram cell of the prior art.For SRAM, static noise allowance is read（read static
noise margin；RSNM）It is increasingly difficult to meet the requirement of practical application.And improve the β ratios of SRAM（βratio）, can be with
Improve and read static noise allowance（RSNM）.Therefore, the β ratios of SRAM how to be improved（βratio）And then improve reading static state and make an uproar
Sound allowance a, it has also become technical problem urgently to be resolved hurrily in the prior art.
Therefore, in order to solve the above technical problems, the present invention proposes a kind of new semiconductor devices（SRAM or including SRAM's
Semiconductor devices）Manufacture method.
The content of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, can improve the β of SRAM
Ratio.
The embodiment of the present invention provides a kind of manufacture method of semiconductor devices, the described method includes：
Step S101：Semiconductor substrate is provided, defines active area on the semiconductor substrate；
Step S102：Diffusion impervious layer is formed on the semiconductor substrate；
Step S103：The diffusion impervious layer is performed etching, retains the diffusion impervious layer and is located at transmission gate transistor
Channel width dimension part, remove the part that the diffusion impervious layer is located at other regions；
Step S104：Landform project treatment is diffused, is pulled up transistor and the performance of pull-down transistor and guarantor with improving
Hold or even reduce the performance of transmission gate transistor.
Alternatively, in the step S103, also retain the diffusion impervious layer and be located at the channel length to pull up transistor
The part in direction.
Alternatively, in the step S102, the diffusion impervious layer is compression film；Also, in the step
In S104, while landform project treatment is diffused, the compression for the part that the diffusion impervious layer is retained is transferred
To the channel width dimension of transmission gate transistor.
Alternatively, in the step S102, the diffusion impervious layer is compression film；Also, in the step
In S104, while landform project treatment is diffused, the compression for the part that the diffusion impervious layer is retained is transferred
Channel width dimension and the orientation that pulls up transistor to transmission gate transistor.
Alternatively, in the step S102, the material of the compression film is compression silicon nitride.
Alternatively, in the step S104, the diffusion landform project treatment carries out under the annealing conditions of hydrogen.
Alternatively, in the step S104, the duration of the diffusion landform project treatment is 5-120 seconds.
Alternatively, step S105 is further included after the step S104：
Remove the part that the diffusion impervious layer is retained.
Alternatively, in the step S105, method is used by removing the part that the diffusion impervious layer is retained
Wet method is peeled off.
Alternatively, step S106 is further included after the step S105：The active area formed pull up transistor, under
Pull transistor and transmission gate transistor.
The manufacture method of the semiconductor devices of the present invention, by being diffused landform engineering after diffusion impervious layer is set
（DTE）Processing, can improve and pull up transistor and the performance of pull-down transistor, the property for keeping even reducing transmission gate transistor
Can, so as to improve the β ratios of SRAM, therefore the performance of semiconductor devices can be improved.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
The schematic diagram in the direction of stress required when being the performance by stress improvement PMOS and NMOS Fig. 1；Wherein, Figure 1A
The stress needed for the performance of lifting NMOS is illustrated, Figure 1B illustrates the stress needed for the performance of lifting PMOS；
Fig. 2 is the schematic diagram of DTE technologies of the prior art；Wherein, Fig. 2A is a kind of device of the prior art along Y side
To TEM scheme, Fig. 2 B be DTE technologies stress simulation figure；
Fig. 3 is a kind of structure diagram of sram cell of the prior art；
Fig. 4 A to Fig. 4 E are the structure that the correlation step of the manufacture method of the semiconductor devices of the embodiment of the present invention is formed
Schematic diagram；Wherein,
Fig. 4 A-1 are the top view to form the device architecture after active area, and Fig. 4 A-2 are the section view along Fig. 4 A-1 center lines AA '
Figure；
Fig. 4 B-1 are the top view to form the device architecture after compression film, and Fig. 4 B-2 are along Fig. 4 B-1 center lines AA's '
Sectional view；
For Fig. 4 C-1 to remove the top view of the device architecture after the compression film of part, Fig. 4 C-2 are along Fig. 4 C-1 center lines
The sectional view of AA ', Fig. 4 C-3 are the sectional view along Fig. 4 C-1 center lines BB '；
For Fig. 4 D-1 to carry out the schematic plan of the device architecture after DTE, Fig. 4 D-2 are showing along Fig. 4 D-1 center lines AA '
Meaning property sectional view, Fig. 4 D-3 are the schematic cross sectional views along Fig. 4 D-1 center lines BB '；
For Fig. 4 E-1 to remove the top view of the device architecture after remaining compression film, Fig. 4 E-2 are along Fig. 4 E-1 center lines
The sectional view of AA ', Fig. 4 E-3 are the sectional view along Fig. 4 E-1 center lines BB '；
Fig. 5 is a kind of indicative flowchart of the manufacture method of the semiconductor devices of the embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to further include to make
With the different orientation with the device in operation.For example, if the device upset in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as that the injection region of rectangle usually has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions,
The present invention can also have other embodiment.
In the following, the manufacture method of the semiconductor devices of the embodiment of the present invention is described with reference to Fig. 4 A to Fig. 4 E and Fig. 5.Its
In, Fig. 4 A to Fig. 4 E are the schematic diagram for the structure that the correlation step of the manufacture method of the semiconductor devices of embodiment is formed；Fig. 5 is
A kind of indicative flowchart of the manufacture method of the semiconductor devices of the embodiment of the present invention.
The manufacture method of the semiconductor devices of the present embodiment, includes the following steps：
Step A1：Semiconductor substrate 100 is provided, active area 101 is defined in the Semiconductor substrate 100, such as Fig. 4 A institutes
Show.Wherein, the active area 101 includes pulling up transistor（PU）Active area, pull-down transistor（PD）Active area and biography
Defeated door transistor（PG）Active area, as shown in Figure 4 A.
Exemplarily, which is monocrystalline substrate or silicon-on-insulator substrate（SOI substrate）.Pull up transistor
（PU）For PMOS, pull-down transistor（PD）And transmission gate transistor（PG）For NMOS.
Step A2：Compression film 102 is formed on a semiconductor substrate, as shown in Figure 4 B.
Wherein, compression film 102 can use various feasible materials, such as compression silicon nitride in the prior art.
The method for forming compression film 102, can be sedimentation or other suitable methods.
Step A3：Compression film 102 is performed etching, reservation compression film 102, which is located at, to pull up transistor（PMOS）
Orientation part 1021（It is denoted as the Part I of compression film retained）And compression film 102 is located at
Transmission gate transistor（NMOS）Channel width dimension part 1022（It is denoted as the Part II of compression film retained）, go
Except compression film 102 is located at the part in other regions, as shown in Figure 4 C.
Exemplarily, the etching can be dry etching or wet etching.When the material of compression film 102 should for pressure
During power silicon nitride, it is preferred to use dry etching.
Step A4：It is diffused landform engineering（DTE）Processing, to improve the performance of pull-down transistor, keep even reducing
The performance of transmission gate transistor is so as to improve the β ratios of SRAM（βratio）, and improve the performance to pull up transistor.By the step
Suddenly the structure formed, as shown in Figure 4 D.
It is to be understood that Fig. 4 D are only used for illustrating, the structure change after DTE is handled is not showed that, but actually
The microstructure of device causes stress that above-mentioned change occurs there occurs certain change.
In the present embodiment, it is being diffused landform engineering（DTE）During processing, except retained compression is thin
The region of film covering, the migration of silicon atom can occur for other regions（Retained compression film can be used as barrier layer, resistance
Keep off silicon atom migration）, thus can improve in respective direction to the tensile stress of raceway groove.In addition,（DTE）High temperature in processing procedure
The compression of the compression film of reservation can be transferred on the raceway groove of device, thus to pulling up transistor（PMOS）Raceway groove
Length direction additionally applies compression, produces stress memory technique（SMT）Effect, further improve the performance of PMOS；It is and right
Transmission gate transistor（NMOS）The compression that applies of channel width dimension, then can reduce the performance of transmission gate transistor.
Due to pull-down transistor（PD）Performance it is elevated, transmission gate transistor（PG）Performance be lowered, thus SRAM
β ratios（βratio）It is enhanced, therefore the stability of SRAM can be improved and read static noise allowance（RSNM）, Jin Erti
The performance of high semiconductor devices.Further, since the performance to pull up transistor is elevated at the same time, therefore it can further improve and partly lead
The performance of body device.
In this embodiment, it is preferred that DTE processing is carried out under the annealing conditions of hydrogen.Surrounding environment preferably includes
Other gases, for example, nitrogen, helium, neon, argon, krypton, xenon and combinations of the above.Air pressure preferably in the range of about 1 support between 1000 supports,
More preferably between about 1 support between 300 supports.The temperature control of DTE processing is between 700-1200 DEG C, more preferably between about
Between 900-1100 DEG C.The time of DTE processing lasts about 5 to 120 seconds.
In the present embodiment, can also replace with compression film 102 common cannot apply the thin of stress to raceway groove
Film, can not apply compression by SMT technologies to raceway groove at this time, but still can stop the migration of silicon atom in DTE techniques, press down
The effect for making and avoiding the tensile stress of DTE techniques to strengthen.
Step A5：The compression film 102 ' retained is removed, as shown in Figure 4 E.
Exemplarily, minimizing technology can be wet method stripping or dry etching etc..
So far, the introduction of the committed step of the embodiment of the present invention is completed.It is to be understood that in the above-mentioned of the present embodiment
In description, PU, PD, PG refer both to intend PU, PD, the PG formed, these devices will be formed in subsequent step.Here directly it is referred to as
PU, PD, PG, are in order at and state brief consideration.
After step A5, the step of can also including forming PU, PD, PG and other assemblies, correlation step can join
Realized according to the prior art, details are not described herein again.
The manufacture method of the semiconductor devices of the present invention, by setting diffusion impervious layer（Refer to the resistance that etching retains afterwards
Barrier）Landform engineering is diffused afterwards（DTE）, can improve and pull up transistor with the performance of pull-down transistor, holding even
The performance of transmission gate transistor is reduced, so as to improve the β ratios of SRAM, therefore the performance of semiconductor devices can be improved.Also,
By rationally setting diffusion impervious layer, the performance to pull up transistor can be improved at the same time in DTE, partly led so as to further improve
The performance of body device.
Further, which can be the diffusion impervious layer with compression（Compression film）, therefore,
In DTE processing procedures, it can not only stop to pulling up transistor（PMOS）Orientation tensile stress humidification,
And compression can be applied to the orientation to pull up transistor by SMT technologies, further improve and pull up transistor
Performance, further, it is also possible to transmission gate transistor（NMOS）Raceway groove apply compression, further reduce transmission gate transistor
Performance.
Fig. 5 shows a kind of a kind of typical flowchart of the manufacture method for semiconductor devices that the embodiment of the present invention proposes,
For schematically illustrating the typical process of the manufacture method.Specifically include：
Step S101：Semiconductor substrate is provided, defines active area on the semiconductor substrate；
Step S102：Diffusion impervious layer is formed on the semiconductor substrate；
Step S103：The diffusion impervious layer is performed etching, retains the diffusion impervious layer and is located at transmission gate transistor
Channel width dimension part, remove the part that the diffusion impervious layer is located at other regions；
Step S104：Landform project treatment is diffused, is pulled up transistor and the performance of pull-down transistor and guarantor with improving
Hold or even reduce the performance of transmission gate transistor.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
- A kind of 1. manufacture method of semiconductor devices, it is characterised in that the described method includes：Step S101：Semiconductor substrate is provided, defines active area on the semiconductor substrate, the active area is used to make SRAM device, the SRAM device include pull-down transistor and transmission gate transistor, the pull-down transistor and the transmission gate Transistor is nmos device；Step S102：Diffusion impervious layer is formed on the semiconductor substrate；Step S103：The diffusion impervious layer is performed etching, retains the ditch that the diffusion impervious layer is located at transmission gate transistor The part of road width, removes the part that the diffusion impervious layer is located at other regions；Step S104：Landform project treatment is diffused, to improve the performance of pull-down transistor and reduce transmission gate transistor Performance.
- 2. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that the SRAM device further includes pull-up Transistor, it is described to pull up transistor as PMOS device, in the step S103, also retain the diffusion impervious layer positioned at pull-up The part of the orientation of transistor.
- 3. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that described in the step S102 Diffusion impervious layer is compression film；Also, in the step S104, while landform project treatment is diffused, institute The compression for stating the part that diffusion impervious layer is retained is transferred to the channel width dimension of transmission gate transistor.
- 4. the manufacture method of semiconductor devices as claimed in claim 2, it is characterised in that described in the step S102 Diffusion impervious layer is compression film；Also, in the step S104, while landform project treatment is diffused, institute The compression for stating the part that diffusion impervious layer is retained is transferred to the channel width dimension of transmission gate transistor and upper crystal pulling The orientation of body pipe.
- 5. the manufacture method of the semiconductor devices as described in claim 3 or 4, it is characterised in that in the step S102, institute The material for stating compression film is compression silicon nitride.
- 6. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that described in the step S104 Diffusion landform project treatment carries out under the annealing conditions of hydrogen.
- 7. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that described in the step S104 The duration for spreading landform project treatment is 5-120 seconds.
- 8. the manufacture method of semiconductor devices as claimed in claim 1, it is characterised in that also wrapped after the step S104 Include step S105：Remove the part that the diffusion impervious layer is retained.
- 9. the manufacture method of semiconductor devices as claimed in claim 8, it is characterised in that in the step S105, remove Method is peeled off for wet method used by the part that the diffusion impervious layer is retained.
- 10. the manufacture method of semiconductor devices as claimed in claim 8, it is characterised in that after the step S105 also Including step S106：Formed in the active area pull up transistor, pull-down transistor and transmission gate transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410138464.9A CN104979293B (en) | 2014-04-08 | 2014-04-08 | A kind of manufacture method of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410138464.9A CN104979293B (en) | 2014-04-08 | 2014-04-08 | A kind of manufacture method of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104979293A CN104979293A (en) | 2015-10-14 |
| CN104979293B true CN104979293B (en) | 2018-05-04 |
Family
ID=54275677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410138464.9A Active CN104979293B (en) | 2014-04-08 | 2014-04-08 | A kind of manufacture method of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104979293B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878425B (en) * | 2017-05-09 | 2021-09-03 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038920A (en) * | 2006-03-17 | 2007-09-19 | 台湾积体电路制造股份有限公司 | Semiconductor structures and its forming method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7605447B2 (en) * | 2005-09-22 | 2009-10-20 | International Business Machines Corporation | Highly manufacturable SRAM cells in substrates with hybrid crystal orientation |
| KR100707612B1 (en) * | 2005-12-29 | 2007-04-13 | 동부일렉트로닉스 주식회사 | Sram device and manufacturing method thereof |
-
2014
- 2014-04-08 CN CN201410138464.9A patent/CN104979293B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038920A (en) * | 2006-03-17 | 2007-09-19 | 台湾积体电路制造股份有限公司 | Semiconductor structures and its forming method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104979293A (en) | 2015-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| SG143263A1 (en) | A method for engineering hybrid orientation/material semiconductor substrate | |
| JP2005522034A (en) | Semiconductor device formed on buried oxide film having a plurality of thicknesses and manufacturing method thereof | |
| TW200644257A (en) | Self-aligned STI SONOS | |
| KR0168194B1 (en) | Method for forming isolation film on a semiconductor device | |
| US20130280871A1 (en) | Semiconductor device and method of fabricating the same | |
| JP2004327493A (en) | Semiconductor device and its manufacturing method | |
| CN104979293B (en) | A kind of manufacture method of semiconductor devices | |
| US5286672A (en) | Method for forming field oxide regions | |
| JP2007281027A (en) | Semiconductor device and its manufacturing method | |
| US8691643B2 (en) | Methods of forming semiconductor devices | |
| KR20080002485A (en) | Mehtod for manufacturing bonded soi wafer | |
| CN104979208B (en) | A kind of manufacture method of semiconductor devices | |
| WO2013132766A1 (en) | Method for manufacturing semiconductor device | |
| KR100613371B1 (en) | Semiconductor device and method of manufacturing the same | |
| JPWO2006092848A1 (en) | Semiconductor device and manufacturing method thereof | |
| JP3061025B2 (en) | Method for manufacturing semiconductor device | |
| JP2003324195A (en) | Semiconductor device and method for manufacturing the same | |
| US7488647B1 (en) | System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device | |
| KR100521439B1 (en) | Method for fabricating the p-channel MOS transistor | |
| KR101348400B1 (en) | Gate-Oxide Manufacturing Method of Semiconductor Device | |
| KR100280813B1 (en) | Device Separator Formation Method of Semiconductor Device | |
| JP2004095645A (en) | Semiconductor device and method of manufacturing the same | |
| US6875647B2 (en) | Method of manufacturing semiconductor devices to protect against a punchthrough phenomenon | |
| JPS6059777A (en) | Manufacture of semiconductor device | |
| US7494879B2 (en) | Method for forming a gate insulating layer of a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |