CN104979206B - The forming method of transistor - Google Patents
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- CN104979206B CN104979206B CN201410136263.5A CN201410136263A CN104979206B CN 104979206 B CN104979206 B CN 104979206B CN 201410136263 A CN201410136263 A CN 201410136263A CN 104979206 B CN104979206 B CN 104979206B
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Abstract
The present invention provides a kind of forming method of transistor, including：Substrate is provided；Multiple pseudo- grid structures are formed over the substrate and use fluid chemistry vapour deposition process, and first medium layer is filled between dummy gate structure, first medium layer is less than dummy gate structure；Second dielectric layer is formed in dummy gate structure and first medium layer, the compactness of the second dielectric layer is higher than the compactness of the first medium layer；The pseudo- grid in pseudo- grid structure are removed, form opening；Metal gates are formed in said opening.The first medium layer of fluid chemistry vapour deposition process filling initially has mobility, can preferably it be filled between pseudo- grid structure, not and the defects of not allowing to be also easy to produce gap, the hardness of second dielectric layer and anti-etching ability are stronger, second dielectric layer can keep preferable pattern in the forming process of metal gates afterwards, so that can subsequently form the more unified metal gates of height, ensure the quality of transistor.
Description
Technical field
The present invention relates to semiconductor applications, and in particular to a kind of forming method of transistor.
Background technology
In high K dielectric/rear metal gate engineering of transistor, formed on substrate after multiple pseudo- grid structures, it is necessary to
Interlayer dielectric layer is filled between multiple puppet grid structures, after pseudo- grid are removed, interlayer dielectric layer is formed with corresponding pseudo- grid shape
Opening, fills metal gates, to form high K dielectric/rear metal-gate structures in the opening.
With the continuous improvement of the transistor density on integrated circuit, between the sizes of metal gates, metal gates between
Away from also constantly reducing, correspondingly the spacing of pseudo- grid structure also constantly reduces, and interlayer dielectric layer is filled between multiple pseudo- grid structures
During, interlayer dielectric layer is difficult to be filled into the inter-level dielectric in less spacing, so formed between multiple pseudo- grid structures
Layer pattern out-of-flatness, and generation gap is easy in interlayer dielectric layer（void）.
If producing gap in interlayer dielectric layer, easily leakage current is produced so that transistor performance reduces.In addition,
Pattern out-of-flatness, has in the interlayer dielectric layer in gap and fills metal gates, metal gates height may be caused not flush, metal
The defects of penetrating into interlayer dielectric layer void.
Therefore, the filling effect in how improving interlayer dielectric layer between pseudo- grid structure, forms high quality and pattern is put down
Whole interlayer dielectric layer, becomes those skilled in the art's urgent problem to be solved.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of Transistor forming method, interlayer dielectric layer is improved between pseudo- grid structure
Filling effect, form high quality and the smooth interlayer dielectric layer of pattern.
To solve the above problems, the present invention provides a kind of Transistor forming method, including：
Substrate is provided；
Multiple pseudo- grid structures are formed over the substrate, and dummy gate structure includes pseudo- grid；
Source region, drain region are formed in the substrate that dummy gate structure is exposed；
Using fluid chemistry vapour deposition process, first medium layer is filled between dummy gate structure, makes first medium layer
Less than dummy gate structure；
Form second dielectric layer in dummy gate structure and first medium layer, make the surface of the second dielectric layer with
Pseudo- grid surface in pseudo- grid structure flushes, and the compactness of the second dielectric layer is higher than the compactness of the first medium layer；
The pseudo- grid in pseudo- grid structure are removed, form opening；
Metal gates are formed in said opening.
Optionally, the step of first medium layer is filled between dummy gate structure includes:
First medium layer is filled between dummy gate structure using fluid chemistry vapour deposition process, and makes described first to be situated between
Matter floor height is in pseudo- grid structure;
Curing process is carried out to the first medium layer；
The first medium layer after curing process is planarized, first medium layer is flushed with pseudo- grid structure；
First medium layer carve, the first medium layer of segment thickness is removed, is less than remaining first medium layer
Dummy gate structure.
Optionally, first medium layer is filled between dummy gate structure, and makes the first medium floor height in pseudo- grid knot
In the step of structure, the thickness of the first medium layer of filling is in the range of 500 angstroms to 2000 angstroms.
Optionally, the step of first medium layer is less than pseudo- grid structure is made in the first medium layer for removing segment thickness
In, the thickness of the first medium layer removed is in the range of 200 angstroms to 300 angstroms.
Optionally, the step of first medium layer is filled between dummy gate structure using fluid chemistry vapour deposition process
In, the material of the first medium layer is silica.
Optionally, the step of formation first medium layer is carried out in reaction chamber, fills out between dummy gate structure
The step of being filled with the first medium layer that silica is material includes：It is passed through in reaction chamber including front three silicon amine gas, ammonia, hydrogen
The reactant of gas, oxygen and water.
Optionally, the curing process is carried out in reaction chamber, curing process includes：
Ozone is passed through in reaction chamber；
Make the temperature in reaction chamber in the range of 400 degrees Celsius to 600 degrees Celsius, to anneal.
Optionally, the step of carrying out curing process to the first medium layer further includes：After anneal, to reaction chamber
In be passed through oxygen and water.
Optionally, after first medium layer is flushed with pseudo- grid structure, before to first medium layer carve, also wrap
Include：Silicon doping is carried out to the first medium layer.
Optionally, second dielectric layer is formed in dummy gate structure and first medium layer, makes the second dielectric layer
Surface the step of being flushed with the pseudo- grid surface in pseudo- grid structure include:
Using chemical vapour deposition technique, formed and be higher than in the remaining first medium layer surface and pseudo- grid body structure surface
The second dielectric layer of pseudo- grid structure；
Silicon doping is carried out to the second dielectric layer；
The second dielectric layer is planarized, until exposing the surface of pseudo- grid.
Optionally, the higher than pseudo- grid structure is formed in the remaining first medium layer surface and pseudo- grid body structure surface
In the step of second medium layer：The thickness of the second dielectric layer is in the range of 300 angstroms to 500 angstroms.
Optionally, the material of the second dielectric layer is silica.
Optionally, after substrate is provided, formed before pseudo- grid structure, further include and form fin on substrate；
The step of forming multiple pseudo- grid structures over the substrate includes：Formed on the fin multiple across the fin
Pseudo- grid structure.
Compared with prior art, technical scheme has the following advantages：
Using fluid chemistry vapour deposition process, first medium layer, fluid chemistry gas phase are filled between dummy gate structure
The first medium layer of sedimentation filling has good filling capacity, so as to not allow to be also easy to produce when being filled between pseudo- grid structure
The defects of gap, form the second medium flushed with the pseudo- grid in pseudo- grid structure in dummy gate structure and first medium layer
Layer, the compactness of the second dielectric layer are higher than the compactness of the first medium layer so that the hardness of second dielectric layer and anti-
Etching power is stronger, and second dielectric layer can keep preferable pattern in subsequent step afterwards, so that follow-up energy
It is enough to form the more unified metal gates of height, ensure the quality of transistor.
Further, first medium layer is silica, after the first medium layer that filling is flushed with dummy gate structure, is gone
Falling part first medium layer makes the first medium layer be less than before pseudo- grid structure, further includes：The first medium layer is carried out
Silicon adulterates, and the first medium layer hardness and anti-etching ability by silicon doping are stronger, reduce the highly uneven equality of metal gates and lack
Sunken generation, to improve the quality of transistor.
Further, second dielectric layer is silica, and the is formed in the first medium layer surface and pseudo- grid body structure surface
After second medium layer, silicon doping is carried out to the second dielectric layer.So pass through the hardness of the second dielectric layer of silicon doping and resist
Etching power is stronger, the generation of the highly uneven equality defect of metal gates is reduced, to improve the quality of transistor.
Brief description of the drawings
Fig. 1 to Figure 10 is the schematic diagram of each step of one embodiment of Transistor forming method of the present invention.
Embodiment
In existing high K dielectric/rear metal gate engineering in transistor, interlayer dielectric layer is filled between multiple pseudo- grid structures
During, interlayer dielectric layer is difficult to be filled into the inter-level dielectric in less spacing, so formed between multiple pseudo- grid structures
Layer pattern out-of-flatness, and the defects of be easy in interlayer dielectric layer to produce gap.
In order to solve the above technical problem, the present invention provides a kind of Transistor forming method.Sunk using fluid chemistry gas phase
Area method, fills first medium layer, the first medium layer of fluid chemistry vapour deposition process filling is first between dummy gate structure
The defects of beginning has mobility, can preferably be filled between pseudo- grid structure, and not allow to be also easy to produce gap, then removes portion
Divide first medium layer, the second dielectric layer flushed with pseudo- grid structure is formed in dummy gate structure and first medium layer, the
The hardness of second medium layer and anti-etching ability are stronger, and the upper surface of second dielectric layer can keep preferable shape in subsequent step
Looks, it is hereby achieved that the more unified metal gates of height, ensure the quality of transistor.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Referring to figs. 1 to the schematic diagram for each step that Figure 10 is one embodiment of Transistor forming method of the present invention.Need
Bright, in the present embodiment, the transistor is CMOS, but should not therefore limit Transistor forming method institute of the present invention shape
Into transistor types, in other embodiments, Transistor forming method of the present invention can be also used for being formed fin field effect crystalline substance
Body pipe.
With reference to figure 1, there is provided substrate 100.
In the present embodiment, the substrate 100 is silicon substrate, and in other embodiments, the substrate 100 can also be germanium
Other Semiconductor substrates such as silicon substrate or silicon-on-insulator substrate, any restrictions are not done to this present invention.
Specifically, in the present embodiment, NMOS tube and PMOS tube are formed at the same time on the substrate 100, so providing
After substrate 100, it is also necessary to isolation structure 101 is formed in substrate 100, substrate 100 is divided for NMOS substrate zones and PMOS substrates
Area.The isolation structure 101 is fleet plough groove isolation structure, and in other embodiments, the isolation structure can also be local oxygen
Change isolation.The isolation structure 101 is used to isolate NMOS tube and PMOS tube.In other embodiments, can not also be formed described
Isolation structure 101.
With continued reference to Fig. 1, multiple pseudo- grid structures for including pseudo- grid are formed on the substrate 100.In dummy gate structure
Source region, drain region are formed in the substrate 100 exposed.
In the present embodiment, the first pseudo- grid structure of the NMOS tube is formed on the NMOS substrate zones of substrate 100, is being served as a contrast
The PMOS substrate zones at bottom 100 form the second pseudo- grid structure of the PMOS tube.
Wherein, the first pseudo- grid structure includes the first pseudo- grid 140, the first grid dielectric layer positioned at the first pseudo- 140 bottom of grid
150 and the first side wall positioned at the first pseudo- 140 both sides of grid（It is not shown）；Second pseudo- grid structure includes the second pseudo- grid 130, is located at
The second grid dielectric layer 160 of second pseudo- 130 bottom of grid and the second side wall positioned at the second pseudo- 130 both sides of grid（It is not shown）.
Specifically, the first grid dielectric layer 150, the material of second grid dielectric layer 160 are silica, described first
The material of the pseudo- pseudo- grid 130 of grid 140, second is polysilicon, and the material of the side wall is silicon nitride, but the present invention is situated between first grid
The pseudo- grid 130 of the pseudo- grid 140, second of matter layer 150, second grid dielectric layer 160, first, the first side wall, the specific material of the second side wall
It is not limited.
In the present embodiment, the first stress knot is formed in the substrate 100 exposed between the first pseudo- grid structure of NMOS tube
Structure 110, forms the second stress structure 120 in the substrate 100 exposed between the second pseudo- grid structure of PMOS tube, described first should
Power structure 110 is formed using stress germanium silicon, and the second stress structure 120 is formed using carborundum, but the present invention is to the first stress knot
Structure 110, the specific forming method of the second stress structure 120 and material are not limited.
With continued reference to Fig. 1, after the first stress structure 110, the second stress structure 120 is formed, to the first stress structure
110th, the second stress structure 120 is doped, to form NMOS tube, the source region of PMOS tube, drain region.
In the present embodiment, after NMOS tube, the source region of PMOS tube, drain region is formed, in the substrate 100 and first
Pseudo- grid structure, the second pseudo- grid body structure surface form etching barrier layer 102, as the etching barrier layer of subsequent technique, in other realities
Apply in example, the etching barrier layer 102 can not also be formed.
With reference to figure 2, the filling first medium layer 103 between the described first pseudo- grid structure, the second pseudo- grid structure, described first
Dielectric layer 103 is higher than the described first pseudo- grid structure, the second pseudo- grid structure.
In the present embodiment, the first medium layer 103 is formed on 102 surface of etching barrier layer.
Specifically, using fluid chemistry vapour deposition process, filled out between the described first pseudo- grid structure and the second pseudo- grid structure
Fill material and be the first medium layer 103 of silica, and make the first medium layer 103 higher than the described first pseudo- grid structure, second
Pseudo- grid structure.The height of usually puppet grid structure is right in 500 Izods, and therefore, optionally, the thickness of the first medium layer 103 exists
In the range of 500 angstroms to 2000 angstroms.
The principle of fluid chemistry vapour deposition process cvd silicon oxide is used as nitrogenous gaseous matter is passed through reaction chamber
It is interior, then nitrogen therein is displaced by reacting, pure unazotized silicon oxide deposition is changed into and gets off.
Specifically, in the present embodiment, front three silicon amine is passed through in reaction chamber（N(SiH3)3）Gas, ammonia, hydrogen,
The reactant such as oxygen and water
Under low-temperature condition, above-mentioned reactant reacts, the chemical bond rupture of front three silicon amine and the ion and ammonia that are formed
The reaction such as amino and oxonium ion that gas and oxygen produce, forms the intermediate product of mobility, in the intermediate product of the mobility
With amino.The intermediate product of mobility is enough to be preferably filled between pseudo- grid structure, and the defects of do not allow to be also easy to produce gap.
It should be noted that with the progress of reaction, the intermediate product for the mobility being initially formed gradually hardens, that is,
Say, the time that the mobility of intermediate product is kept after deposition is shorter so that intermediate product after the completion of the reaction was complete
With certain degree of hardness.
After completion of the reaction, the hardness of intermediate product also needs to further improve, for intermediate product is converted into solid oxygen
SiClx to intermediate product, it is necessary to carry out curing process.
The curing process includes：Process annealing processing is carried out to the first medium layer 103, in the present embodiment,
It is passed through ozone in reaction chamber, the temperature in reaction chamber is in the range of 400 degrees Celsius to 600 degrees Celsius.After annealing, flow
Amino in the intermediate product of dynamic property is aoxidized, and forms solid material containing silica.
Curing process is further included carries out curing process to the solid material containing silica, in the present embodiment, optionally,
Oxygen and water are passed through in reaction chamber so that the solid material containing silica further aoxidizes, and is converted into solid oxidation
Silicon.
But the present invention is not limited the condition of curing process, and the reactant being passed through in reaction chamber is not also limited
System, in other embodiments, can also use other methods to carry out curing process to the intermediate product of the mobility；Curing
In processing procedure, the temperature in reaction chamber can not also be in the range of 400 degrees Celsius to 600 degrees Celsius.
It should be noted that in the present embodiment, the first medium layer 103 of fluid chemistry vapour deposition process filling is
Silica, but the present invention is not limited the material of the first medium layer 103, in other embodiments, described first is situated between
Other free-flowing materials that the material of matter layer 103 can also be formed by fluid chemistry vapour deposition process.
With reference to figure 3, after curing process is carried out to the silica of the mobility, using chemical mechanical milling method, put down
The smoothization first medium layer 103, makes first medium layer 103 be flushed with the first pseudo- grid structure, the second pseudo- grid structure.
It should also be noted that, in the present embodiment, material is cured and moved back for the first medium layer 103 of silica
After fire, the first silicon doping 201 is carried out to the first medium layer 103 so that the hardness of first medium layer 103 and anti-etching energy
Power further improves.But whether the present invention carries out the first medium layer 103 first silicon doping 201 and be not limited, at it
In his embodiment, the first silicon doping 201 can not also be carried out to the first medium layer 103.
With reference to figure 4, first medium layer 103 carve, removing the first medium layer 103 of segment thickness makes described first
Dielectric layer 103 is less than pseudo- grid structure.
The purpose for removing part first medium layer 103 is, after part first medium layer 103 is removed, using chemistry
Vapour deposition process fills second dielectric layer, and the compactness of second dielectric layer is higher than first medium layer 103, i.e., second dielectric layer is hard
Degree and anti-etching ability are stronger, and preferable pattern can be kept in the forming process of metal gates afterwards.
Specifically, using plasma etching removes the first medium layer 103 of segment thickness.Plasma etching is dry method
One kind of etching, has high etch rate, uniformity and good selective, in other embodiments, can also use it
His dry etch process removes the pseudo- grid.
It should be noted that if the segment thickness that plasma etching removes first medium layer 103 is too small, due to subsequently filling out
The second dielectric layer 104 filled needs and the first pseudo- grid structure is flushed with the second pseudo- grid structure, then the second dielectric layer subsequently filled
104 is excessively thin, it is difficult to plays the role of strengthening hardness and anti-etching ability, if plasma etching removes first medium layer 103
Segment thickness is excessive, then the difficulty that follow-up second dielectric layer 104 is filled between the first pseudo- grid structure and the second pseudo- grid structure increases
Add, it is possible to create the defects of gap.Optionally, the thickness of the first medium layer 103 removed is in the range of 200 angstroms to 300 angstroms.
But the thickness of first medium layer 103 of the present invention to removing is not limited, in other embodiments, with pseudo- grid
The change of structure height and the change of fluid chemistry vapour deposition process technological parameter, the thickness of the first medium layer 103 removed is also
Can not be in the range of 200 angstroms to 300 angstroms.
It should be noted that using the first medium layer 103 being initially formed higher than pseudo- grid structure in the present embodiment, then to first
The method that dielectric layer 103 is planarized so that the height of first medium layer 103 is more smooth, but the present invention does not make this
Limitation, can be by the technique of improving fluid chemistry vapour deposition process so that the silica that fluid chemistry vapour deposition process is formed
Flatness improves, so as to directly form the first medium layer 103 for being less than pseudo- grid structure.
With reference to figure 5, in remaining 103 surface of first medium layer and the first pseudo- grid structure and the second pseudo- grid structure table
Face forms second dielectric layer 104, makes the second dielectric layer 104 higher than the first pseudo- grid structure and the second pseudo- grid structure.
In the present embodiment, the second dielectric layer 104, the second dielectric layer are formed using chemical vapour deposition technique
104 material is silica, and the oxidation compared with 103 compactness higher of first medium layer can be deposited using chemical vapour deposition technique
Silicon, has higher hardness and anti-etching ability, but the present invention is not limited the specific material of second dielectric layer 104,
In other embodiment, the material of the second dielectric layer 104 can also be the other materials such as silicon nitride.
Since the second dielectric layer 104 can all produce in the step of follow-up chemical mechanical grinding, formation metal gates
Raw consumption, and the first medium layer for passing through back quarter step is less than the first pseudo- grid structure with the height of the second pseudo- grid structure 200
Angstrom in the range of 300 angstroms, therefore, optionally, the thickness of second dielectric layer 104 is in the range of 300 to 500 angstroms.But by
Can not also be in the range of 200 angstroms to 300 angstroms, so the present invention is situated between to second in the thickness of the first medium layer 103 removed
The thickness of matter layer 104 is not also limited, and the thickness of second dielectric layer 104 can not also be in the range of 300 to 500 angstroms.
With reference to figure 6, the second silicon doping 202 is carried out to the second dielectric layer 104, to further improve the silica of densification
Hardness and anti-etching ability, but whether the present invention carries out the second silicon 202 to the second dielectric layer 104 is adulterated and is not limited
System, in other embodiments, can not also carry out the second silicon 202 to the first medium layer 103 and adulterate.
With reference to figure 7, using chemical mechanical milling method, the second dielectric layer 104 is planarized, exposes the first pseudo- grid 140, the
The surface of two pseudo- grid 130.But the present invention is not limited the specific method for planarizing the second dielectric layer 104.
With reference to figure 8, the first pseudo- grid 140 in the first pseudo- grid structure are removed, form the first of 140 shape of corresponding first pseudo- grid
Opening 142；The second pseudo- grid 130 in the second pseudo- grid structure are removed, form the second opening 132 of 130 shape of corresponding second pseudo- grid.
Specifically, in the present embodiment, using the dry etching and wet etching carried out successively, remove the first pseudo- grid 140,
Second pseudo- grid 130, first the 142, second opening 132 of opening is formed in the original position of the first pseudo- pseudo- grid 130 of grid 140, second.But
The present invention is not limited the specific method for removing the first pseudo- pseudo- grid 130 of grid 140, second.
In the present embodiment, the material by exposure to the second dielectric layer 104 in etching agent is fine and close silica, is had
There are higher hardness and anti-etching ability, during being performed etching to the first pseudo- pseudo- grid 130 of grid 140, second, fine and close oxygen
SiClx is influenced smaller by etching, and after dry etching and wet etching, second dielectric layer 104 can keep preferable pattern,
So as to be conducive to reduce leakage current, and avoid due to first medium layer 103 other defect caused by over etching；In dry etching
After wet etching, the upper surface of second dielectric layer 104 is more smooth, in actual production, is formed at the same time on wafer more
A PMOS tube, NMOS tube, the high level of homogeneity of so 132 side walls of multiple the 142, second openings of first opening is higher, so that
The height of the metal gates formed in multiple PMOS tube, first the 142, second opening 132 of opening of NMOS tube is more unified.
With reference to reference to figure 9, Figure 10, formed in described first the 142, second opening 132 of opening the first metal gates 143,
Second metal gates 133.
Specifically, diffusion impervious layer 106 is formed in the described first opening 132 inner walls of the 142, second opening, described first
Metal layer 105 is filled in the opening of opening 142, second 132, chemical mechanical grinding then is carried out to the metal layer 105, removes the
Metal layer 105 and diffusion impervious layer 106 on second medium layer 104, retain in first the 142, second opening 132 of opening
Metal layer 105, forms the first metal gates 143, the second metal gates 133.
It should be noted that in the present embodiment, after chemical mechanical grinding is carried out to the metal layer 105, still
The second dielectric layer 104 of remainder thickness, because the anti-etching ability and hardness of second dielectric layer 104 are higher, to described
The upper surface of second dielectric layer 104 is more smooth after the progress chemical mechanical grinding of metal layer 105, the first metal gates of formation
143rd, the height of the second metal gates 133 is more unified.During actual fabrication, due to carrying out chemistry to the metal layer 105
The first metal gates 143 for being formed after mechanical lapping, the height of the second metal gates 133 can generally be less than the first pseudo- grid 140,
The height of second pseudo- grid 130, the present invention is not also construed as limiting the thickness of second dielectric layer 104, therefore, to the metal layer 105
Lucky second dielectric layer 104 may be completely consumed by carrying out chemical mechanical grinding, i.e. the first metal gates 143, the second metal gate
First medium layer 103 is only existed between pole 133, therefore, the present invention is to forming the first metal gates 143, the second metal gates 133
After, do not limited with the presence or absence of second dielectric layer 104 between the first metal gates 143, the second metal gates 133.Need
It is bright, during carrying out chemical mechanical grinding to the metal layer 105, it should avoid being ground to first medium layer as far as possible
103。
By above-mentioned steps, that is, form nmos pass transistor and PMOS transistor that forming method of the present invention is formed.
It should be noted that the forming method of transistor of the present invention can be also used for forming fin formula field effect transistor, with
Above-described embodiment difference is, after substrate is provided, is formed before pseudo- grid structure, further includes and form fin on substrate；
The step of forming multiple pseudo- grid structures over the substrate includes：Multiple pseudo- grid knots across the fin are formed on the fin
Structure.Subsequent step is identical with the forming method of CMOS, and details are not described herein, and the present embodiment can improve fin formula field effect transistor
Improve the filling capacity of interlayer dielectric layer, reduce defect, improve the performance of fin formula field effect transistor.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (12)
- A kind of 1. forming method of transistor, it is characterised in that including：Substrate is provided；Multiple pseudo- grid structures are formed over the substrate, and dummy gate structure includes pseudo- grid；Source region, drain region are formed in the substrate that dummy gate structure is exposed；Using fluid chemistry vapour deposition process, first medium layer is filled between dummy gate structure, is less than first medium layer Dummy gate structure；Second dielectric layer is formed in dummy gate structure and first medium layer using chemical vapour deposition technique, so that described The compactness of second dielectric layer is higher than the compactness of the first medium layer；Silicon doping is carried out to the second dielectric layer, to further improve the hardness of second dielectric layer and anti-etching ability；After carrying out silicon doping, the second dielectric layer is planarized, makes the surface of the second dielectric layer and the puppet in pseudo- grid structure Grid surface flushes；The pseudo- grid in pseudo- grid structure are removed, form opening；Metal gates are formed in said opening.
- 2. forming method as claimed in claim 1, it is characterised in that first medium layer is filled between dummy gate structure Step includes:First medium layer is filled between dummy gate structure using fluid chemistry vapour deposition process, and makes the first medium layer Higher than pseudo- grid structure；Curing process is carried out to the first medium layer；The first medium layer after curing process is planarized, first medium layer is flushed with pseudo- grid structure；First medium layer carve, removes the first medium layer of segment thickness, makes remaining first medium layer less than described Pseudo- grid structure.
- 3. forming method as claimed in claim 2, it is characterised in that first medium layer is filled between dummy gate structure, And making the first medium floor height in the step of pseudo- grid structure, the thickness of the first medium layer of filling is arrived at 500 angstroms In the range of 2000 angstroms.
- 4. forming method as claimed in claim 2, it is characterised in that make described in the first medium layer for removing segment thickness One dielectric layer was less than in the step of pseudo- grid structure, and the thickness of the first medium layer removed is in the range of 200 angstroms to 300 angstroms.
- 5. forming method as claimed in claim 2, it is characterised in that using fluid chemistry vapour deposition process in the pseudo- grid knot In the step of first medium layer is filled between structure, the material of the first medium layer is silica.
- 6. forming method as claimed in claim 5, it is characterised in that in reaction chamber to be formed the step of first medium layer Suddenly, filling is included using the step of first medium layer of the silica as material between dummy gate structure：It is passed through in reaction chamber Include the reactant of front three silicon amine gas, ammonia, hydrogen, oxygen and water.
- 7. forming method as claimed in claim 6, it is characterised in that the curing process is carried out in reaction chamber, is cured Processing includes：Ozone is passed through in reaction chamber；Make the temperature in reaction chamber in the range of 400 degrees Celsius to 600 degrees Celsius, to anneal.
- 8. forming method as claimed in claim 7, it is characterised in that the step of curing process is carried out to the first medium layer Further include：After anneal, oxygen and water are passed through into reaction chamber.
- 9. forming method as claimed in claim 2, it is characterised in that after first medium layer is flushed with pseudo- grid structure, Before to first medium layer carve, further include：Silicon doping is carried out to the first medium layer.
- 10. forming method as claimed in claim 1, it is characterised in that using chemical vapour deposition technique in dummy gate structure And in the step of on first medium layer forming second dielectric layer, the model of the thickness of the second dielectric layer at 300 angstroms to 500 angstroms In enclosing.
- 11. forming method as claimed in claim 1, it is characterised in that the material of the second dielectric layer is silica.
- 12. forming method as claimed in claim 1, it is characterised in that after substrate is provided, formed multiple pseudo- grid structures it Before, further include and form fin on substrate；The step of forming multiple pseudo- grid structures over the substrate includes：Multiple pseudo- grid across the fin are formed on the fin Structure.
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| US8685867B1 (en) * | 2010-12-09 | 2014-04-01 | Novellus Systems, Inc. | Premetal dielectric integration process |
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