CN104979177B - Grid structure and preparation method thereof - Google Patents
Grid structure and preparation method thereof Download PDFInfo
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Abstract
The present invention provides a kind of grid structure and preparation method thereof, including：Substrate, the first metal layer and second metal layer are provided；First processing is carried out to the first metal layer of the first opening；Second processing is carried out to the second metal layer in the second opening；Form metal gates.The present invention also provides a kind of grid structure, including substrate, the work function in the first opening are less than the first metal layer positioned at second, third work function being open, the work function in the second opening is higher than the second metal layer of the work function in the first, the 3rd opening；Metal gates.The beneficial effects of the present invention are, first, second metal level of certain openings is handled, to adjust in the certain openings work function of first or second metal layer, do not need additional coverage or stack new metal level to change the work function after superposition, both saved space and in turn simplify step, also as far as possible avoid additional coverage or laminated metal layer therewith it is issuable covering defect the problem of.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of grid structure and preparation method thereof.
Background technology
With the continuous progress of semiconductor technology, the characteristic size of semiconductor devices tapers into.And semiconductor devices is special
Tapering into for size of sign proposes higher requirement to semiconductor fabrication process.
By taking complementary metal oxide semiconductor (CMOS) device as an example, with the reduction of the size of device in itself, in order to suitable
This change is answered, starts to form metal gates using rear grid (gate last) metal gate process in the prior art, to obtain performance
More preferably grid.This technique generally first forms pseudo- grid (dummy gate) on substrate, and is defined by the pseudo- grid
Source-drain area；After source-drain area is formed, the layer of dielectric material that can expose pseudo- grid is formed on substrate；Remove pseudo- grid afterwards, and
Remove in the opening after pseudo- grid and form metal gates.
At the same time, in order to which the trend reduced with the size of metal gates matches, the equivalent oxide of gate dielectric material layer
Thickness degree (equivalent oxide thickness, EOT) is also required to reduce (scale down) according to a certain percentage, this meaning
The manufacture difficulty that taste gate dielectric material layer is also increasing.
In addition, when making cmos device, in order that cmos device has more flexible threshold voltage (VT), that is,
Make PMOS device different in cmos device or nmos device that there are a variety of different threshold voltages (multi-VT).With PMOS
Exemplified by device, it is common practice to after the pseudo- grid of PMOS device removal form multiple openings, pass through photoresist or other screenings
Cap rock covers different piece opening, so as to form different metal layer in the not covered opening of another part, and then not
With the stacked structure that formation different metal layer is formed in opening, and metal gates are formed on the stacked structure, to be formed
PMOS.The stacked structure that different metal layer is formed has different work functions, so as to so that the PMOS formed threshold voltage
Also it is different.
But above-mentioned method need repeatedly to be formed covering layer (such as：Photoresist) with multiple laminated metal in the opening
Layer.Not only step is complicated for this method, and requires also higher to the covering performance of covering layer and metal level, is actually manufacturing
Operation difficulty in journey increases considerably.Further, it is more prone to produce during covering layer or metal level is formed to lack
Fall into, for example, laminated metal layer can make the depth-to-width ratio of opening become big, so as to cause follow-up metal level or covering layer in the opening
Covering difficulty further increase, the coverage effect in the opening such as follow-up metal level or metal gates easily occurs not
It is good, or even produce the situation of defect.When forming metal level, the covering such as space defect is produced because coverage effect is bad.This
Outside, in the case of gate dielectric material layer is formed using the method for deposition, this method needs multiple covering layer to cover not
Same opening, operating process will become comparatively laborious and complicated, and the difficulty using the threshold voltage of above method adjusting device increases
Greatly.In addition, laminated metal layer can also occupy certain spatial volume repeatedly.Therefore, how to simplify manufacturing step, with relatively simple
Ground forms the device of multi-Vt, and turning into those skilled in the art needs to solve the problems, such as.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of grid and preparation method thereof, with relatively simple form multi-Vt
Device.
To solve the above problems, the present invention provides a kind of preparation method of grid structure, including：
Substrate is provided；
Layer of dielectric material and multiple pseudo- grid structures in layer of dielectric material are formed over the substrate；
Pseudo- grid structure is removed, is formed and is located in interlayer dielectric layer and exposes multiple openings of the substrate, it is the multiple to open
Mouth includes：For forming the first opening of the first semiconductor devices, for forming the second opening of the second semiconductor devices, it is used for
Form the 3rd opening of the 3rd semiconductor devices；
The first metal layer is formed respectively in the described first opening, the second opening and the 3rd opening；
First processing is carried out to the first metal layer in the described first opening, the first metal layer after being handled with formation is described
The work function of the first metal layer is less than the work function of the first metal layer in the second opening and the 3rd opening after processing；
After the step of first is handled, the first metal layer, the second opening and the after the processing in the described first opening
Second metal layer is formed respectively on the first metal layer in three openings；
The second metal layer progress second processing being pointed in second opening, second metal layer after being handled with formation,
The work function of second metal layer is more than the work function of the first opening and the second metal layer in the 3rd opening after the processing；
In second metal layer after processing in the described second opening in second metal layer, the first opening and the 3rd opening
Metal gates are formed respectively.
Optionally, the material of the first metal layer is tantalum, or the compound of tantalum.
Optionally, the material of the first metal layer is tantalum, tantalum nitride or calorize tantalum.
Optionally, the step of forming the first metal layer includes, using chemical vapor deposition, physical vapour deposition (PVD) or atom
Layer deposition forms the first metal layer.
Optionally, the step of forming the first metal layer includes, and makes scope of the thickness of the first metal layer at 5~20 angstroms
It is interior.
Optionally, the step of carrying out the first processing to the first metal layer includes：It is right in the mixed gas of oxygen and nitrogen
The first metal layer is heat-treated.
Optionally, the step of carrying out the first processing to the first metal layer includes：The mixing ratio of the oxygen and nitrogen is set to exist
1:1~1:In the range of 50, and make temperature during heat treatment in the range of 400~1000 degrees Celsius.
Optionally, the heat treatment uses rapid thermal oxidation, spike annealing or laser annealing.
Optionally, the step of forming second metal layer includes：Formation material is titanium nitride, the of ramet or molybdenum nitride
Two metal levels.
Optionally, the step of carrying out second processing to second metal layer includes：In the mixed gas of oxygen and nitrogen or
The second metal layer is heat-treated in the mixed gas of ammonia and nitrogen, or, using Nitrogen ion to described second
Metal level carries out Ions Bombardment processing.
Optionally, the mixing ratio of the oxygen and nitrogen is made 1:1~1:In the range of 50, and make annealing temperature 400
In the range of~1000 degrees Celsius.
Optionally, the mixing ratio of the ammonia and nitrogen is made 1:1~20:In the range of 1, and make annealing temperature 400
In the range of~1000 degrees Celsius.
Optionally, the heat treatment uses rapid thermal oxidation, spike annealing or laser annealing.
Optionally, during the Nitrogen ion bombardment second metal layer, make the flow of nitrogen every in 4000~15000 standard milliliters
Point, and make temperature below 400 degrees Celsius；The power of Ions Bombardment equipment is below 1000 watts.
Optionally, after the step of forming multiple openings, before the step of forming the first metal layer, in addition to following step
Suddenly：
Gate dielectric material layer, high K are sequentially formed on the substrate that the described first opening, the second opening and the 3rd opening are exposed
Layer of dielectric material and cap.
Optionally, after the step of forming the first metal layer, the first metal layer in the first opening is carried out at first
Before the step of reason, in addition to：First be covered on the first metal layer is formed in the described second opening, the 3rd opening
Sacrifice layer, with first handle during block the second opening and the 3rd opening in the first metal layer；
To first opening in the first metal layer carry out first processing the step of after, formed second metal layer the step of it
Before, in addition to：Remove first sacrifice layer；
After the step of forming second metal layer, before the step of second metal layer progress second processing, in addition to：
The second sacrifice layer being covered in the second metal layer is formed in the described first, the 3rd opening, with the mistake of second processing
The second metal layer in the first opening and the 3rd opening is blocked in journey；
To second metal layer carry out second processing the step of after, formed metal gates the step of before, in addition to：Go
Except second sacrifice layer.
Optionally, the step of forming metal gates includes：Using chemical vapor deposition or physical vapour deposition (PVD), aluminium is formed
Or the metal gates of tungsten material.
In addition, the present invention also provides a kind of grid structure, including：
Substrate；
Interlayer dielectric layer on the substrate, it is provided with the interlayer dielectric layer and exposes the multiple of the substrate and open
Mouthful, the multiple opening includes：For forming the first opening of the first semiconductor devices, for forming the second semiconductor devices
Second opening, for forming the 3rd opening of the 3rd semiconductor devices；
The first metal layer being formed in second opening, the 3rd opening, the processing being formed in first opening
The first metal layer afterwards, the work function of the first metal layer is less than the first metal layer in the second opening and the 3rd opening after the processing
Work function；
It is formed at after being handled in the first opening on the first metal layer, the second metal in the 3rd opening on the first metal layer
Layer, it is formed at second metal layer after the processing in second opening on the first metal layer, second metal layer after the processing
Work function is more than the work function of second metal layer in the first opening and the 3rd opening；It is formed at the after being handled in second opening
Metal gates in two metal levels, the first opening in second metal layer and in the 3rd opening in second metal layer.
Optionally, the material of the first metal layer includes：Tantalum, tantalum nitride or calorize tantalum.
Optionally, the material of the second metal layer includes：Titanium nitride, ramet or molybdenum nitride.
Compared with prior art, technical scheme has advantages below：
By forming the first metal layer, and the first metal layer being pointed in the first opening carries out the first processing to reduce
Work function of the first metal layer in the first opening is stated, and the second metal layer being pointed in the second opening carries out second processing, with
Improve the work function of the second metal layer in the second opening so that positioned at first, second and the 3rd in opening the
One metal level and second metal layer it is superimposed work function it is different, so as to obtain the device of multi-Vt.The present invention
Directly the first metal layer in the first selected opening, the second metal layer in the second opening are handled, are located at adjustment
In selected opening first or second metal layer work function, then form metal gates, it is not necessary to which additional coverage stacks new
Metal level change work function, not only simplified step but also save space, decreased additional coverage or the production of laminated metal layer
The problem of raw covering defect.
Further, using tantalum, or material of the compound as the first metal layer of tantalum, the first metal layer may be used also
Using the diffusion impervious layer after metal gates are formed as metal gates, without re-forming one layer of diffusion impervious layer, further letter
Processing step is changed.
Brief description of the drawings
Fig. 1 to Fig. 7 be grid structure of the present invention the embodiment of preparation method one in each step structural representation.
Embodiment
In the prior art, when making the cmos device with multi-Vt, typically removing pseudo- grid to be formed
After forming the opening of metal gates, using the covering layer covering part opening such as photoresist, and in not covered opening
Middle covering metal level, by covering different openings and every time covering different metal layer every time, to be formed respectively in different openings
Different laminated metal layers, and then make the transistor to be formed that there is different threshold voltages.
But work function is adjusted by way of above-mentioned laminated metal layer to be needed to be concatenated to form and remove covering layer, this meeting
Cause manufacturing process's step increase and the increase of technology difficulty
In order to solve the technical problem, the present invention provides a kind of preparation method of grid, including：Substrate is provided；Institute
State and layer of dielectric material and multiple pseudo- grid structures in layer of dielectric material are formed on substrate；Pseudo- grid structure is removed, forms position
In interlayer dielectric layer and expose multiple openings of the substrate, first is open and is led for forming the first half in the multiple opening
Body device, second is open for forming the second semiconductor devices, and the 3rd is open for forming the 3rd semiconductor devices；Described
The first metal layer is formed respectively in one opening, the second opening and the 3rd opening；To the first metal layer in the described first opening
Carry out the first processing, the first metal layer after being handled with formation；The work function of the first metal layer is less than the second opening after the processing
With the work function of the first metal layer in the 3rd opening；After the step of first is handled, after the processing in the described first opening
Second metal layer is formed respectively on the first metal layer in the first metal layer, the second opening and the 3rd opening；It is pointed to described
Second metal layer in two openings carries out second processing, second metal layer after being handled with formation；Second metal layer after the processing
Work function be more than first opening and the 3rd opening in second metal layer work function；After processing in the described second opening
Metal gates are formed respectively in second metal layer in second metal layer, the first opening and the 3rd opening.
By above-mentioned steps, directly first and second metal layer of selected opening are handled, with adjustment positioned at choosing
In fixed opening first or second metal layer work function, then form metal gates, have the cmos device to be formed to reach
There is the purpose of multiple threshold voltages, it is not necessary to which additional coverage stacks new metal level to change the work function after superposition, both saves
Space is saved and in turn simplify step, while also avoided additional coverage or laminated metal layer as far as possible issuable covering lacks therewith
The problem of falling into.
The specific embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.The making side of the present embodiment grid structure
Method includes：
Substrate is provided, the substrate includes the first area for the first PMOS device of formation, for forming second
The second area of PMOS device and the 3rd region for forming the 3rd PMOS device.
Then, cover layer of dielectric material on the active area of the PMOS device, and first area, second area and
Pseudo- grid structure is formed in the layer of dielectric material in the 3rd region respectively.
With reference to figure 1, dummy gate structure is removed, with the dielectric material of first area, second area and the 3rd region
First opening the 30, second opening 20 and the 3rd opening 10 for exposing the substrate are formed in layer (not shown) respectively.Institute
The opening 10 of the first opening 30, second opening 20 and the 3rd is stated to be used to form the metal gates in subsequent steps.Wherein,
First opening 30 is used for the metal gates for forming the first PMOS device, and second opening 20 is used to form the 2nd PMOS devices
The metal gates of part, the 3rd opening 10 are used for the metal gates for forming the 3rd PMOS device.First PMOS device, second
PMOS device and the 3rd PMOS device have different threshold voltages.
In the present embodiment, also on the substrate 40 that described first opening the 30, second opening 20 and the 3rd opening 10 are exposed
Sequentially form：
Gate dielectric material layer (IL layer) 50, in the present embodiment, the gate dielectric material layer 50 are made using oxide
For material, and obtained, can also be by chemical vapor deposition, physics gas by the oxidation reaction of thermal oxide or chemical mode
Mutually deposition or ald obtain, and this is not limited by the present invention.Further, in the present embodiment, the gate medium material
The thickness of the bed of material 50 is 5~10 angstroms, such to be advantageous in that, gate dielectric material layer 50 is had preferable isolation, while not
The overall structure of PMOS device is influenceed as blocked up.
High K dielectric material layer 60, in the present embodiment, the high K dielectric material layer 60 can use as LaO, AlO,
BaZrO、HfZrO,HfZrON、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3
(BST)、Al2O3、Si3N4Or nitrogen oxides etc. is used as material.Meanwhile chemical vapor deposition, physical vapour deposition (PVD) can be passed through
Or ald obtains the high K dielectric material layer 60, this is not limited by the present invention.Further, in order that the high K
Layer of dielectric material 60 is unlikely to excessively thin so that it cannot play a role, and is unlikely to the blocked up structure for causing to influence PMOS device again,
The thickness of high K dielectric material layer 60 in the present embodiment is in the range of 10~30 angstroms.
Cap (cap layer) 70, the cap 70, which is mainly used in improving, includes mobility, electrical and grid can
By the device performance of property etc..In the present embodiment, the cap 70 can use such as La2O3、AL2O3,Ga2O3,In2O3,MoO,
Pt,Ru,TaCNO,Ir,TaC,MoN,WN,TixN1-xDeng being used as material, and by chemical vapor deposition, physical vapour deposition (PVD) or
Person's ald obtains.This is not limited by the present invention.Further, in order that cap 70 be unlikely to it is excessively thin so that it cannot
Play a role, be unlikely to the blocked up structure for causing to influence PMOS device, the scope of the thickness of the cap 70 at 5~20 angstroms again
It is interior.
With reference to figure 2 (substrate is not drawn into Ben Tu and follow-up accompanying drawing), in described first the 30, second opening 20 of opening
And the 3rd opening 10 in form the first metal layer 80 respectively.The first metal layer 80 is used for selectivity in subsequent steps
Ground is processed to adjust the work function of different openings.
Specifically, in the present embodiment, using material of the tantalum as the first metal layer 80.The first of the tantalum material
Metal level 80 is used to carry out work function adjustment subsequently through the first processing, while the first metal layer 80 of the tantalum material may be used also
For use as the diffusion impervious layer of metal gates, that is to say, that when the grid is formed in subsequent step, it is not necessary to extra shape again
Diffusion impervious layer into layer of metal layer as metal gates, this simplifies technological process to a certain extent.
But the present invention is not restricted to the material of the first metal layer 80, in other embodiments of the invention, the first gold medal
Belong to the compound that layer 80 can also use tantalum, such as the other materials such as tantalum nitride or calorize tantalum, it is of the invention without limitation.
Accordingly, in order that the first metal layer 80 is unlikely to excessively thin and does not have adjustment work function and prevents diffusion
Effect, while in order that the first metal layer 80 is unlikely to the blocked up structure for having influence on whole PMOS device, in the present embodiment
In, make the thickness of the first metal layer 80 in the range of 5~20 angstroms.
Specifically, first gold medal can be formed using chemical vapor deposition, physical vapour deposition (PVD) or ald
Belong to layer 80, the present invention is not construed as limiting to the concrete technology for forming the first metal layer 80.
In the present embodiment, before next step is performed also include it is following step by step：
Formed in described first opening the 30, second opening 20 and the 3rd opening 10 and be covered in the first metal layer 80
On first sacrifice layer 90C, 90B and 90A；It is such to be advantageous in that, can be subsequently to the first oxygen in the first opening 30
When changing the first processing of progress of layer 80, protect the first metal layer 80 of second, third opening 20,10 as far as possible unaffected.
In order that described first sacrifice layer 90A, 90B and 90C relatively good first opening 30, second that is filled in is opened
In the opening 10 of mouth 20 and the 3rd, do not influenceed by follow-up annealing steps as far as possible and be easy to be stripped (strip), in this implementation
In example, the material such as non-crystalline silicon, amorphous carbon as first sacrifice layer 90A, 90B and 90C can be used, but it is of the invention
This is not restricted, such as DUO (DUV Light Absorbing Oxide) etc. can also be used as the first sacrifice layer as described
90A, 90B and 90C material.
As shown in Fig. 2 after first sacrifice layer 90A, 90B and 90C is formed, also the first sacrifice layer 90A,
Photoresist layer 41 is covered on 90B and 90C
The graphical photoresist layer 41 is to expose the first sacrifice layer 90C of the first opening 30；And removed by etching
The first sacrifice layer 90C, the first metal layer 80 in the first opening 30 can be exposed.Now, described in the present embodiment
One metal level 80 can also play a part of etching barrier layer during etching removes the first sacrifice layer 90C.
It should be noted that the present invention is not also limited described first sacrifice layer 90A, 90B and 90C lithographic method
System, the methods of dry etching or wet etching can be taken according to actual conditions.
With reference to figure 3, the first metal layer 80 being pointed in first opening 30 carries out the first processing, after being handled with formation
The first metal layer；And then reduce the work function of the first metal layer 80 in the first opening 30.That is, first after processing
The work function of metal level is less than the work function of the first metal layer 80 in the second opening 20 and the 3rd opening 30.
The purpose of this step is open in the work function for making to be located at the first metal layer 80 in the first opening 30 relative to second
20 and the 3rd the first metal layer 80 in opening 10 decrease, and work function is lower, and threshold voltage is higher, so follow-up
The step of in formed metal gates after, positioned at first opening 30 metal gates threshold voltage relative to second opening 20 and
The threshold voltage highest of metal gates in 3rd opening 10, that is, form the first PMOS device of high threshold voltage (HVT).
In the present embodiment, the first metal layer is heat-treated in the mixed gas 31 of oxygen and nitrogen, with
The first processing is carried out to the first metal layer 80.Wherein, oxygen is used as reacting gas in the first processing, in the oxygen
A part of oxygen atom mixes the surface of the first metal layer 80, and the nitrogen is the protective gas for dilution oxygen.
Wherein, in order that the content of the oxygen is enough to the processing of the first metal layer 80 progress first, while in order to
Make the oxygen unlikely excessive and cause the first metal layer 80 too to be aoxidized, or have excessive oxygen atom incorporation described first
Metal level 80 and influence the equivalent oxide thickness (EOT) of gate dielectric material layer, in the present embodiment, oxygen proportion should
More than the ratio of nitrogen, specifically, the mixing ratio of oxygen and nitrogen (gas flow ratio) can be 1:1~1:In the range of 50.
Meanwhile in order that temperature enough carry out first processing, cause to impact PMOS device without regard to too high,
In the present embodiment, temperature during heat treatment is made to be maintained in the range of 400~1000 degrees Celsius.
In addition, in the present embodiment, heat treatment can use rapid thermal oxidation, spike annealing or laser annealing, this hair
It is bright that this is not construed as limiting.
The present embodiment uses material of the tantalum as the first metal layer 80, so, by described first processing after, one
Kind situation is, in the first metal layer 80 after the described first processing because the part described in surface is converted into oxide layer
81, the work function relative reduction of tantalum oxide.Now, after the first metal layer 80 and oxide layer 81 are collectively forming the processing
The first metal layer.
Another situation is that, after the described first processing, a part of oxygen atom enters the first metal layer 80
Surface, this can equally make mixed with the first metal layer 80 of oxygen atom work function reduction.Now, it is mixed with the of oxygen atom
One metal level 80 is the first metal layer after the processing.
With reference to figure 4, after the step of first sacrifice layer 90A, 90B of the first processing and removal, in the described first opening
30th, second metal layer 100 is formed in the second opening 20 and the 3rd opening 10.
It should be noted that due to formed with first sacrifice layer 90A, 90B, forming second metal layer in the present embodiment
It is further comprising the steps of before 100：
Remove remaining first sacrifice layer 90A, 90B.
Specifically, the second metal layer 100 is the functional layer (PMOS work function, PWF) of PMOS device, the
Two metal levels 100 stack with the first metal layer after the first metal layer 80 of lower section or processing, with the metal for changing and being subsequently formed
Overall work function between grid, and then adjust the threshold voltage of the grid of PMOS device.
In the second opening 20 and the 3rd opening 10, the second metal layer 100 is covered on the first metal layer 80；
In first opening 30, the second metal layer 100 is covered in the oxide layer 81.
In the present embodiment, the material of second metal layer 100 is titanium nitride.
During due to forming the first metal layer 80 in the pmos devices, the also shape in the nmos device on same wafer
Into the first metal layer 80 for having same material, similarly, the second metal layer 100 is also formed in the nmos device simultaneously
On the first metal layer 80.But in general, in nmos device it is not appropriate for forming the second gold medal as PMOS device functional layer
Belong to layer 100, so needing in subsequent steps to remove the second metal layer 100 in the nmos device.Based on upper
State reason, the first metal layer 80 in the present embodiment makees material using tantalum, has relative to the second metal layer 100 of titanium nitride material
There is high etch to select ratio, larger etching selectivity is advantageous to form second metal layer in PMOS device region in the present embodiment
When 100, remove the second metal layer 100 relative to the NMOS area being similarly positioned on same wafer.
But this is not limited by the present invention, such as ramet or molybdenum nitride other materials can also be used.
With reference to figure 5, formed in described first opening the 30, second opening 20 and the 3rd opening 10 and be covered in described second
Second sacrifice layer 110C, 110B and 110A of metal level 100；It is such to be advantageous in that, can be protected in subsequent step
Second metal layer 80 in one opening 30 and the 3rd opening 10 is not influenceed by subsequent step as far as possible.In second sacrifice layer
Photoresist layer 42 is covered on 110A, 110B and 110C；The graphical photoresist layer 42 is to expose the of the second opening 20
One sacrifice layer 90C.The second sacrifice layer 110B is removed by etching, to expose second in the split shed 21 of the second opening 20
Metal level 100.
In order to reduce material cost, alternatively, second described sacrifice layer 110A, 110B and 110C can use with it is upper
Material same first sacrifice layer 90A, 90B and 90C for stating.
With reference to figure 6, second processing is carried out to the second metal layer 100 of the described second opening 20, second after being handled with formation
Metal level, and then improve the work function of the second metal layer 100 in the second opening 20.That is, positioned at described second
The work function of second metal layer is more than the work(of the second metal layer in the opening 10 of the first opening the 30, the 3rd after being handled in opening 20
Function.
In the present embodiment, in the mixed gas of oxygen and nitrogen, the second metal layer 100 is heat-treated,
The portion of material on the surface of second metal layer 100 is set to be converted into oxide layer 101.Now, the second metal layer 100 and its
The oxide layer 101 on surface is collectively forming second metal layer after the processing.
Further, in the mixed atmosphere of oxygen and nitrogen, oxygen is to carry out second processing to the second metal layer 100
Reacting gas, nitrogen be dilution oxygen protective gas.
Due to using material of the titanium nitride as the second metal layer 100 in the present embodiment, the oxide layer 101 is
Titanium oxynitrides, the work function of titanium oxynitrides are more than the work function of titanium nitride.
In order that the content of the oxygen carries out second processing to the second metal layer 100 enough, and it is unlikely excessive
Cause second metal layer 100 to be excessively oxidated, in the present embodiment, make the mixing ratio (gas flow ratio) of the oxygen and nitrogen
1:1~1:In the range of 50.
Meanwhile in order that the surface portion of second metal layer 100 is converted into oxide layer 101, and temperature is unlikely to too high
Cause to impact PMOS device, in the present embodiment, the temperature of heat treatment is in the range of 400~1000 degrees Celsius.
Due to using material of the titanium nitride as second metal layer 100 in the present embodiment, by oxygen and nitrogen
After heat treatment, a kind of situation is that the partial nitridation titanium of second metal layer 100 is oxidized generation compound such as titanium oxynitrides,
Now, second metal layer includes the second metal layer 100 of the titanium nitride material and described titanium oxynitrides etc. after the processing
Compound, the work function of second metal layer increases with respect to second metal layer 100 after processing.
Another situation is that part oxygen atom mixes the surface of second metal layer 100, and this can equally make second gold medal
Belong to the relative rise of total work function of layer 100.Now, the second metal layer 100 for being mixed with oxygen atom is second after the processing
Metal level.
With reference to figure 7, in the second metal layer 100 in the described first opening 30 and the 3rd opening 10 and second is open
Form metal gates 200 respectively in second metal layer after being handled in 20, now, first area, second area on substrate with
And the 3rd form independent PMOS device in region respectively.
Due to be now placed in the first opening 30 handle after the first metal layer work function be less than positioned at second opening 20 with
And the 3rd the first metal layer 80 in opening 10 work function, meanwhile, the second metal layer after the processing in the second opening 20
Work function is higher than the work function for being located at the first opening 30 and the 3rd opening 10 in second metal layer 100, and in general, material
Work function it is higher, threshold voltage in the operating condition is lower, so, after metal gates 200 are formed, positioned at first opening
Threshold voltage highest i.e. high threshold voltage (High VT, HVT) type PMOS device of 30 PMOS device in, and be located at
Low threshold voltage (Low VT, LVT) type PMOS device of second opening 20, positioned at the 3rd opening 10 PMOS device for standard
Threshold voltage (Standard VT, SVT) type PMOS device.
In addition, the present invention also provides second embodiment relative to above-mentioned first embodiment, this second embodiment with it is upper
The difference for stating first embodiment is, includes the step of second processing：To second metal under the atmosphere of ammonia and nitrogen
Layer 100 is heat-treated, and the surface of the second metal layer 100 is passivated, to improve the second metal layer 100
Total work function.
By taking the second metal layer 100 of titanium nitride material as an example, the titanium nitride after the passivation is elevated in work function
At the same time it can also the barrier layer as the metal gates 200 being subsequently formed.
In order that second metal layer 100 can be passivated, without regard to undue reaction, in this second embodiment, make
The mixing ratio of ammonia and nitrogen (gas flow ratio) is 1:1~20:In the range of 1.
Meanwhile in order to there are enough temperature to carry out reaction, whole device is influenceed without regard to warm too high, is heat-treated
In the range of 400~1000 degrees Celsius.
In addition, the present invention also provides the 3rd embodiment relative to first, second above-mentioned embodiment,
The difference of this third embodiment and above-mentioned first, second embodiment is to include the step of carrying out second processing：Adopt
Ions Bombardment processing is carried out to the second metal layer with Nitrogen ion, to be carried out to the second metal layer 100 at described second
Reason.Nitrogen ion bombardment processing is with by the chemical bond rupture in second metal layer 100, or second metal layer is changed from crystalline state
For amorphous state, and chemical bond rupture or amorphous state are respectively provided with higher work function, can also reach raising positioned at the second opening
In 20 second metal layer 100 work function purpose.
In this third embodiment, in order that Nitrogen ion enough by the chemical bond rupture in second metal layer 100 either
Second metal layer 100 is converted into amorphous state, while is unlikely to have influence on the other parts of PMOS device again, in the present embodiment
In, make the flow of nitrogen in 4000~15000 every point of standard milliliters, and make temperature below 400 degrees Celsius；Ions Bombardment equipment
Power below 1000 watts.
In addition, the present invention also provides a kind of grid structure, include with reference to reference to figure 7, the grid structure：
Substrate (not shown)；
Interlayer dielectric layer (not shown) on the substrate, be provided with the interlayer dielectric layer expose it is described
Multiple openings of substrate, the multiple opening include：For forming the first opening of the first semiconductor devices, for forming second
Second opening of semiconductor devices, for forming the 3rd opening of the 3rd semiconductor devices；
The first metal layer 80 being formed in second opening, the 3rd opening, the place being formed in first opening
The first metal layer after reason, the work function of the first metal layer is less than the first metal layer in the second opening and the 3rd opening after the processing
Work function；In the present embodiment, the first metal layer includes the first metal layer 80 and the table of the first metal layer 80 after the processing
The oxide layer 81 in face；But the present invention is not limited thereto, in other embodiments of the invention, the first metal layer after the processing
It can also be the first metal layer 80 for being mixed with oxygen atom；
It is formed at after being handled in the first opening on the first metal layer 80, the second gold medal in the 3rd opening on the first metal layer 80
Belong to layer 100, be formed at second metal layer after the processing in second opening on the first metal layer 80, the second gold medal after the processing
The work function for belonging to layer is more than the work function of second metal layer in the first opening and the 3rd opening；In the present embodiment, the processing
Second metal layer includes second metal layer 100 and the oxide layer 101 on the surface of the second metal layer 100 afterwards.It is but of the invention
This is not limited to, in other embodiments of the invention, second metal layer can also be mixed with oxygen atom after the processing
Second metal layer 100；
It is formed at after being handled in second opening in second metal layer, the first opening in second metal layer 200 and the 3rd
Metal gates 200 in opening in second metal layer 200.
Because the work function of the first metal layer after the processing in the first opening is relative to the in second, third opening
One metal level 80 is relatively low, while the work function of second metal layer is open compared to the first, the 3rd after the processing of the second opening
In second metal layer 200 it is higher, and work function and threshold voltage are inversely, so, positioned at the metal gate of the first opening
The threshold voltage of pole is located at the threshold voltage of the metal gates of the second opening relatively most with respect to highest (High VT, HVT)
Low (Low VT, LVT), and with respect under, the threshold voltage positioned at the metal gates of the 3rd opening is then considered as level threshold value
Voltage (Standard VT, SVT).
In the present embodiment, the material of the first metal layer 80 can be tantalum, or the compound of tantalum, such as tantalum, nitrogen
Change tantalum or calorize tantalum.Accordingly, the first metal layer includes tantalum, or the first metal of the compound-material of tantalum after the processing
Layer 80, and it is formed at the tantalum on the surface of the first metal layer 80 or the oxide of tantalum compound.
In addition, in other embodiments of the invention, the first metal layer can also be mixed with oxygen atom after the processing
Tantalum, or the first metal layer 80 of the compound-material of tantalum.
In the present embodiment, the material of the second metal layer 200 can include：Titanium nitride, ramet or molybdenum nitride.
Accordingly, second metal layer includes titanium nitride, ramet or the second metal layer 200 for nitrogenizing Mo after the processing, with
And the oxide of the titanium nitride on formation and the surface of second metal layer 200, ramet or molybdenum nitride.
In addition, in other embodiments of the invention, second metal layer can also be mixed with oxygen atom after the processing
Second metal layer 200.
In addition, in other embodiments of the invention, second metal layer can also be amorphous state or change after the processing
Learn the second metal layer 200 of key fracture.
In addition, the present invention is not limited in above-mentioned PMOS device, different work functions material can also be used to be formed for example
Other semiconductor devices such as nmos device, the invention is not limited in this regard.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
- A kind of 1. preparation method of grid structure, it is characterised in that including：Substrate is provided；Layer of dielectric material and multiple pseudo- grid structures in layer of dielectric material are formed over the substrate；Pseudo- grid structure is removed, is formed and is located in interlayer dielectric layer and exposes multiple openings of the substrate, the multiple opening bag Include：For forming the first opening of the first semiconductor devices, for forming the second opening of the second semiconductor devices, for being formed 3rd opening of the 3rd semiconductor devices；The first metal layer is formed respectively in the described first opening, the second opening and the 3rd opening；First processing, the first metal layer after being handled with formation, the processing are carried out to the first metal layer in the described first opening The work function of the first metal layer is less than the work function of the first metal layer in the second opening and the 3rd opening afterwards；After the step of first is handled, the first metal layer, the second opening and the 3rd are opened after the processing in the described first opening Second metal layer is formed respectively on the first metal layer in mouthful；The second metal layer being pointed in second opening carries out second processing, and second metal layer after being handled with formation is described The work function of second metal layer is more than the work function of the first opening and the second metal layer in the 3rd opening after processing；In second metal layer after processing in the described second opening in second metal layer, the first opening and the 3rd opening respectively Form metal gates.
- 2. preparation method as claimed in claim 1, it is characterised in that the material of the first metal layer is tantalum, or tantalum Compound.
- 3. preparation method as claimed in claim 1, it is characterised in that the material of the first metal layer be tantalum, tantalum nitride or Person's calorize tantalum.
- 4. preparation method as claimed in claim 2 or claim 3, it is characterised in that the step of forming the first metal layer includes, using change Learn vapour deposition, physical vapour deposition (PVD) or ald and form the first metal layer.
- 5. preparation method as claimed in claim 2 or claim 3, it is characterised in that the step of forming the first metal layer includes, and makes described The thickness of the first metal layer is in the range of 5~20 angstroms.
- 6. the preparation method as described in claim 1 or 3, it is characterised in that the step of the first processing is carried out to the first metal layer Including：The first metal layer is heat-treated in the mixed gas of oxygen and nitrogen.
- 7. preparation method as claimed in claim 6, it is characterised in that the step of carrying out the first processing to the first metal layer is wrapped Include：Make the mixing ratio of the oxygen and nitrogen 1:1~1:In the range of 50, and make temperature during heat treatment 400~1000 In the range of degree Celsius.
- 8. preparation method as claimed in claim 6, it is characterised in that the heat treatment is using rapid thermal oxidation, spike annealing Or laser annealing.
- 9. preparation method as claimed in claim 1, it is characterised in that the step of forming second metal layer includes：Form material For the second metal layer of titanium nitride, ramet or molybdenum nitride.
- 10. preparation method as claimed in claim 9, it is characterised in that the step of second processing is carried out to second metal layer bag Include：Hot place is carried out to the second metal layer in the mixed gas of oxygen and nitrogen or in the mixed gas of ammonia and nitrogen Reason, or, Ions Bombardment processing is carried out to the second metal layer using Nitrogen ion.
- 11. preparation method as claimed in claim 10, it is characterised in that make the mixing ratio of the oxygen and nitrogen 1:1~ 1:In the range of 50, and make annealing temperature in the range of 400~1000 degrees Celsius.
- 12. preparation method as claimed in claim 10, it is characterised in that make the mixing ratio of the ammonia and nitrogen 1:1~ 20:In the range of 1, and make annealing temperature in the range of 400~1000 degrees Celsius.
- 13. the preparation method as described in claim 11 or 12, it is characterised in that the heat treatment is using rapid thermal oxidation, point Peak is annealed or laser annealing.
- 14. preparation method as claimed in claim 10, it is characterised in that during the Nitrogen ion bombardment second metal layer, make nitrogen The flow of gas makes temperature below 400 degrees Celsius in 4000~15000 every point of standard milliliters；The power of Ions Bombardment equipment Below 1000 watts.
- 15. preparation method as claimed in claim 1, it is characterised in that after the step of forming multiple openings, form first It is further comprising the steps of before the step of metal level：Gate dielectric material layer, high K dielectric are sequentially formed on the substrate that the described first opening, the second opening and the 3rd opening are exposed Material layer and cap.
- 16. preparation method as claimed in claim 1, it is characterised in thatAfter the step of forming the first metal layer, to first opening in the first metal layer carry out first processing the step of it Before, in addition to：The first sacrifice layer being covered on the first metal layer is formed in the described second opening, the 3rd opening, with The first metal layer in the second opening and the 3rd opening is blocked during being handled first；To first opening in the first metal layer carry out first processing the step of after, formed second metal layer the step of before, Also include：Remove first sacrifice layer；After the step of forming second metal layer, before the step of second metal layer progress second processing, in addition to：Institute State in the first, the 3rd opening and form the second sacrifice layer being covered in the second metal layer, with during second processing Block the second metal layer in the first opening and the 3rd opening；To second metal layer carry out second processing the step of after, formed metal gates the step of before, in addition to：Remove institute State the second sacrifice layer.
- 17. preparation method as claimed in claim 1, it is characterised in that the step of forming metal gates includes：Using chemical gas Mutually deposition or physical vapour deposition (PVD), form the metal gates of aluminium or tungsten material.
- A kind of 18. grid structure, it is characterised in that including：Substrate；Interlayer dielectric layer on the substrate, the multiple openings for exposing the substrate are provided with the interlayer dielectric layer, The multiple opening includes：For forming the first opening of the first semiconductor devices, for forming the of the second semiconductor devices Two openings, for forming the 3rd opening of the 3rd semiconductor devices；The first metal layer being formed in second opening, the 3rd opening, it is formed at the after the processing in first opening One metal level, the work function of the first metal layer is less than the work content of the first metal layer in the second opening and the 3rd opening after the processing Number；It is formed at after being handled in the first opening on the first metal layer, the second metal layer in the 3rd opening on the first metal layer, shape Second metal layer after the processing on the first metal layer in second opening described in Cheng Yu, the work content of second metal layer after the processing Number is more than the work function of the first opening and the second metal layer in the 3rd opening；It is formed at second after being handled in second opening Metal gates in metal level, the first opening in second metal layer and in the 3rd opening in second metal layer.
- 19. grid structure as claimed in claim 18, it is characterised in that the material of the first metal layer includes：Tantalum, nitridation Tantalum or calorize tantalum.
- 20. grid structure as claimed in claim 18, it is characterised in that the material of the second metal layer includes：Titanium nitride, Ramet or molybdenum nitride.
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| CN107369650B (en) * | 2016-05-11 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Multi-threshold voltage transistor and forming method thereof |
| CN107564863B (en) * | 2016-06-30 | 2020-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN108022879B (en) * | 2016-11-04 | 2020-07-10 | 中芯国际集成电路制造(上海)有限公司 | Multi-threshold voltage transistor and forming method thereof |
| CN108389835B (en) * | 2017-02-03 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108630519A (en) * | 2017-03-17 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
| US10529815B2 (en) * | 2017-10-31 | 2020-01-07 | International Business Machines Corporation | Conformal replacement gate electrode for short channel devices |
| CN110233098A (en) * | 2018-03-05 | 2019-09-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN110349851B (en) * | 2018-04-08 | 2021-12-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and manufacturing method thereof |
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