CN104979176A - Manufacturing method of grid and manufacturing method of transistor - Google Patents
Manufacturing method of grid and manufacturing method of transistor Download PDFInfo
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- CN104979176A CN104979176A CN201410135908.3A CN201410135908A CN104979176A CN 104979176 A CN104979176 A CN 104979176A CN 201410135908 A CN201410135908 A CN 201410135908A CN 104979176 A CN104979176 A CN 104979176A
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Abstract
The present invention provides a manufacturing method of a grid and a manufacturing method of a transistor. The manufacturing method of the grid comprises the steps of providing a substrate; forming a grid material layer on the substrate; etching the grid material layer to form the grid. The step of etching the grid material layer comprises etching the grid material layer by using an etching agent capable of generating the hydroxide ions during an etching process. The beneficial effects of the present invention are that: the formed hydroxide ions can block the ions which are generated during the etching process and can cause the substrate loss easily to permeate towards the substrate, thereby reducing the substrate loss degree caused by the ions as much as possible during the process of etching the grid material layer, namely, reducing the probability of forming recesses on the surface of the substrate.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of manufacture method of grid, the manufacture method of transistor.
Background technology
In the prior art, in each step forming semiconductor device, easily on the substrate of grid both sides, depression (recess) is formed.
Such as, in the process of existing formation grid, generally first on substrate, cover one deck gate material layers, then remove some gate material by the method for etching, remaining gate material layers is as the grid of semiconductor device.But the process of existing etching grid material layer easily causes loss (loss) to a part for substrate.
Particularly, when etching described gate material layers, usually adopt and can produce hydrionic etching agent, during etching, hydrogen ion is easy to penetrate into position darker in substrate, and produces loss to substrate.
In addition, the part contacted with grid due to substrate does not expose all the time, so situation about caving in can not be there is in this part, so, substantially there is not loss in the part that substrate contacts with grid, and substrate is positioned at the part generation loss of grid both sides, that is, the junction of substrate and grid and substrate create difference in height between the position of grid both sides, and this difference in height just defines described depression (depression 5 with reference in figure 1).
In addition, described depression can make the source region of follow-up formation, the position in drain region to the direction skew bottom substrate, and then affect the performance of semiconductor device.In addition, between subsequently formed layer interconnect architecture step in, in order to optimize the contact performance of metal interconnecting wires of source region, drain region and follow-up formation, may in source region, drain region surface formed silicide layer (silicide), now to the bottom skew of substrate, the position in source region, drain region means that the silicide layer that formed on source region, drain region also can offset to substrate bottom direction accordingly, and this can affect the carrying out of subsequent technique.
And along with the reduction gradually of dimensions of semiconductor devices, the impact of described depression on semiconductor device is more and more obvious.
Summary of the invention
The problem that the present invention solves is to provide a kind of manufacture method of grid, the manufacture method of transistor, reduces the probability forming depression on the substrate of grid both sides.
For solving the problem, the invention provides a kind of manufacture method of grid, comprising:
Substrate is provided;
Form gate material layers over the substrate;
Gate material layers is etched, to form grid;
Described the step that gate material layers etches to be comprised: adopt can generate hydroxide ion in etching process etchant described in gate material layers.
Optionally, the step that gate material layers etches is comprised:
Main etching is carried out to described gate material layers, to remove the gate material layers of part;
Soft landing etching is carried out to remaining gate material layers, to remove a part for residue gate material layers;
Over etching is carried out, to remove remaining gate material layers completely to remaining gate material layers after soft landing etching; Wherein, in the step of described over etching, adopt the etching agent that can generate hydroxide ion.
Optionally, described main etching, soft landing etching and over etching are plasma etching.
Optionally, the material of described gate material layers is polysilicon.
Optionally, the etching agent that can generate hydroxide ion in etching process is adopted to comprise:
Oxygen, and ammonia or methane.
Optionally, the described etching agent that can generate hydroxide ion in etching process also comprises hydrogen bromide, or fluorine-based etching gas.
Optionally, described can generation in etching process in the etching agent of hydroxide ion also comprises helium.
The etching agent of described main etching comprises carbon tetrafluoride, sulphur hexafluoride, oxygen and nitrogen.
Optionally, the etching agent of described soft landing etching comprises:
Hydrogen bromide or fluorine-based etching gas, and nitrogen and oxygen.
Optionally, gate material layers is etched, comprise with the step forming grid: in described gate material layers, form mask, with described mask for mask is to the described gate material layers of described etching;
Wherein, the step forming mask comprises: in described gate material layers, form first medium anti-reflecting layer, amorphous carbon layer, second medium anti-reflecting layer and bottom anti-reflection layer successively; Graphical described first medium anti-reflecting layer, amorphous carbon layer, second medium anti-reflecting layer and bottom anti-reflection layer, to form mask.
Optionally, described substrate adopts silicon as material.
Optionally, after the step forming grid, also comprise:
Dielectric layer between described grid upper caldding layer;
Remove described grid to form opening in described interlayer dielectric layer;
Form metal gates in said opening.
In addition, the present invention also provides a kind of manufacture method of transistor, comprising:
Adopt as above-mentioned manufacture method forms grid;
Source region and drain region is formed in the substrate of grid both sides.
Compared with prior art, technical scheme of the present invention has the following advantages:
After described gate material layers forms described mask, described mask forms opening; Then to be formed with the mask of opening for etching mask, the gate material layers that etching is exposed is to form grid, and wherein the etching agent of etching grid material layer generates hydroxide ion in etching process; Owing to easily forming the hydrogen ion penetrated in substrate in etching agent, described hydrogen ion easily produces loss to substrate, and described hydroxide ion can stop the infiltration of described hydrogen ion to substrate, thus reduce described hydrogen ion to the extent of deterioration caused substrate, and then reduce the probability that substrate surface forms depression.
Further, the etching agent of described over etching comprises: oxygen, and ammonia or methane; Wherein, ammonia or methane can in etching process with oxygen reaction, and then generate hydroxyl, the ion that described hydroxyl can be blocked in the easy loss substrate produced in etching process as far as possible permeates in substrate.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of semiconductor device of prior art;
Fig. 2 to Fig. 7 is the structural representation of each step in manufacture method one embodiment of grid of the present invention.
Embodiment
At existing etching grid material layer to be formed in the process of grid, etching agent easily causes loss (loss) to a certain degree to substrate, and then the substrate surface in the grid both sides formed forms depression (recess).
For this reason, the invention provides a kind of manufacture method of grid, comprising: substrate is provided; Form gate material layers over the substrate; Described gate material layers forms mask; Opening is formed in described mask; The gate material layers that etching is exposed is to form grid, and wherein the etching agent of etching grid material layer generates hydroxide ion in etching process.
By above-mentioned steps, in etching process, generate hydroxide ion; Owing to easily forming the hydrogen ion penetrated in substrate in etching agent, described hydrogen ion easily produces loss to substrate, and described hydroxide ion can stop the infiltration of described hydrogen ion to substrate, thus reduce described hydrogen ion to the extent of deterioration caused substrate, and then reduce the probability that substrate surface forms depression.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiment of the invention below in conjunction with accompanying drawing.
Referring to figs. 2 to Fig. 7, it is the structural representation of each step in manufacture method one embodiment of grid of the present invention.
As shown in Figure 2, provide substrate 100, and form gate material layers 200 on described substrate 100.Described gate material layers 200 forms the grid of semiconductor device for being etched in subsequent steps.
In the present embodiment, the material of described substrate 100 is silicon, and the material of described gate material layers 200 is polysilicon.
In the present embodiment, before the described gate material layers 200 of formation, described substrate 100 forms grid oxide layer (not shown).
Further, described grid oxide layer adopts silicon dioxide as material, but the present invention is not limited in any way this.
Continue with reference to figure 3, described gate material layers is formed mask 300.
In the present embodiment, the step forming described mask 300 comprises formation in described gate material layers 200 successively:
First medium anti-reflecting layer (Dielectric Anti-Reflect Coating, DARC) 310, amorphous carbon layer (amorphous carbon) 320, second medium anti-reflecting layer 330 and bottom anti-reflection layer (BottomAnti-Reflect Coating, BARC) 340.
In the present embodiment, the material of described first medium anti-reflecting layer 310 can be silica, silicon oxynitride or both combinations; The formation method of first medium anti-reflecting layer 310 can adopt deposition to obtain, but the present invention does not limit this.
In the present embodiment, described second medium anti-reflecting layer 330 can be formed by with described first medium anti-reflecting layer 310 same material, and also can be formed by the depositional mode similar to first medium anti-reflecting layer 310, and the present invention does not also limit this.
In the present embodiment, described bottom anti-reflection layer 340 can adopt titanium nitride or silicon nitride as material, but the present invention does not also limit this, and some organic substance materials also can as the material of described bottom anti-reflection layer 340.
In addition, described bottom anti-reflection layer 340 can adopt the modes such as deposition to be formed, and the present invention does not limit this.
In addition, the mask layer 300 of above-mentioned first medium anti-reflecting layer 310, amorphous carbon layer 320, second medium anti-reflecting layer 330 and bottom anti-reflection layer 340 combination is only the example adopted in the present embodiment, in practical operation, other anti-reflecting layer can be adopted as the case may be, as the anti-reflecting layer (Si-ARC) etc. containing silicon combines, so should not limit the present invention with this.
With reference to figure 4, in described mask 300, form opening 50, described opening 50 defines the size of the grid that subsequent step will be formed.
Specifically, in the present embodiment, can by the mode of photoetching, by once or multiple etching, to form described opening 50 in described first medium anti-reflecting layer 310, amorphous carbon layer 320, second medium anti-reflecting layer 330 and bottom anti-reflection layer 340.
In the present embodiment, after the described opening 50 of formation, further comprising the steps of:
Divest (strip) described second medium anti-reflecting layer 330, amorphous carbon layer 320 and bottom anti-reflection layer 340, only retain described first medium anti-reflecting layer 310, think that follow-up etching provides condition.
With reference to figure 5 to Fig. 7, the gate material layers 200 that etching is exposed is to form grid, and wherein the etching agent of etching grid material layer 200 generates hydroxide ion (OH-) in etching process.
In the present embodiment, the step etching the gate material layers exposed comprises step by step following:
First with reference to figure 5, to be formed with the first medium anti-reflecting layer 310 of described opening for etching mask, main etching (main etch, ME) is carried out to described gate material layers 200, to remove the gate material layers 200 of part; Now, the gate material layers 201 that the needs of some residual are removed is still had.
This object is step by step to remove fast the gate material layers 200 that major part needs to remove, to ensure the efficiency of whole etch step.
Secondly with reference to figure 6, soft landing etching (soft landing, SL) is carried out to remaining gate material layers 201, to remove a part for remaining gate material layers 201, and substrate 100 is exposed; Now, the gate material layers 202 of fraction remnants still may be had not to be etched totally.
Due in the present embodiment, described substrate 100 is formed with grid oxide layer, so in the step etched in this soft landing, is specially the part removing residue gate material layers, and grid oxide layer is exposed.
Due to after carrying out main etching, be positioned at the position of the gate bottom begun to take shape, may there be the remnants of gate material layers at the position be namely connected with substrate 100, such as, remaining gate material layers 202 in Fig. 6, so basis object is step by step, as far as possible when not having influence on grid oxide layer and substrate 100, revise the sidewall of the grid begun to take shape, namely remove described remaining gate material layers 202, make the sidewall profile of grid become ideal.
Then with reference to figure 7, over etching (over etch) is carried out, comparatively fully to remove above-mentioned remaining gate material layers 201 to remaining gate material layers after soft landing etching.Now, the remaining gate material layers 200 in Fig. 7 is just as the grid of semiconductor device.Wherein, in the step of described over etching, adopt the etching agent that can generate hydroxide ion.
Due to through upper one step by step soft landing etching after, still the residual of some gate material layers may be there is on the surface of described substrate 100, the object of this step is, when removing these and be residual as far as possible, reduce the probability that substrate 100 surface produces depression (recess) as far as possible, that is, some ion reduced in etching agent enters substrate 100 as far as possible, and then causes substrate 100 rounds losses (loss).
In the present embodiment, described main etching, soft landing etching and over etching are plasma etching, and such benefit is, the selectivity of this lithographic method is higher and etching efficiency is higher; In addition, the etch residue of plasma etching is also fewer.
In the present embodiment, the etching agent of described main etching comprises carbon tetrafluoride, sulphur hexafluoride, oxygen and nitrogen; This etching agent is very fast for the etching speed of the gate material layers 200 of the polycrystalline silicon material in the present embodiment, is conducive to the efficiency ensureing whole etch step.
Particularly, in plasma etching process, make the flow of carbon tetrafluoride in the scope of 65 ~ 85 marks condition milliliter per minute (sccm), the flow of sulphur hexafluoride marks the scope of condition milliliter per minutes 5 ~ 20, the flow of oxygen marks the scope of condition milliliter per minute 1 ~ 5, nitrogen flow is in the scope of 10 ~ 20 mark condition milliliter per minutes.
Meanwhile, make ambient pressure in the scope of 1 ~ 100 millitorr, the source power (source power) of etching machine is in the scope of 400 ~ 600 watts, and bias power (bias power) is in the scope of 100 ~ 300 watts.
But it should be noted that, above etching parameters is only the example adopted in the present embodiment, in practical operation, these parameters can adjust accordingly according to actual conditions, so should not limit the present invention with this.
In the present embodiment, the etching agent of described soft landing etching comprises:
Hydrogen bromide, nitrogen and oxygen.Such benefit is, hydrogen bromide has good selectivity for substrate.But the present invention, for whether hydrogen bromide being adopted not to be restricted, also can adopt other etching gas, such as, comprise some fluorine-based etching gas of hydrogen fluoride.
Owing to containing hydrogen bromide in the etching agent of soft landing etching, hydrogen bromide will produce hydrogen ion (H in etching process
+).Hydrogen ion, due to himself characteristic, is easy to penetrate into substrate 100, and penetration degree is comparatively large, causes the degree of loss also larger for substrate 100.So, above-mentioned easily cause the ion of loss to be hydrogen ion to substrate 100.
Particularly, in the present embodiment, bromizate the scope of flow at 200 ~ 400 mark condition milliliter per minutes of hydrogen, the flow of oxygen marks the scope of condition milliliter per minute 1 ~ 5, nitrogen flow is in the scope of 10 ~ 20 mark condition milliliter per minutes.
Simultaneously, because etching is now close to substrate 100, in order to reduce the impact on substrate 100, can make ambient pressure in the scope of 1 ~ 100 millitorr, the source power of etching machine is in the scope of 300 ~ 400 watts, and bias power (bias power) is in the scope of 50 ~ 150 watts.
But it should be noted that, above etching parameters is only the example adopted in the present embodiment, in practical operation, these parameters can adjust accordingly according to actual conditions, so should not limit the present invention with this.
In the present embodiment, the etching agent of described over etching comprises:
Oxygen, hydrogen bromide and ammonia.Such benefit is, hydrogen bromide has for substrate 100 selectivity preferably, ammonia can reduce the loss of the hydrogen ion in etching agent for substrate 100 simultaneously, its reason is, the hydrogen ion produced in etch step is easy to penetrate into grid oxide layer and substrate 100, and then causes loss to grid oxide layer and substrate 100.When carrying out over etching, ammonia in the etching agent of over etching can be freeed with oxygen quickly and be reacted to generate nitrogen and water, hydroxide ion in water is difficult to enter in substrate 100, and be attached to substrate 100 surface, serve and stop that hydrogen ion enters the effect of substrate 100, and then the probability that above-mentioned hydrogen ion enters grid oxide layer and substrate 100 can be reduced as far as possible.
It should be noted that, whether the present invention does not limit in etching agent must adopt hydrogen bromide, also can adopt other etching gas, such as fluorine-based etching gas.
Simultaneously, whether the present invention is for ammonia being adopted also not limit, the present invention is intended to employing can generate hydroxide ion in etching process, to stop that hydrogen ion enters substrate 100, so for which kind of material of employing do not limit, can also adopt other gas, the methane that such as can generate hydroxide ion equally in etching process with oxygen reaction carrys out alternative ammonia.
In addition, in the present embodiment, the helium as protective gas can also be comprised in etching agent.But the present invention is not construed as limiting this, also can adopts other protective gas such as argon gas, or protective gas is not set.
Particularly, in the present embodiment, bromizate the scope of flow at 300 ~ 500 marks condition milliliter per minute (sccm) of hydrogen, the flow of oxygen marks the scope of condition milliliter per minute 1 ~ 15, make the flow of ammonia in the scope of 5 ~ 100 mark condition milliliter per minutes, the flow of helium is 400 ~ 600 mark condition milliliter per minutes.
Meanwhile, make ambient pressure in the scope of 50 ~ 100 millitorrs, the source power of etching machine is in the scope of 1300 ~ 1500 watts, and bias power is in the scope of 200 ~ 500 watts.In addition, the time of over etching is in the scope of 5 ~ 120 seconds.
But it should be noted that, above etching parameters and etch period are only the examples adopted in the present embodiment, in practical operation, these parameters can adjust accordingly according to actual conditions, so should not limit the present invention with this.
In addition it should be noted that, the etching agent that can generate hydroxide ion in etching process adopted in above-mentioned over etching step is also not limited to over etching step, in main etching and soft landing etching, also can adopt this etching agent.
After this, remove remaining first medium anti-reflecting layer 310, now remaining gate material layers 200 becomes the grid of semiconductor device.
In addition in the present embodiment, after formation of the gate, the mode that loss (loss) degree on substrate 100 and grid oxide layer can pass through optical critical yardstick (Optical Critical Dimension, OCD) is monitored, to adjust parameters when forming grid next time.In addition, the present invention also loses the grid being limited to above-mentioned formation semiconductor device, and the formation for the pseudo-grid (dummy gate) in rear grid technique is applicable to adopting manufacture method of the present invention equally.
Particularly, after the step forming grid, also step is comprised: dielectric layer between described grid upper caldding layer; Remove described grid to form opening in described interlayer dielectric layer; Form metal gates in said opening.Because grid both sides decrease the generation of depression, therefore interlayer dielectric layer can be filled between grid preferably, is not easy to produce the defects such as space (void), thus has comparatively even curface, and then improves the performance of the transistor with metal gates.
The present invention also provides a kind of manufacture method of transistor, and above-mentioned manufacture method adopts above-mentioned method to form the grid of transistor, in the substrate of grid both sides, form source region and drain region.Because grid both sides decrease the generation of depression, because of the problem this reducing source region, the position in drain region offsets to the bottom of substrate.In addition, the problem that the follow-up silicide layer formed on source region, drain region offsets bottom substrate is also reduced.Improve the performance of transistor.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (13)
1. a manufacture method for grid, is characterized in that, comprising:
Substrate is provided;
Form gate material layers over the substrate;
Gate material layers is etched, to form grid;
Described the step that gate material layers etches to be comprised: adopt can generate hydroxide ion in etching process etchant described in gate material layers.
2. manufacture method as claimed in claim 1, is characterized in that, comprise the step that gate material layers etches:
Main etching is carried out to described gate material layers, to remove the gate material layers of part;
Soft landing etching is carried out to remaining gate material layers, to remove a part for residue gate material layers;
Over etching is carried out, to remove remaining gate material layers completely to remaining gate material layers after soft landing etching; Wherein, in the step of described over etching, adopt the etching agent that can generate hydroxide ion.
3. manufacture method as claimed in claim 2, it is characterized in that, described main etching, soft landing etching and over etching are plasma etching.
4. manufacture method as claimed in claim 1, it is characterized in that, the material of described gate material layers is polysilicon.
5. the manufacture method as described in any one of Claims 1-4 claim, is characterized in that, adopts the etching agent that can generate hydroxide ion in etching process to comprise:
Oxygen, and ammonia or methane.
6. manufacture method as claimed in claim 5, it is characterized in that, the described etching agent that can generate hydroxide ion in etching process also comprises hydrogen bromide, or fluorine-based etching gas.
7. manufacture method as claimed in claim 5, it is characterized in that, described can generation in etching process in the etching agent of hydroxide ion also comprises helium.
8. the manufacture method as described in any one of claim 2 to 4 claim, is characterized in that, the etching agent of described main etching comprises carbon tetrafluoride, sulphur hexafluoride, oxygen and nitrogen.
9. the manufacture method as described in any one of claim 2 to 4 claim, is characterized in that, the etching agent of described soft landing etching comprises:
Hydrogen bromide or fluorine-based etching gas, and nitrogen and oxygen.
10. manufacture method as claimed in claim 1, is characterized in that, etch gate material layers, comprise with the step forming grid: in described gate material layers, form mask, with described mask for mask is to the described gate material layers of described etching;
Wherein, the step forming mask comprises: in described gate material layers, form first medium anti-reflecting layer, amorphous carbon layer, second medium anti-reflecting layer and bottom anti-reflection layer successively; Graphical described first medium anti-reflecting layer, amorphous carbon layer, second medium anti-reflecting layer and bottom anti-reflection layer, to form mask.
11. manufacture methods as claimed in claim 1, is characterized in that, described substrate adopts silicon as material.
12. manufacture methods as claimed in claim 1, is characterized in that, after the step forming grid, also comprise:
Dielectric layer between described grid upper caldding layer;
Remove described grid to form opening in described interlayer dielectric layer;
Form metal gates in said opening.
The manufacture method of 13. 1 kinds of transistors, is characterized in that, comprising:
The manufacture method as described in claim 1 ~ 10 is adopted to form grid;
Source region and drain region is formed in the substrate of grid both sides.
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| CN201410135908.3A CN104979176B (en) | 2014-04-04 | 2014-04-04 | Production method, the production method of transistor of grid |
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| CN201410135908.3A CN104979176B (en) | 2014-04-04 | 2014-04-04 | Production method, the production method of transistor of grid |
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| CN104979176A true CN104979176A (en) | 2015-10-14 |
| CN104979176B CN104979176B (en) | 2019-07-30 |
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| US20030054611A1 (en) * | 2001-09-19 | 2003-03-20 | Masayoshi Kanaya | Method of fabricating a split-gate semiconductor device |
| CN1604278A (en) * | 2003-10-01 | 2005-04-06 | 台湾积体电路制造股份有限公司 | A method for treating a gate structure |
| CN101140873A (en) * | 2006-09-04 | 2008-03-12 | 中芯国际集成电路制造(上海)有限公司 | Method of preparing semiconductor device grids |
| US20080102619A1 (en) * | 2006-10-31 | 2008-05-01 | Hynix Semiconductor Inc. | Method of manufacturing a semiconductor device |
| CN102184852A (en) * | 2011-03-15 | 2011-09-14 | 上海集成电路研发中心有限公司 | Method for etching double-doped polysilicon |
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2014
- 2014-04-04 CN CN201410135908.3A patent/CN104979176B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030054611A1 (en) * | 2001-09-19 | 2003-03-20 | Masayoshi Kanaya | Method of fabricating a split-gate semiconductor device |
| CN1604278A (en) * | 2003-10-01 | 2005-04-06 | 台湾积体电路制造股份有限公司 | A method for treating a gate structure |
| CN101140873A (en) * | 2006-09-04 | 2008-03-12 | 中芯国际集成电路制造(上海)有限公司 | Method of preparing semiconductor device grids |
| US20080102619A1 (en) * | 2006-10-31 | 2008-05-01 | Hynix Semiconductor Inc. | Method of manufacturing a semiconductor device |
| CN102184852A (en) * | 2011-03-15 | 2011-09-14 | 上海集成电路研发中心有限公司 | Method for etching double-doped polysilicon |
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