CN104979164A - Defect-free Relaxed Covering Layer On Semiconductor Substrate With Lattice Mismatch - Google Patents

Defect-free Relaxed Covering Layer On Semiconductor Substrate With Lattice Mismatch Download PDF

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CN104979164A
CN104979164A CN201510176799.4A CN201510176799A CN104979164A CN 104979164 A CN104979164 A CN 104979164A CN 201510176799 A CN201510176799 A CN 201510176799A CN 104979164 A CN104979164 A CN 104979164A
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layer
semiconductor
semi
substrate
conducting material
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CN104979164B (en
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H·黄
H·刘
J·P·刘
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GlobalFoundries Inc
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GlobalFoundries Inc
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Abstract

A defect-free, relaxed semiconductor covering layer (e.g., epitaxial SiGe) over a semiconductor substrate (e.g., Si) is provided having a strain relaxation degree above about 80% and a non-zero threading dislocation density of less than about 100/cm2. A lattice mismatch exists between the substrate and the covering layer. The covering layer also has a non-zero thickness that may be less than about 0.5 microns. The strain relaxation degree and threading dislocation are achieved by exposing defects at or near a surface of an initial semiconductor layer on the substrate (i.e., exposing defects via selective etch and filling-in any voids created), planarizing the filled-in surface, and creating the covering layer (e.g., growing epitaxy) on the planarized, filled-in surface, which is also planarized.

Description

The zero defect do not mated on semiconductor substrate in lattice relaxes cover layer
Technical field
The present invention substantially has and relates to semiconductor structure and manufacture thereof.More particularly, the present invention relates to a kind of semiconductor structure and a kind of method in order to be manufactured with this semiconductor structure of semiconductor layer on substrate, this layer is had an appointment the strain relaxation degree of more than 80% and about 100/cm 2following runs through difference row's density (threading dislocation density).
Background technology
Strain relaxation semi-conducting material on semiconductor substrate, such as, SiGe on silicon substrate, has many potential application at electronics and electrooptical device.In order to practical application, preferably this layer has the loose degree of Large strain, and the low difference that runs through arranges density, and level and smooth surface.In addition, preferably also thickness is minimized, such as, because along with thickness increase, production cost also rises and occurs great technical problem, the bad thermal conductivity correlated with material.Experimentally result and theoretical model, these institutes are for characteristic usually self-contradiction.Such as, experimental result and theoretical model point out that SiGe strain relaxation degree on a silicon substrate depends on the thickness of SiGe, and this layer is thicker, then strain relaxation degree is higher.Expect to only have very thin film just to have the loose degree of Large strain (about 90%), but with regard to cost, this is unactual.Equally, run through the function that difference row's density (TDD) is shown as SiGe thickness, thus TDD increases along with SiGe thickness and reduces.As a result, manufacture has the thin silicon germanium of the loose degree of the Large strain being suitable for application of installation and low TDD to be part challenge on a silicon substrate.
Therefore, there are the loose degree of Large strain, low TDD and reduce the strain relaxation semiconductor layer of thickness and need to have the feasible manufacturing technology of cost benefit, volume production.
Summary of the invention
On the one hand, a kind of method manufacturing semiconductor structure is provided, the shortcoming of prior art can be overcome and have additional advantage.The method comprises: provide an initial semiconductor structure, this structure comprises: semiconductor substrate, comprises at least one first semi-conducting material, and the second layer be made up of at least one second semi-conducting material on the substrate.There is lattice between this substrate with this second layer not mate (lattice mismatch), and at least one defect occurs and can be exposed in this second layer.The method more comprises: expose this at least one defect, inserts any space (void) produced by this exposing step in (fill-in) this second layer, and after this inserts step, covers this second layer with semiconductor cover layer.This cover layer is had an appointment the strain relaxation degree of more than 80% and about 100/cm 2following non-zero (non-zero) runs through difference row density.
According on the other hand, provide a kind of semiconductor structure.This structure comprises semiconductor substrate, comprises at least one first semi-conducting material, the second layer be made up of at least one second semi-conducting material on the substrate, and the semiconductor cover layer on this second layer.There is lattice between this substrate with this cover layer not mate, and this cover layer is had an appointment the strain relaxation degree of more than 80% and about 100/cm 2following non-zero runs through difference row density.
Above and other target of the present invention, feature and advantage can be understood by the detailed description by reference to the accompanying drawings of the various aspect of following the present invention.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of an example of initial semiconductor structure according to one or more aspect of the present invention, and it has and one or morely exposes defect in the semiconductor layer of surface.
Fig. 2 is in exposing the example after defect (or several) according to one or more aspects of the present invention pictorial image 1 graph structure.
Fig. 3 is according to the example of one or more aspects of the present invention pictorial image 2 structure after deposition one deck filler material is above exposure defect (or several).
Fig. 4 is exposing packing layer defect (or several) above and example planarization after in removing through inserting according to one or more aspects of the present invention pictorial image 3 structure.
Fig. 5 is according to the example of one or more aspects pictorial image 4 structure of the present invention after the cover layer setting up semi-conducting material.
Fig. 6 is according to the example of one or more aspects pictorial image 5 structure of the present invention after cover layer planarization.
Symbol description
102 substrates 104,112 layers
106 defect 108,120 surfaces
110 space 114 calkings
115 planarized surface 116 semiconductor material layers
118 little indenture 122 defect-free surface.
Embodiment
Several aspect of the present invention and some features, advantage and details is explained in more detail below with the non-limiting examples being illustrated in accompanying drawing.Omit conventional materials, fabrication tool, process technology etc. description in order to avoid unnecessary details fuzzy of the present invention.But, should be appreciated that, although detailed description and particular example point out several aspect of the present invention, but they all only supply graphic extension instead of are used for limiting.Those skilled in the art obviously can understand in the spirit and/or category of concept of the present invention, to have various replacement, amendment, additional and/or configuration by this disclosure.
Any quantitative representation as do not caused relevant basic function to change for the approximate language in patent specification and claims to modify permission change can be applied.Therefore, the numerical value modified with a term or several term, such as " approximately " is not limited to the exact numerical values recited of specifying.In some cases, this approximate language may correspond to the accuracy to the instrument for measuring this numerical value.
Only in order to specific embodiment and not intended to be limiting the present invention will be described for term herein.As used herein, English singulative " a ", " an " and " the " are also intended to comprise plural form, clearly indicate unless separately had in context.More should be appreciated that, term " comprises (comprise) " (and any type ofly to comprise, such as " comprises " and " comprising "), " having (have) " (and any type ofly to have, such as " has " and " having "), " comprising (include) " (and any type ofly to comprise, such as " includes " and " including ") and " containing (contain) " (and any type of contain, such as " contains " and " containing ") be all open copulative verb.As a result, method or the device of " comprising ", " having ", " comprising ", " containing " one or more step or element have this one or more step or element, but are not limited to only have this one or more step or element.Equally, method step or the device element of " comprising ", " having ", " comprising ", " containing " one or more feature have this one or more feature, but are not limited to only have this one or more feature.In addition, be at least use which configuration by the device of a certain mode configuration or structure, but also can carry out configuration by the mode of non-tabular.
As used herein, mean these two solid element when using term " to connect (connect) " and mention two solid element and directly connect.But, term " coupling (couple) " can mean directly connection or the connection by one or more intermediary element.
As used herein, term " possibility " and " perhaps " represent and may to occur in one group of situation; Have specified properties, characteristic or function; And/or limiting another verb, they are one or more by what express in the ability, performance or the possibility that correlate with limited verb.Therefore, a modification term is obviously applicable to, can or be applicable to by reference performance, function or usage to use " possibility " and " perhaps " to point out, consider in some cases simultaneously, this modification term may be not suitable for sometimes, can or applicable.Such as, in some cases, can expect an event or performance, in other cases, this event or performance can not occur, and therefore use " possibility " and " perhaps " to reflect this difference simultaneously.
Easily understand and the accompanying drawing of not to scale drafting below with reference to for asking, in accompanying drawing, the identical component symbol of same or similar assembly represents.
Fig. 1 is the cross-sectional view of an example of initial semiconductor structure, and it has one or more defect on the surface of the substrate or in neighbouring semiconductor layer.This initial structure comprises the substrate 102 be made up of the first semi-conducting material and the layer 104 be made up of the second semi-conducting material.The semi-conducting material of this substrate can comprise any suitable semi-conducting material, such as, and silicon (Si), GaAs (GaAs) or indium phosphide (InP).In addition, this substrate can be bulk substrate (such as, wafer).This second semiconductor material layer comprises one or more semi-conducting material and does not mate with this substrate lattice.The example of possibility the second semi-conducting material comprises the one or more semi-conducting materials of the iii-v from the periodic table of elements substantially, such as, SiGe (SiGe), germanium (Ge), InGaAsP (InGaAs), cadmium telluride (CdTe) or cadmium mercury telluride (CdHgTe).As shown in Figure 1, in layer 104, there is one or more defect, be included in the defect 106 in the front 108 of the second semiconductor material layer.Usually, these defects are in the depth distribution along this layer or film, and its density is successively decreased to surface by substrate (that is, with the interface of substrate 102) usually.But, with regard to object of the present invention, only have in mind relevant surfaces place or near defect and also be referred to herein as " can expose (exposable) ".As used herein, term " defect " or " several defect " refer to that the one or more differences in lattice structure arrange (such as, running through the row of difference) or scrambling.
Fig. 2 is the example of pictorial image 1 structure after exposure defect (or several) 106.Expose defect (or several) refer to actual remove layer 104 surface 108 cover this defect region in material, leave space 110 and expose these defects.Preferably, minimize the material be removed, still expose this defect simultaneously.Such as, available dry ecthing or to defect selectively wet etching realize defect and expose (that is, remove the material covering given defect in layer 104).Those skilled in the art should be appreciated that, the etching in defectiveness region is obviously faster than not having defective region; Therefore, this etching is regarded as defect selective.In an example, this second semi-conducting material comprise SiGe and with dry type for preferably selective etch, and can to comprise, such as, with higher than the temperature of about 600 DEG C, in hydrogen atmosphere, to use hydrochloric acid.
Fig. 3 is that pictorial image 2 structure is at the example of deposition one deck filler material above the layer having exposure defect (or several).The layer 112 be made up of filler material can comprise, such as, and oxide or nitride.In an example, when the material that substrate 102 comprises silicon and layer 104 comprises SiGe, this filler material can comprise, such as, and oxide.The deposition realizing this oxide can use, and such as, the form of chemical vapour deposition (CVD) (CVD), comprises such as known CVD and low pressure chemical vapor deposition (LPCVD).Under arbitrary situation, those skilled in the art should be appreciated that, all need silicon source and oxygen source.This silicon source, such as, can be tetraethoxysilane (TEOS) or silane (SiH 4).Oxygen source, such as, can be oxygen (O 2) or nitric oxide (N 2o).In addition, those skilled in the art should be appreciated that, LPCVD uses subatmospheric pressure.In a variant of this example, nitride is used as filler material.Need siliceous source and contain nitrogenous source.Such as, silicon source can be silicon dioxide (SiO 2), dichlorosilane (H 2siCl 2), it is also referred to as " DCS ", simultaneously nitrogenous source, such as, can be and produce silicon nitride (Si 3n 4) ammonia (NH 3).
Fig. 4 be pictorial image 3 structure in remove through insert packing layer above defect (or several) then planarization produce the example after planarized surface 115.Preferably, remove the useless filler material on calking 114, and in same processing procedure, complete both planarizations, but do not need so.In an example, when substrate comprises silicon, the material of layer 104 comprises SiGe, and this filler material comprises oxide, realize sige surface and the oxide removal of calking and planarization useful chemical mechanical lapping (CMP) technology, such as, use based on cerium oxygen (that is, cerium (IV) oxide (CeO 2)) mud and on layer 104 stop.In a better variant, use cerium (III) oxide, it is more stable under the reference condition of temperature, pressure.
Fig. 5 is that pictorial image 4 structure is producing the example of additional semiconductor material 116 on layer 104, after covering planarized surface (the 115,5th figure).In an example, producing this additional materials can by growth extension (epitaxial) semi-conducting material in this on the surface.Such as, when this epitaxial material comprises SiGe, growth epitaxial sige, such as, available CVD processing procedure, such as, LPCVD.Silicon source, such as, can be silane (SiH 4) or DCS, and germanium source, such as, can be germane (GeH 4) or two germane (Ge 2h 6).For the epitaxial material except SiGe, molecular beam epitaxy is grown up (MBE) or metallorganic CVD (MOCVD) is better processing procedure.Those skilled in the art should be appreciated that, MBE use have slow deposition rate and without the high vacuum of carrier gas with depositing monocrystalline, and MOCVD uses metal organic precursor thing.It should be noted that if removing and losing any filler material during planarization, little indenture (indentation) 118 may be had on calking.
The thickness of additional materials 116 will depend on many factors, comprise the type of additional materials used, apply, and institute is for defect concentration and cost.Be in the example of epitaxial sige at additional materials, this additional materials can thick about 500 nanometers extremely about 800 nanometers.Generally speaking, this thickness should be able to realize strain relaxation and the about 100/cm of about more than 80% 2following non-zero runs through the target of difference row density.
Fig. 6 is the example of pictorial image 5 structure after planarizing semiconductor material layer 116.In an example, in order to remove any indenture (such as, indenture 118), the planarization realizing surface 120 (with reference to the 5th figure) can utilize and use mud abrasive material size about 20 nanometer to the ultra-high purity colloidal state tripoli mud of about 30 nanometers and the relatively low CMP form removing speed of about 2 dusts/second to about 3 dusts/second.Final result is that defect-free surface 122 is ready for further processing, or optionally, repeated defects exposes, insert and add tectal circulation until realize institute for defect level.In addition, as described in further detail subsequently, planarization layer 116 is had an appointment the strain relaxation degree of more than 80% and about 100/cm 2following non-zero runs through difference row density.
Disclosed above is the method making the loose semiconductor layer of zero defect resulting structures on a semiconductor substrate.As used herein, term " loose " refers to strain relaxation.Those skilled in the art should be appreciated that, when being in application to substrate, the lattice size of layer 104 (Fig. 1) changes compared with its nature (such as, becoming large), so that conformal with the substrate lattice (such as, more greatly) varied in size.Lattice size becomes different from nature can produce strain.
The method of having given announcement comprises: provide an initial semiconductor structure, and this structure comprises the semiconductor substrate be made up of at least one first semi-conducting material, and the second layer be made up of at least one second semi-conducting material on the substrate.There is lattice between this substrate with this second layer not mate, and defect (or several) can be exposed be present in this second layer.The method more comprises: expose this at least one defect, inserts any space produced by this exposing step in this second layer, and after this inserts step, covers this second layer with semiconductor cover layer.This cover layer is had an appointment the strain relaxation degree of more than 80% and about 100/cm 2following runs through difference row density.Those skilled in the art should be appreciated that, " running through difference row density " refers to that the one or more differences in lattice structure arrange (such as, running through difference row) or scrambling.
In an example, the semi-conducting material of this substrate can comprise silicon, GaAs or indium phosphide.In another example, this semiconductor substrate can comprise a bulk semiconductor substrate.
In an example, expose this (s) the step of defect comprise: the material removing this second layer, and insert any space (or several) set up with filler material (or several).In an example, to be somebody's turn to do (s) filler material and to comprise oxide.In an example, removing materials with expose this (s) the step of defect comprise: etch this second layer with dry ecthing method, such as, the H of about 600 to about 800 DEG C under about 10 holder ear low pressure 2the HCl (hydrochloric acid) carried in (hydrogen).In an example, this is inserted step and comprises the packing layer that conformal deposited is made up of filler material (or several), and etches this packing layer, and this second layer stops.
In an example, this covering step comprises: growth epitaxial semiconductor material in this through inserting on the second layer.In an example, this epitaxial semiconductor material can comprise the one or more semi-conducting materials of the iii-v from the periodic table of elements, such as, and silicon and/or germanium (Si/Ge belongs to IV race, and Ga-As belongs to three or five races).Selected special epitaxial material can depend on the semi-conducting material being used in the second layer.As described in above when key diagram 1, this second layer comprises the one or more semi-conducting materials of the iii-v from the periodic table of elements substantially, such as, SiGe (SiGe), germanium (Ge), InGaAsP (InGaAs), cadmium telluride (CdTe) or cadmium mercury telluride (CdHgTe).Selected epitaxial semiconductor material such as should minimize or avoid the strain caused by lattice difference in size.Such as, by guaranteeing lattice constant (in-plane lattice constant) in the face that epitaxial material has approximately identical with this second layer material (identical the most desirable), this thing can be realized.This helps avoid any additional defects.
When SiGe is used as epitaxial material, the percentage of germanium in this SiGe can in the scope of about 20% to about 100%.
Together with above-mentioned manufacture method, the present invention includes gained semiconductor structure.This structure comprises the semiconductor substrate be made up of one or more semi-conducting material, and the semiconductor cover layer in face on the substrate, and this cover layer comprises one or more second semi-conducting material.There is lattice between this substrate with this cover layer not mate, and this cover layer is had an appointment the strain relaxation degree of more than 80% and about 100/cm 2following non-zero runs through difference row density.In an example, this semiconductor structure has the non-zero thickness being less than about 0.5 micron.
In an example, this semi-conducting material of this substrate comprises silicon, GaAs or indium phosphide.In another example, this semiconductor substrate comprises a bulk semiconductor substrate.
This semiconductor covering layer can comprise the material of the iii-v from the periodic table of elements, and/or can comprise an epitaxial material.In an example, this semiconductor covering layer comprises SiGe.When using SiGe, the percentage of germanium in this SiGe can in the scope of about 20% to about 100%.
In another example, this semiconductor covering layer one of to comprise in InGaAsP, cadmium telluride and cadmium mercury telluride.
Although described herein and illustrated several aspect of the present invention, but those skilled in the art still can make alternative aspect to realize identical target.Therefore, wish that following claims can contain these type of alternative aspect all dropped in true spirit of the present invention and category.

Claims (20)

1. a method, comprising:
There is provided initial semiconductor structure, this structure comprises: semiconductor substrate, comprises at least one first semi-conducting material; And the second layer of at least one second semi-conducting material on the substrate, wherein, there is lattice between this substrate with this second layer and do not mate, and wherein, at least one defect occurs and can be exposed in this second layer;
Expose this at least one defect;
Insert any space produced by this exposure in this second layer; And
After this is inserted, cover this second layer with semiconductor covering layer;
Wherein, this cover layer has strain relaxation degree and the about 100/cm of about more than 80% 2following non-zero runs through difference row density.
2. method according to claim 1, wherein, this exposure comprises: optionally etch this second layer to this at least one defect.
3. method according to claim 1, wherein, this is inserted and comprises:
The packing layer of at least one filler material of conformal deposited is on this second layer with at least one defect through exposing; And
Etch this packing layer and stop on this second layer.
4. method according to claim 3, wherein, this at least one filler material comprises oxide.
5. method according to claim 1, wherein, this covering comprises:
This second layer with at least one defect through exposing sets up semiconductor layer of cover material; And
This cover layer of planarization.
6. method according to claim 5, wherein, this cladding material comprises semiconductor epitaxial material, and wherein, this foundation comprises this semiconductor epitaxial material of growing up.
7. method according to claim 1, wherein, this second semi-conducting material comprises at least one semi-conducting material of the iii-v from the periodic table of elements, and wherein, and this cover layer comprises and has the semiconductor epitaxial material that in face, lattice constant is approximately identical with this second layer.
8. method according to claim 7, wherein, this at least one semi-conducting material from the iii-v of the periodic table of elements one of to comprise in germanium, SiGe, InGaAsP, cadmium telluride and cadmium mercury telluride.
9. method according to claim 8, wherein, this at least one semi-conducting material comprises SiGe, and wherein, the percentage of germanium in this SiGe is in the scope of about 20% to about 100%.
10. method according to claim 1, wherein, this at least one first semi-conducting material of this substrate one of to comprise in silicon, GaAs and indium phosphide.
11. methods according to claim 1, wherein, this semiconductor substrate comprises bulk semiconductor substrate.
12. 1 kinds of semiconductor structures, comprising:
Semiconductor substrate, comprises at least one first semi-conducting material;
The second layer of at least one second semi-conducting material on the substrate; And
Semiconductor covering layer on this second layer;
Wherein, there is lattice between this substrate with this cover layer and do not mate, and wherein, this cover layer has strain relaxation degree and the about 100/cm of about more than 80% 2following non-zero runs through difference row density.
13. semiconductor structures according to claim 12, wherein, this semiconductor covering layer comprises and has approximately identical with this second layer epitaxial material of lattice constant in face.
14. semiconductor structures according to claim 12, wherein, this semiconductor covering layer comprises at least one semi-conducting material of the iii-v from the periodic table of elements.
15. semiconductor structures according to claim 14, wherein, this at least one semi-conducting material one of to comprise in germanium, SiGe, InGaAsP, cadmium telluride and cadmium mercury telluride.
16. semiconductor structures according to claim 15, wherein, this at least one semi-conducting material comprises SiGe.
17. semiconductor structures according to claim 16, wherein, the percentage of germanium in this SiGe is in the scope of about 20% to about 100%.
18. semiconductor structures according to claim 12, wherein, this semiconductor structure has the non-zero thickness being less than about 0.5 micron.
19. semiconductor structures according to claim 12, wherein, this at least one first semi-conducting material of this substrate one of to comprise in silicon, GaAs and indium phosphide.
20. semiconductor structures according to claim 12, wherein, this semiconductor substrate comprises bulk semiconductor substrate.
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