CN104979160A - Manufacturing method of semiconductor device and manufacturing method of TI-IGBT - Google Patents
Manufacturing method of semiconductor device and manufacturing method of TI-IGBT Download PDFInfo
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Abstract
The invention provides a manufacturing method of a semiconductor device and a manufacturing method of a TI-IGBT (triple-insulated gate bipolar transistor), wherein a region with lower requirement on local doping precision is doped in the manufacturing process of the semiconductor device, an ion cover is adopted in the local doping method to shield a semiconductor substrate, ions in a partial region pass through in the ion implantation process, and ions in the partial region are shielded, so that the local shielding of the semiconductor substrate is realized by only one step, and compared with the prior art in which the local shielding is realized by the procedures of gluing, exposure, development and the like, the manufacturing method provided by the invention greatly simplifies the process, shortens the production period and improves the production efficiency; and the manufacturing cost of the ion cover is greatly reduced relative to the cost of the photoetching machine and equipment required by each procedure in the photoetching process, so that the production cost of the semiconductor device can be reduced.
Description
Technical field
The present invention relates to the making field of semiconductor device, relate to a kind of manufacture method of semiconductor device and the manufacture method of TI-IGBT in particular.
Background technology
In fabrication of semiconductor device, usually need the doped region forming suitable type and debita spissitudo at the regional area of semiconductor substrate surface, and not adulterating in other regions, namely realizes local doping to Semiconductor substrate.
The doping of existing local comprises photoetching process and ion implantation technology, general photoetching process will carry out cleaning, drying to semiconductor substrate surface, linging, spin coating photoresist, soft baking, aim at exposure, rear baking, development, hard baking, etching, the operations such as detection, the region of carrying out adulterating is needed to form window at semiconductor substrate surface, the region of carrying out adulterating is not needed to form photoresist or film is covered at semiconductor substrate surface, then ion implantation is carried out to the Semiconductor substrate with photoresist or film, because the place outside window has photoresist or film to block, ion cannot enter into Semiconductor substrate, and place corresponding to window does not have photoresist or film to block, ion enters into Semiconductor substrate and forms doped region, thus form local doping on a semiconductor substrate.
Because photoetching process comprises multiple processing step, and need mask aligner to realize, when causing region lower to the requirement of local doping accuracy in semiconductor device manufacturing process to realize locally adulterating, technique is loaded down with trivial details and cost is higher.
Summary of the invention
In view of this, the invention provides a kind of manufacture method and TI-IGBT(Triplemode Integrate-Insulated Gate Bipolar Transistor of semiconductor device, the integrated insulated gate bipolar transistor of three-mode) manufacture method, with solve in prior art to local doping accuracy require lower semiconductor device realize local adulterate time, the loaded down with trivial details and problem that cost is larger of technique.
For achieving the above object, the invention provides following technical scheme:
A manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided;
Adulterate in a surface of described Semiconductor substrate first kind impurity, forms the first doped layer of all doping;
Described first doped layer is provided with the ion cover of through-hole pattern, and described through hole exposes the surface of described first doped layer the second doped region to be formed;
To the first doped layer doping Second Type impurity being provided with ion cover, in described second doping formation second doped region, doped region to be formed, all the other first doped layer region of not carrying out the doping of Second Type impurity form the first doped region.
Preferably, the detailed process of described doping first kind impurity and described doping Second Type impurity is: adopt ion implantor to carry out ion implantation.
Preferably, the described ion cover being provided with through-hole pattern on described first doped layer is specially: be arranged on by ion cover on described ion implantor, the Semiconductor substrate of the first doped layer that mobile described formation is all adulterated, the Semiconductor substrate of the first doped layer described formation all adulterated is aimed at described ion cover.
Preferably, the described ion cover being provided with through-hole pattern on described first doped layer is specially: the Semiconductor substrate of the first doped layer adopting fixture described ion cover and described formation all to be adulterated is fixed together after aiming at.
Preferably, described ion cover is sheet metal.
Preferably, described semiconductor device is any one in fast recovery diode, gate level turn-off thyristor, electron injection enhancement gate transistors, integrated gate commutated thyristor, MOS control type turn-off thyristor or integral gate pair transistor.
Present invention also offers another manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided;
The first ion cover of the first doped region pattern is provided with on a surface of described Semiconductor substrate;
The Semiconductor substrate being provided with the first ion cover is carried out to the doping of first kind impurity, form the first doped region;
The second ion cover of the second doped region pattern is provided with at the semiconductor substrate surface of formation first doped region;
The Semiconductor substrate being provided with the second ion cover is carried out to the doping of Second Type impurity, form the second doped region.
Preferably, the detailed process of the doping of described first kind impurity and the doping of described Second Type impurity is: adopt ion implantor to carry out ion implantation.
Preferably, described ion cover is sheet metal.
Preferably, described semiconductor device is any one in fast recovery diode, gate level turn-off thyristor, electron injection enhancement gate transistors, integrated gate commutated thyristor, MOS control type turn-off thyristor or integral gate pair transistor.
Meanwhile, present invention also offers the manufacture method of a kind of TI-IGBT, comprising:
S1, provide Semiconductor substrate, comprise multiple IGBT cellular in a surface of described Semiconductor substrate, described IGBT cellular comprises drift region, is positioned at the base on surface, described drift region, be positioned at two emitter regions of described base region surface, and cover the emitter metal of described two emitter regions;
S2, by thinning for another surface of described Semiconductor substrate, and adopting ion to cover on thinning of the described Semiconductor substrate upper structure forming described TI-IGBT, described structure comprises laid out in parallel and contrary the first doped region of doping type and the second doped region.
Preferably, described employing ion covers on thinning the upper structure forming described TI-IGBT of described Semiconductor substrate, specifically comprises:
S201, the first doped layer that formation is all adulterated on thinning of described Semiconductor substrate;
S202, on described first doped layer, be provided with the ion cover of the second doped region pattern, local ion doping is carried out to described first doped layer, form the second doped region, the first doped layer region that on described first doped layer, all the other do not carry out the doping of Second Type impurity forms the first doped region.
Preferably, described employing ion covers on thinning the upper structure forming described TI-IGBT of described Semiconductor substrate, specifically comprises:
S211, on thinning of described Semiconductor substrate, be provided with the first ion cover of the first doped region pattern, local ion doping carried out to the thinning face of described Semiconductor substrate, forms the first doped region;
S212, on thinning of described Semiconductor substrate, be provided with the second ion cover of the second doped region pattern, local ion doping carried out to the thinning face of described Semiconductor substrate, forms the second doped region.
Preferably, in step s 2 by described Semiconductor substrate another surface thinning after, before forming the structure of described TI-IGBT, also comprise:
All adulterated in the thinning surface of described Semiconductor substrate, form resilient coating on the thinning surface of described Semiconductor substrate.
Preferably, the base material of described Semiconductor substrate is any one in silicon, carborundum, gallium nitride, diamond or gallium phosphide.
Known via above-mentioned technical scheme, the manufacture method of semiconductor device provided by the invention, in semiconductor device manufacturing process, local doping accuracy is required to adulterate in lower region, described local doping method adopts ion cover to block Semiconductor substrate, in ion implantation process, the ion of subregion is passed through, the ion of subregion is blocked, only a step just achieves the partial occlusion to Semiconductor substrate, gluing is needed relative in prior art, exposure, the operations such as development realize partial occlusion, manufacture method provided by the invention enormously simplify technique, shorten the production cycle, improve production efficiency, and the cost of manufacture of ion cover reduces greatly relative to the cost of the equipment of each operation needs in mask aligner and photoetching process, and then the production cost of semiconductor device can be reduced.
Namely requiring in lower semiconductor device manufacturing process to local doping accuracy, manufacture method provided by the invention can replace the local realized by photoetching process and ion implantation technology in prior art to adulterate, because the manufacture method processing step in the present invention is simple, therefore can Simplified flowsheet, shorten the production cycle, and the ion cover adopted due to described method is relative to the mask aligner of costliness, and cost reduces greatly, can reduce the production cost of semiconductor device to a certain extent.
Present invention also offers the manufacture method of a kind of TI-IGBT, its front IGBT cellular adopts existing photoetching process to be formed, and when making the doped region at the described TI-IGBT back side, the above-mentioned manufacture method provided is adopted to be formed, because the doped region area at the TI-IGBT back side is larger, local doping accuracy requires lower, adopt expensive photoetching process to form local doping and cause larger waste, and TI-IGBT manufacture method provided by the invention, ion cover is adopted to realize local doping, not only simplify the technique for manufacturing back of TI-IGBT, also reduce the cost of manufacture of TI-IGBT.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
Fig. 1 is the manufacture method flow chart of a kind of semiconductor device provided by the invention;
A kind of ion cover mounting means that Fig. 2 provides for the embodiment of the present invention;
The another kind of ion cover mounting means that Fig. 3 provides for the embodiment of the present invention;
A kind of TI-IGBT manufacture method flow chart that Fig. 4 provides for the embodiment of the present invention;
A kind of TI-IGBT device substrate that Fig. 5 provides for the embodiment of the present invention;
A kind of concrete grammar flow chart of the step S2 that Fig. 6 provides for the embodiment of the present invention;
The process chart of a kind of formation the first doped layer that Fig. 7 provides for the embodiment of the present invention;
The process chart forming the second doped region on the first doped layer surface that Fig. 8 provides for the embodiment of the present invention;
A kind of TI-IGBT structure chart that Fig. 9 provides for the embodiment of the present invention;
The another kind of concrete grammar flow chart of the step S2 that Figure 10 provides for the embodiment of the present invention;
The another kind of TI-IGBT structure chart that Figure 11 provides for the embodiment of the present invention.
Embodiment
Just as described in the background section, local of the prior art doping method comprises photoetching process and ion implantation technology, because photoetching process comprises multiple step, and need mask aligner to realize, cause that local of the prior art doping process is loaded down with trivial details and cost is higher.
Inventor finds, occur that the reason of above-mentioned phenomenon is, in the process making semiconductor device, because dimensions of semiconductor devices is less, and the shape to doped region in Semiconductor substrate, the precise requirements of size and position is higher, usually mask aligner is adopted accurately to aim in prior art, realize local doping, but inventor also finds, the doped structure of some semiconductor device surface is to doped region shape, the precise requirements of size and position is lower, in this case, mask aligner is also used to carry out local doping, on the one hand, because photoetching process comprises multiple operation, technique is loaded down with trivial details, on the other hand, costly, and depreciation speed quickly, causes photoetching process costly for the imaging system of mask aligner and navigation system.
Based on this, inventor finds through research, there is provided a kind of manufacture method of semiconductor device to replace photoetching process, realize the making to the lower semiconductor device doped region of the precise requirements of shape, size and position, the manufacture method of described semiconductor device comprises:
Semiconductor substrate is provided;
Adulterate in a surface of described Semiconductor substrate first kind impurity, forms the first doped layer of all doping;
Described first doped layer is provided with the ion cover of through-hole pattern, and described through hole exposes the surface of described first doped layer the second doped region to be formed;
To the first doped layer doping Second Type impurity being provided with ion cover, in described second doping formation second doped region, doped region to be formed, all the other first doped layer region of not carrying out the doping of Second Type impurity form the first doped region.
From above-mentioned technical scheme, the manufacture method of semiconductor device provided by the invention, the photoresist of photoetching process formation in prior art or film is replaced to block semiconductor substrate surface owing to only adopting ion cover, form local doping, make local doping process only need a step to block just can realize with ion implantation, avoid prior art by gluing in photoetching process, exposure, the use of the operations such as development and mask aligner could realize partial occlusion, manufacture method provided by the invention not only simplify technique, improve production efficiency, the use of mask aligner can also be reduced, reduce the production cost of semiconductor device.
It is more than the core concept of the application, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from mode described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
The manufacture method of the semiconductor device provided in the present invention and the manufacture method of TI-IGBT are be provided below by several embodiment.
One embodiment of the present of invention disclose a kind of manufacture method of semiconductor device, and its flow chart as shown in Figure 1, comprising:
Step S101: Semiconductor substrate is provided.
The base material of described Semiconductor substrate is any one in silicon, carborundum, gallium nitride, diamond or gallium phosphide, does not limit in the present embodiment to this.
It should be noted that, the manufacture method of the semiconductor device that the present embodiment provides is mainly used in shape, in the manufacturing process of the doped region that the precise requirements of size and position is not high, such as power semiconductor FRD(Fast Recovery Diode, fast recovery diode), GTO(Gate Turn-Off Thyristor, gate level turn-off thyristor), IEGT(Injection Enhanced Gate Transistor, electron injection enhancement gate transistors), IGCT(Integrated Gate-Commutated Thyristor, integrated gate commutated thyristor), MTO(MOS Controlled Gate Turn-Off Thyristor, MOS control type turn-off thyristor), IGDT(Integrated Gate Dual Transistor, integral gate pair transistor) etc. back side short circuit collector electrode or anode manufacturing process in, because the doped region of its back side short circuit collector electrode or anode is to shape, the precise requirements of size and position is not too strict, without the need to realizing blocking Semiconductor substrate by the photoetching process with accurate alignment function, form local doping again.And to forming the doped region higher to the precise requirements of shape, size and position on a semiconductor substrate, in the present embodiment, the preferred photoetching process that adopts realizes local doping.
Step S102: adulterate first kind impurity on a surface of described Semiconductor substrate, forms the first doped layer of all doping;
Described first kind impurity can be N-type impurity can be also p type impurity, does not limit in the present embodiment to this.
Step S103: the ion cover being provided with through-hole pattern on described first doped layer, described through hole exposes the surface of described first doped layer the second doped region to be formed;
The cover of ion described in the present embodiment can be the thin slice formed by metal material processing, also can be the thin slice formed by the materials processing identical with Other substrate materials, in the present embodiment, the material of described ion cover is not limited, as long as described ion cover can in ion implantation process, realize the effect of blocking ion, in the present embodiment, preferred described ion cover is sheet metal.It should be noted that, on described ion cover with through-hole pattern with described Semiconductor substrate is treated doped region shape and position corresponding, described pattern is Semiconductor substrate needs carry out the figure that ion implantation forms doped region.Through-hole pattern on described ion cover can make ion pass through, thus forms the doped region with certain doping type on a semiconductor substrate.
Step S104: to the first doped layer doping Second Type impurity being provided with ion cover, in described second doping formation second doped region, doped region to be formed, all the other first doped layer region of not carrying out the doping of Second Type impurity form the first doped region.
In the present embodiment, ion implantor is preferably adopted to carry out ion doping to the first doped layer doping Second Type impurity being provided with ion cover.When adopting ion implantor to carry out ion implantation to described Semiconductor substrate, as shown in Figure 2, ion cover 1 can be formed " composite semiconductor substrate " by overlapping the clipping together of fixture 3 with Semiconductor substrate 2, then put into ion implantor and carry out ion implantation, it should be noted that, when ion cover and Semiconductor substrate being clipped together by fixture, when fixing between ion cover and Semiconductor substrate, can have certain gap, the proximity that is fixed as namely between ion cover and Semiconductor substrate is fixed; Can also directly contact between ion cover and Semiconductor substrate, the contact that is fixed as namely between ion cover and Semiconductor substrate is fixed.Conveniently ion cover and Semiconductor substrate are fixed together by fixture, in the present embodiment the appearance profile of preferred described ion cover and the appearance profile size of described Semiconductor substrate close, shape is similar.
The ion cover being provided with through-hole pattern in the present embodiment on described first doped layer is specially: the Semiconductor substrate of the first doped layer adopting fixture described ion cover and described formation all to be adulterated is fixed together after aiming at.
In addition, when adopting ion implantor to carry out ion implantation to described Semiconductor substrate, ion cover can not also be fixed together by fixture with Semiconductor substrate, especially when producing the semiconductor device of same or same type in enormous quantities, can be as shown in Figure 3, ion cover 1 is arranged on ion implantor 4, then multiple Semiconductor substrate 2 is placed on conveyer belt 5, by conveyer belt 5, Semiconductor substrate 2 is sent to successively the below of ion cover 1, thus realizes fast adulterating to the local of multiple Semiconductor substrate.
In the present embodiment, the ion cover that described first doped layer is provided with through-hole pattern is specially: be arranged on by ion cover on described ion implantor, the Semiconductor substrate of the first doped layer that mobile described formation is all adulterated, the Semiconductor substrate of the first doped layer described formation all adulterated is aimed at described ion cover.
The manufacture method of the semiconductor device provided in the present embodiment, the figuratum ion cover of band is adopted to block the surface of Semiconductor substrate, replace realizing the partial occlusion to Semiconductor substrate by photoetching processes such as gluing, exposure, developments in prior art, again ion implantation is carried out to the described semiconductor substrate surface with ion cover, because described ion cover throughhole portions can pass through ion, but not throughhole portions can block passing through of ion, thus realize local doping on a semiconductor substrate.Because the manufacture craft of described ion cover is simple, and cost is lower, relative to the local doping needing the photoetching process of and apparatus expensive loaded down with trivial details by technique to realize Semiconductor substrate in prior art, the manufacture method provided in the present embodiment is simpler, and cost is lower and can shorten production cycle of semiconductor device.
In addition, when thinner Semiconductor substrate forms doped region, because photoetching process comprises, the operations such as soft baking, rear baking and hard baking are carried out to Semiconductor substrate, in these techniques, due to high-temperature process, easily there is warpage or fragment in Semiconductor substrate, cause device bad or damage, reduce the rate of finished products of device, cause larger cost.And adopt in the hood-shaped process becoming locally to adulterate of ion, described ion cover is only near to or in contact with semiconductor substrate surface, without the need to carrying out multiple working procedure on the surface of Semiconductor substrate, and do not need to carry out high-temperature process to Semiconductor substrate, therefore, the probability that warpage or fragment appear in Semiconductor substrate can be reduced, thus improve rate of finished products, provide cost savings.
The manufacturing method of semiconductor device provided in an alternative embodiment of the invention comprises the following steps:
Semiconductor substrate is provided;
The first ion cover of the first doped region pattern is provided with on a surface of described Semiconductor substrate;
The Semiconductor substrate being provided with the first ion cover is carried out to the doping of first kind impurity, form the first doped region;
The second ion cover of the second doped region pattern is provided with at the semiconductor substrate surface of formation first doped region;
The Semiconductor substrate being provided with the second ion cover is carried out to the doping of Second Type impurity, form the second doped region.
With a upper embodiment unlike, two ion covers are adopted on the surface of Semiconductor substrate in the present embodiment, form different doped regions respectively at twice, the final dopant patterns forming needs, in the actual production process of semiconductor device, the selection of above-mentioned two kinds of manufacture methods can be carried out according to the structure of the doped region shape of semiconductor device structure or back anode, in the present invention, this is not limited.
A kind of TI-IGBT(Triple modeIntegrate-Insulated Gate Bipolar Transistor is disclosed in another embodiment of the present invention, the integrated insulated gate bipolar transistor of three-mode) manufacture method, described TI-IGBT is by IGBT(Insulated Gate Bipolar Transistor, insulated gate bipolar transistor), VDMOS(Vertical Double diffused MOS, vertical double diffused metal-oxide field-effect transistor), the power semiconductor that combines cleverly of the 26S Proteasome Structure and Function of FRD tri-kinds of devices.
The manufacture method of a kind of TI-IGBT disclosed in the present embodiment, as shown in Figure 4, comprising:
S1, provide Semiconductor substrate, comprise multiple IGBT cellular in a surface of described Semiconductor substrate, described IGBT cellular comprises drift region, is positioned at the base on surface, described drift region, be positioned at two emitter regions of described base region surface, and cover the emitter metal of described two emitter regions.
The forming process of described Semiconductor substrate is: provide semiconductor chip, the material of described semiconductor chip can be any one in silicon, carborundum, gallium nitride, diamond or gallium phosphide, in the present embodiment preferred with described semiconductor chip for silicon chip is described in detail; All doping are carried out to described semiconductor chip and forms drift region; By photoetching process, partial occlusion is carried out to described drift region, then carry out the doping type ion implantation contrary with drift region doping type, in the surface of described drift region, form base; Again by photoetching process, partial occlusion is carried out to described base, carries out the ion implantation that doping type is identical with drift region doping type, in the surface of described base, form two emitter regions; Finally on described two emitter regions, form emitter region metal, final formation IGBT cellular.
As shown in Figure 5, a surface of described semiconductor chip comprises multiple IGBT cellular, each IGBT cellular includes drift region 101, be positioned at the base 102 on surface, drift region 101, be positioned at two emitter regions 103 on surface, base 102, and cover the emitter metal 104 of described two emitter regions, also comprise insulating barrier 105 between emitter region 103 and emitter metal 104.It should be noted that, drift region 101 is identical with the doping type of emitter region 103, and all contrary with the doping type of base 102.Do not limit the concrete doping type of drift region, emitter region and base in the present embodiment, namely the doping type of described drift region can be N-type, can be also P type, specifically depending on actual conditions.
S2, by thinning for another surface of described Semiconductor substrate, and ion is adopted to cover on thinning of the described Semiconductor substrate upper structure forming described TI-IGBT.
Wherein, described structure comprises laid out in parallel and contrary the first doped region of doping type and the second doped region.
It should be noted that, the structure adopting ion to cover on thinning the upper described TI-IGBT that formed of described Semiconductor substrate described in the present embodiment can be realized by following two kinds of methods.First method, as shown in Figure 6, specifically comprises:
S201, the first doped layer 106 that formation is all adulterated on thinning of described Semiconductor substrate, as shown in Figure 7;
S202, on the first doped layer 106, be provided with the ion cover 107 of the second doped region pattern, local ion doping is carried out to described first doped layer, as shown in Figure 8, finally form the second doped region 108 at the back side of Semiconductor substrate, remainder on described first doped layer is the first doped region 109, is illustrated in figure 9 the final TI-IGBT formed.
Namely when the method forms the first doped region and the second doped region, block Semiconductor substrate by means of only primary ions cover, then form the second doped region in the original local surfaces forming the first doped layer by ion implantation.The doping type of wherein said first doped region and described second doped region is contrary, as, when the doping type of the first doped region is P type, the doping type of the second doped region is N-type, and the doping type of described first doped region is when being N-type, the doping type of the second doped region is P type, does not limit in the present embodiment to this.
Described employing ion covers on the described second method forming the structure of described TI-IGBT on thinning of described Semiconductor substrate, as shown in Figure 10, specifically comprises:
S211, on thinning of described Semiconductor substrate, be provided with the first ion cover of the first doped region pattern, local ion doping carried out to the thinning face of described Semiconductor substrate, forms the first doped region;
S212, on thinning of described Semiconductor substrate, be provided with the second ion cover of the second doped region pattern, local ion doping carried out to the thinning face of described Semiconductor substrate, forms the second doped region.
Namely when second method makes the first doped region and the second doped region, all have employed ion cover and carry out partial occlusion, form local doping.
It should be noted that, after thinning to another surface of described Semiconductor substrate, before forming TI-IGBT structure, can also comprise: all adulterated in the thinning surface of described Semiconductor substrate, form resilient coating on the thinning surface of described Semiconductor substrate.
As shown in figure 11, be the TI-IGBT with resilient coating 110.Wherein, resilient coating is positioned at surface, drift region, and the thickness of device drift region is reduced, thus the conducting resistance rate of device is reduced, and conduction voltage drop reduces; And undoped buffer layer type is identical with the doping type of device drift region, therefore resilient coating can in conjunction with a part of charge carrier, reach the effect of control device back side carrier injection rate, need the quantity of the charge carrier shifted out from device drift region when decreasing shutoff, thus the shutoff speed of device can be improved.
The partial occlusion to semiconductor substrate surface in TI-IGBT manufacturing process is realized by ion cover in the present embodiment, thus adopt simple technique to realize the formation of TI-IGBT structure, partial occlusion is realized owing to instead of photoetching process of the prior art, technique in its implementation procedure simplifies greatly, shorten the fabrication cycle of device, and in TI-IGBT manufacturing process, decrease the use of mask aligner, the production cost of TI-IGBT can be reduced to a certain extent.
In this specification, various piece adopts the mode of going forward one by one to describe, and what each some importance illustrated is the difference with other parts, between various piece identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (15)
1. a manufacture method for semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided;
Adulterate in a surface of described Semiconductor substrate first kind impurity, forms the first doped layer of all doping;
Described first doped layer is provided with the ion cover of through-hole pattern, and described through hole exposes the surface of described first doped layer the second doped region to be formed;
To the first doped layer doping Second Type impurity being provided with ion cover, in described second doping formation second doped region, doped region to be formed, all the other first doped layer region of not carrying out the doping of Second Type impurity form the first doped region.
2. manufacture method according to claim 1, is characterized in that, the detailed process of described doping first kind impurity and described doping Second Type impurity is: adopt ion implantor to carry out ion implantation.
3. manufacture method according to claim 2, it is characterized in that, the described ion cover being provided with through-hole pattern on described first doped layer is specially: be arranged on by ion cover on described ion implantor, the Semiconductor substrate of the first doped layer that mobile described formation is all adulterated, the Semiconductor substrate of the first doped layer described formation all adulterated is aimed at described ion cover.
4. manufacture method according to claim 2, it is characterized in that, the described ion cover being provided with through-hole pattern on described first doped layer is specially: the Semiconductor substrate of the first doped layer adopting fixture described ion cover and described formation all to be adulterated is fixed together after aiming at.
5. manufacture method according to claim 1, is characterized in that, described ion cover is sheet metal.
6. the manufacture method of semiconductor device according to claim 1, it is characterized in that, described semiconductor device is any one in fast recovery diode, gate level turn-off thyristor, electron injection enhancement gate transistors, integrated gate commutated thyristor, MOS control type turn-off thyristor or integral gate pair transistor.
7. a manufacturing method of semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided;
The first ion cover of the first doped region pattern is provided with on a surface of described Semiconductor substrate;
The Semiconductor substrate being provided with the first ion cover is carried out to the doping of first kind impurity, form the first doped region;
The second ion cover of the second doped region pattern is provided with at the semiconductor substrate surface of formation first doped region;
The Semiconductor substrate being provided with the second ion cover is carried out to the doping of Second Type impurity, form the second doped region.
8. manufacture method according to claim 7, is characterized in that, the detailed process of the doping of described first kind impurity and the doping of described Second Type impurity is: adopt ion implantor to carry out ion implantation.
9. manufacture method according to claim 7, is characterized in that, described ion cover is sheet metal.
10. the manufacture method of semiconductor device according to claim 7, it is characterized in that, described semiconductor device is any one in fast recovery diode, gate level turn-off thyristor, electron injection enhancement gate transistors, integrated gate commutated thyristor, MOS control type turn-off thyristor or integral gate pair transistor.
The manufacture method of 11. 1 kinds of TI-IGBT, is characterized in that, comprising:
S1, provide Semiconductor substrate, comprise multiple IGBT cellular in a surface of described Semiconductor substrate, described IGBT cellular comprises drift region, is positioned at the base on surface, described drift region, be positioned at two emitter regions of described base region surface, and cover the emitter metal of described two emitter regions;
S2, by thinning for another surface of described Semiconductor substrate, and adopting ion to cover on thinning of the described Semiconductor substrate upper structure forming described TI-IGBT, described structure comprises laid out in parallel and contrary the first doped region of doping type and the second doped region.
12. TI-IGBT manufacture methods according to claim 11, is characterized in that, described employing ion covers on thinning the upper structure forming described TI-IGBT of described Semiconductor substrate, specifically comprises:
S201, the first doped layer that formation is all adulterated on thinning of described Semiconductor substrate;
S202, on described first doped layer, be provided with the ion cover of the second doped region pattern, local ion doping is carried out to described first doped layer, form the second doped region, the first doped layer region that on described first doped layer, all the other do not carry out the doping of Second Type impurity forms the first doped region.
13. TI-IGBT manufacture methods according to claim 11, is characterized in that, described employing ion covers on thinning the upper structure forming described TI-IGBT of described Semiconductor substrate, specifically comprises:
S211, on thinning of described Semiconductor substrate, be provided with the first ion cover of the first doped region pattern, local ion doping carried out to the thinning face of described Semiconductor substrate, forms the first doped region;
S212, on thinning of described Semiconductor substrate, be provided with the second ion cover of the second doped region pattern, local ion doping carried out to the thinning face of described Semiconductor substrate, forms the second doped region.
14. TI-IGBT manufacture methods according to claim 11-13 any one, is characterized in that, in step s 2 by after thinning for another surface of described Semiconductor substrate, before forming the structure of described TI-IGBT, also comprise:
All adulterated in the thinning surface of described Semiconductor substrate, form resilient coating on the thinning surface of described Semiconductor substrate.
15. TI-IGBT manufacture methods according to claim 11, is characterized in that, the base material of described Semiconductor substrate is any one in silicon, carborundum, gallium nitride, diamond or gallium phosphide.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410135996.7A CN104979160A (en) | 2014-04-04 | 2014-04-04 | Manufacturing method of semiconductor device and manufacturing method of TI-IGBT |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100140658A1 (en) * | 2008-12-10 | 2010-06-10 | Denso Corporation | Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode |
| CN102376759A (en) * | 2010-08-17 | 2012-03-14 | 丰田自动车株式会社 | Semiconductor device having both igbt area and diode area |
| US20130001639A1 (en) * | 2010-04-02 | 2013-01-03 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device comprising semiconductor substrate having diode region and igbt region |
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2014
- 2014-04-04 CN CN201410135996.7A patent/CN104979160A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100140658A1 (en) * | 2008-12-10 | 2010-06-10 | Denso Corporation | Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode |
| US20130001639A1 (en) * | 2010-04-02 | 2013-01-03 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device comprising semiconductor substrate having diode region and igbt region |
| CN102376759A (en) * | 2010-08-17 | 2012-03-14 | 丰田自动车株式会社 | Semiconductor device having both igbt area and diode area |
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