CN104952874A - Three-dimensional structure nonvolatile memory, memory cell structure and manufacture method thereof - Google Patents
Three-dimensional structure nonvolatile memory, memory cell structure and manufacture method thereof Download PDFInfo
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Abstract
The invention provides a three-dimensional structure nonvolatile memory, a memory cell structure and a manufacture method thereof. The manufacture method of the memory cell structure includes forming a first dielectric layer on a first metal layer; forming a first through hole in the first dielectric layer and allowing a part of the first dielectric layer to be left at the bottom of the first through hole; forming a first barrier layer on the inner surface of the first through hole; forming a second metal layer arranged in the first through hole in a filling manner; forming a second dielectric layer on the second metal layer and the first dielectric layer; forming a second through hole in the second dielectric layer and allowing a part of the second dielectric layer to be left at the bottom of the second through hole, wherein the second through hole is above the second metal layer; forming a second barrier layer on the inner surface of the second through hole; forming a third metal layer arranged in the second through hole in a filling manner; combining the first dielectric layer left at the bottom of the first through hole with the first barrier layer so as to form a first transition layer and combining the second dielectric layer left at the bottom of the second through hole with the second barrier layer so as to form a second transition layer.
Description
Technical field
The present invention relates to a kind of memory with and manufacture method, and in particular to a kind of 3 dimension nonvolatile memories of structures and memory cell structure and manufacture method thereof.
Background technology
As everyone knows, nonvolatile memory (non-volatile memory) can continue when power-off to preserve storing data of its inside.And use the most general nonvolatile memory to be flash memory (flash memory) now.Flash memory utilizes floating gate transistors (floating gate transistor) as storage element.And its storing state can be determined according to the quantity of electric charge be stored on floating grid.
Recently, a kind of nonvolatile memory of brand-new framework is suggested.This nonvolatile memory is called resistive random access memory (Resistive Random Access Memory, RRAM), and its storage unit is a resistance element (resistive element).
Please refer to Fig. 1, its illustrate nonvolatile memory schematic diagram into known tool resistance element, it is exposed in U.S. Patent number US8,107,274.This nonvolatile memory 300 has the memory cell of (1T+1R), and 1T represents a transistor (transistor), and 1R represents a resistance (resistor).That is this nonvolatile memory 300 comprises transistor 310 and a resistance element 320, and resistance element 320 is connected to transistor 310.Wherein, resistance element 320 is variable and recoverable resistance element (variable and reversible resistive element).
Transistor 310 comprises: substrate 318, gate dielectric layer (gate dielectric layer) 313, grid 312, first source/drain 314, second source/drain 316, distance piece (spacer) 319.
Resistance element 320 comprises: the connector module (conductive plug module) 130 of transition metal oxide layer (transition metal oxide layer) 110, dielectric layer 150, conduction.Wherein, dielectric layer 150 is formed in the first source/drain 314, and the connector module 130 of conduction is positioned on transition metal oxide layer 110.
Moreover the connector module 130 of conduction comprises a metal plug 132 and a barrier layer (barrier layer) 134.Metal plug 132 to be vertically configured on transition metal oxide layer 110 and can to conduct electricity to transition metal oxide layer 110, and barrier layer 134 is coated with metal plug 132.Wherein, transition metal oxide layer 110 reacts rear by dielectric layer 150 and barrier layer 134 formed, and transition metal oxide layer 110 can change its resistance value.
Because transistor 310 can occupy the layout area of substrate 318, make the density of memory cells of the nonvolatile memory 300 of this (1T+1R) structure lower.Therefore, the nonvolatile memory proposing a kind of high density of memory cells be the present invention object for reaching.
Summary of the invention
The present invention is a kind of memory cell structure of nonvolatile memory, comprising: a first metal layer; One first dielectric layer, is formed at above this first metal layer, wherein, has one first and penetrate hole in this first dielectric layer; One First Transition layer, is formed at this and first penetrates bottom hole and between this first metal layer; One second metal level, is formed at this and first penetrates in hole and to be contacted with this First Transition layer; One second dielectric layer, is formed at this second metal level and this first dielectric layer, wherein, has one second and penetrate hole in this second dielectric layer; One second transition zone, is formed at this and second penetrates bottom hole and between this second metal level; And one the 3rd metal level, be formed at this and second penetrate in hole and to be contacted with this second transition zone.
The present invention is the manufacture method of memory cell structure in a kind of nonvolatile memory, comprises the following steps: to form one first dielectric layer above a first metal layer; Formed in this first dielectric layer and one first penetrate hole, and this first penetrates this first dielectric layer of residual fraction bottom hole; First penetrate hole inner surface in this and be formed at one first barrier layer; Form one second metal level to be filled in this and first to penetrate hole; One second dielectric layer is formed in this second metal level and this first dielectric layer; Formed in this second dielectric layer and one second penetrate hole, and this second penetrates this second dielectric layer of residual fraction bottom hole, wherein this second penetrates hole and is positioned at this second metal layer; Second penetrate hole inner surface in this and be formed at one second barrier layer; Form one the 3rd metal level to be filled in this and second to penetrate hole; And first to penetrate bottom hole this residual first dielectric layer with this first barrier layer to form a First Transition layer in conjunction with this, and second penetrate this second dielectric layer and this second barrier layer of remaining bottom hole to form one second transition zone in conjunction with this.
The present invention is a kind of nonvolatile memory, comprising: one first plain conductor; One first memory cell structure, the first end of this first memory cell structure is connected to this first plain conductor; One second memory cell structure, the first end of this second memory cell structure is connected to this first plain conductor; One second plain conductor, is connected to the second end of this first memory cell structure; One the 3rd plain conductor, is connected to the second end of this second memory cell structure; One the 3rd memory cell structure, the first end of the 3rd memory cell structure is connected to this second plain conductor; One the 4th memory cell structure, the first end of the 4th memory cell structure is connected to the 3rd plain conductor; And one the 4th plain conductor, be connected to the second end of the 3rd memory cell structure and the second end of the 4th memory cell structure; Wherein, this first memory cell structure, this second memory cell structure, the 3rd memory cell structure and all comprise the First Transition layer and one second transition zone that are connected in series in the 4th memory cell structure.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating accompanying drawing, being described in detail below:
Accompanying drawing explanation
Fig. 1 illustrate nonvolatile memory schematic diagram into known tool resistance element.
Fig. 2 A to Fig. 2 J illustrate manufacturing process into the memory cell structure of nonvolatile memory of the present invention and schematic equivalent circuit thereof.
Fig. 3 A to Fig. 3 D illustrate manufacturing process into the memory cell array of nonvolatile memory of the present invention and schematic equivalent circuit thereof.
Wherein, description of reference numerals is as follows:
110: transition zone
130: the connector module of conduction
132: metal plug
134: barrier layer
150: dielectric layer
300: nonvolatile memory
310: transistor
312: grid
313: gate dielectric layer
314: the first source/drain
316: the second source/drain
318: substrate
319: distance piece
320: resistance element
510: the first metal layer
512: the first dielectric layers
514: the first barrier layers
516: the second metal levels
518: First Transition layer
522: the second dielectric layers
524: the second barrier layers
526: the three metal levels
528: the second transition zones
530: memory cell structure
Embodiment
The present invention is a kind of nonvolatile memory of tool resistance element and manufacture method thereof and memory cell structure.The present invention is the nonvolatile memory of design (1D+1R) memory cell structure, and 1D represents a diode (diode), and 1R represents a resistance (resistor).And utilize the multiple memory cell structure of three-dimensional configuration, the nonvolatile memory of high density of memory cells can be formed.Below the present invention is introduced in detail.
Please refer to Fig. 2 A to Fig. 2 J, its illustrate manufacturing process into the memory cell structure of nonvolatile memory of the present invention and schematic equivalent circuit thereof.Wherein, Fig. 2 A to Fig. 2 E illustrate as forming the step of resistance element, and Fig. 2 F to Fig. 2 H institute illustrates the step into formation diode.
As shown in Figure 2 A, a first surface of a first metal layer 510 is formed one first dielectric layer 512 that thickness is h1, this first dielectric layer 512 can be metal intermetallic dielectric layer (Inter-Metal Dielectric layer, be called for short IMD layer), its material can be silicon dioxide (SiO
2).Then, carry out etching step, it is that one first of w1 penetrates hole (via) that the first dielectric layer 512 is formed width, and the residual of the first dielectric layer 512 is still arranged at the first bottom penetrating hole.Substantially, memory cell structure of the present invention is manufactured on semiconductor substrate.Moreover the first metal layer 510 is the plain conductor of first direction, and its material can be copper, aluminium or tungsten.
As shown in Figure 2 B, penetrate upper opening place, hole first, then carry out an etching step, make the first width penetrating upper opening place, hole be greater than w1, and the residual of the first dielectric layer 512 of a1 thickness is still arranged at the first bottom penetrating hole.
As shown in Figure 2 C, penetrate on hole inner surface and the first dielectric layer 512 first and form one first barrier layer 514, its material can be Hf, HfO
x, HfO
xn
y, Mg, MgO
x, MgO
xn
y, NiO
x, NiO
xn
y, TaO
xn
y, Ta, TaO
x, TaN
x, TiO
xn
y, Ti, TiO
x, TiN
x.
Then, as shown in Figure 2 D, the first barrier layer 514 forms one second metal level 516, and its material can be copper, aluminium or tungsten.Then, as shown in Figure 2 E, remove the second metal level 516, and expose the first dielectric layer 512, make the second metal level 516 residue in first and penetrate in hole.Wherein, cmp (Chemical mechanical polish is called for short CMP) technique or etch process can be utilized to remove the second metal level 516.
Then, as shown in Figure 2 F, the surface of the first dielectric layer 512 and the second metal level 516 forms one second dielectric layer 522 that thickness is h2, and this second dielectric layer 512 can be metal intermetallic dielectric layer (IMD layer), and its material can be silicon dioxide (SiO
2).Then, carry out etching step, it is that one second of w2 penetrates hole (via) that the second dielectric layer 522 is formed width, and the residual of the second dielectric layer 522 is still arranged at the second bottom penetrating hole.
Then, as shown in Figure 2 G, penetrate upper opening place, hole second, then carry out an etching step, make second to penetrate above hole and form a groove, and the width of this groove is greater than w2.And the residual of the second dielectric layer 522 of a2 thickness is still arranged at the second bottom penetrating hole.Then, formation one second barrier layer 524 is covered in the second material penetrating hole inner surface, groove and the second dielectric layer 522, second barrier layer 524 and can be Hf, HfO
x, HfO
xn
y, Mg, MgO
x, MgO
xn
y, NiO
x, NiO
xn
y, TaO
xn
y, Ta, TaOx, TaN
x, TiO
xn
y, Ti, TiO
x, TiN
x.Afterwards, the second barrier layer 524 forms one the 3rd metal level 526, and its material can be copper, aluminium or tungsten.
Then, as illustrated in figure 2h, remove the 3rd metal level 526, and expose the second dielectric layer 522, make the 3rd metal level 526 residue in first and penetrate in hole and groove.Moreover the 3rd metal level 526 be formed in groove is the plain conductor of second direction, and first direction and second direction orthogonal.
Then, as shown in figure 2i, carry out a reactions steps after namely form the single memory cell structure of nonvolatile memory of the present invention.That is, after carrying out reactions steps, penetrate the first dielectric layer 512 bottom hole by making first and the first barrier layer 514 carries out reacting to be combined into First Transition layer (transition layer) 518; And make second to penetrate the second dielectric layer 522 bottom hole and the second barrier layer 524 carries out reacting to be combined into the second transition zone 528.Wherein, First Transition layer 518 can be considered a resistance element; Second transition zone 528 can be considered a diode.Moreover the material of ㄧ transition zone 518 and the second transition zone 528 can be HfO
x, HfO
xn
y, MgO
x, MgO
xn
y, NiO
x, NiO
xn
y, TaO
xn
y, TaO
x, TaN
x, TiO
xn
y, TiO
x, TiN
x.Wherein, HfO
x, MgO
x, NiO
x, TaO
x, TiO
xbelong to transition metal oxide layer (transition metal oxide layer); TaN
x, TiN
xbelong to transition metal nitride layer (transition metal nitride layer); HfO
xn
y, MgO
xn
y, NiO
xn
y, TaO
xn
y, TiO
xn
ybelong to transition metal oxymtride dielectric layer (transition metal nitrogen oxide dielectric layer).
According to embodiments of the invention, the first depth-to-width ratio penetrating hole is h1/w1 (aspect ratio), and the depth-to-width ratio h2/w2 that second penetrates hole.And control first and penetrate the depth-to-width ratio that hole and second penetrates hole, first can be controlled and penetrate hole and second and penetrate the first dielectric layer 512 residual bottom hole and the thickness of the second dielectric layer 522.So can control transition zone and become diode or resistance element.
Finally, as shown in fig. 2j, it is the equivalent electric circuit of the single memory cell structure of nonvolatile memory of the present invention.Wherein, the first metal layer 510 is that the plain conductor of first direction can be used as bit line (bitline), 3rd metal level 526 is that the plain conductor of first direction can be used as character line (word line), and memory cell structure 530 is vertically connected between the first metal layer 510 and the 3rd metal level 526.Moreover, contact resistance element 518 between the first metal layer 510 and the second metal level 516; Diode 528 is connected between second metal level 516 with the 3rd metal level 526.Certainly, the present invention also can make to be connected diode between the first metal layer with the second metal level, and contact resistance element between the second metal level and the 3rd metal level.
According to embodiments of the invention, in character line from different voltage and electric current are provided between bit line, can set or remove the resistance value of resistance element 518 in this memory cell structure 530 of setting.For example, when the formula cycle, there is provided 3V voltage as a setting voltage (Vset) between character line and bit line, resistance element 518 will be made to become a set condition (or being called the first storing state), and now resistance element 518 possesses low-resistance value.Moreover, 1V voltage is provided simultaneously and removes setting voltage (Vreset) and electric current (Ireset) as one between 10 μ A electric current character lines and bit line, resistance element 518 will be made to become a releasing set condition (or being called the second storing state), and now resistance element 518 possesses high resistance.
In formula week after date, resistance element can be set condition (the first storing state) by formula or remove set condition (the second storing state).When read cycle, only need provide the reading voltage (Vread) of 0.4V between character line and bit line, reading electric current (or memory cell current) size that can produce according to correspondence learns that the resistance element in this memory cell structure is the first storing state or the second storing state.Therefore, the memory cell structure of nonvolatile memory of the present invention can store two kinds of storing states really.
The above-mentioned manufacture method being illustrated as formation single memory cell structure.And reuse above-mentioned technique, the memory cell array (cell matrix) of volatile storage can be formed.Be described in detail as follows:
Please refer to Fig. 3 A to Fig. 3 D, its illustrate manufacturing process into the memory cell array of nonvolatile memory of the present invention and schematic equivalent circuit thereof.Wherein, detailed resistance element and the manufacturing step of diode can refer to Fig. 2 A to Fig. 2 H, repeat no more herein.
As shown in Figure 3A, the first metal layer comprises plain conductor BL0, BL1 of many first directions, and plain conductor BL0, BL1 of those first directions are as bit line.Wherein, those plain conductors BL0, BL1 can be formed on the surface of a substrate (not shown).
Then, as shown in Figure 3 B, on the first metal layer, after sequentially carrying out forming the step of resistance element and the step of formation diode, multiple memory cell structure can be formed on plain conductor BL0, BL1.
For the memory cell structure C0 ~ C2 on plain conductor BL0, in memory cell structure C0, the first end of resistance element is connected to plain conductor BL0, second end of resistance element is connected to a node p, the first end of diode is connected to node p, and the second end of diode is connected to plain conductor WL0; In memory cell structure C1, the first end of resistance element is connected to plain conductor BL0, and the second end of resistance element is connected to a node q, and the first end of diode is connected to node q, and the second end of diode is connected to plain conductor WL1; In memory cell structure C3, the first end of resistance element is connected to plain conductor BL0, and the second end of resistance element is connected to a node r; The first end of diode is connected to node r, and the second end of diode is connected to plain conductor WL2.Wherein, those nodes p, q, r in memory cell structure C0 ~ C2 are positioned on one second metal level.
Moreover as shown in Figure 3 B, plain conductor WL0, WL1, WL2 of many are second direction, and those plain conductors WL0, WL1, WL2 of second direction are as character line.Moreover, many strip metals wire WL0, WL1, WL2 position of second direction at the 3rd metal level, and first direction and second direction orthogonal.
As shown in Figure 3 C, on the 3rd metal level, after sequentially carrying out forming the step of diode and the step of formation resistance element, multiple memory cell structure can be formed on plain conductor WL0, WL1, WL2.
For memory cell structure C3 ~ C5, in memory cell structure C3, the first end of diode is connected to plain conductor WL0, second end of diode is connected to node x, and the first end of resistance element is connected to node x, and the second end of resistance element is connected to plain conductor BL2; In memory cell structure C4, the first end of diode is connected to plain conductor WL1, and the second end of diode is connected to node y, and the first end of resistance element is connected to node y, and the second end of resistance element is connected to plain conductor BL2; In memory cell structure C5, the first end of diode is connected to plain conductor WL2, and the second end of diode is connected to node z, and the first end of resistance element is connected to node z, and the second end of resistance element is connected to plain conductor BL2.Wherein, those node x, y, z in memory cell structure C3 ~ C5 are positioned on one the 4th metal level.
Moreover as shown in Figure 3 C, plain conductor BL2, BL3 of many are first direction, and those plain conductors BL2, BL3 of first direction are as bit line.Moreover many strip metals wire BL2, BL3 position of first direction is at the 5th metal level.
In like manner, repeat the step of Fig. 3 B and Fig. 3 C, can continue stacking go out as the structure of 3D.That is, form plain conductor WL3, WL4, WL5 of second direction and plain conductor BL4, BL5 of first direction, the i.e. memory cell structure of its correspondence.Because detailed manufacturing step is same as Fig. 3 B and Fig. 3 C, repeat no more herein.
When above-mentioned memory cell array structure is formed, then improve temperature in reaction chamber (chamber), to carry out a reactions steps, the connecting interface of memory cell array dielectric layer and barrier layer should be formed transition zone.So, the memory cell array of nonvolatile memory of the present invention is just completed.
In like manner, the formula cycle of the memory cell array of nonvolatile memory is identical with the operation principles of read cycle, repeats no more herein.
From above explanation, the present invention proposes a kind of nonvolatile memory of tool resistance element and manufacture method thereof and memory cell structure.Utilize the memory cell structure of three-dimensional configuration (1D+1R), the nonvolatile memory of high density of memory cells can be formed.
Moreover the present invention forms resistance element and the diode of serial connection between upper and lower two strip metal wires.Certainly, the present invention does not limit the formation order of resistance element and diode.The present invention can first carry out forming the step that the step of resistance element carries out being formed diode again; Or the step first can carrying out being formed diode carries out the step forming resistance element again.
Moreover the present invention does not limit setting voltage (Vset), releasing setting voltage (Vreset), releasing setting electric current (Ireset) of memory cell structure and reads voltage (Vread).Those skilled in the art certainly can revise setting voltage provided by the present invention, remove setting voltage, remove setting electric current and read voltage, and apply to formula cycle and the read cycle of nonvolatile memory.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (27)
1. a memory cell structure for nonvolatile memory, comprising:
One the first metal layer;
One first dielectric layer, is formed at above this first metal layer, wherein, has one first and penetrate hole in this first dielectric layer;
One First Transition layer, is formed at this and first penetrates bottom hole and between this first metal layer;
One second metal level, is formed at this and first penetrates in hole and to be contacted with this First Transition layer;
One second dielectric layer, is formed at this second metal level and this first dielectric layer, wherein, has one second and penetrate hole in this second dielectric layer;
One second transition zone, is formed at this and second penetrates bottom hole and between this second metal level; And
One the 3rd metal level, is formed at this and second penetrates in hole and to be contacted with this second transition zone.
2. memory cell structure according to claim 1, wherein, this First Transition layer and this second transition zone one of them be a resistance element, and another is a diode.
3. memory cell structure according to claim 2, wherein, in a set condition, this resistance element possesses low-resistance value; And remove set condition in one, this resistance element possesses high resistance.
4. memory cell structure according to claim 1, wherein, this memory cell structure also comprises one first barrier layer, is formed at this first inner surface penetrating hole; And one second barrier layer, be formed at this second inner surface penetrating hole.
5. memory cell structure according to claim 4, wherein the material of this first barrier layer and this second barrier layer is Hf, HfO
x, HfO
xn
y, Mg, MgO
x, MgO
xn
y, NiO
x, NiO
xn
y, TaO
xn
y, Ta, TaO
x, TaN
x, TiO
xn
y, Ti or TiO
x, TiN
x.
6. memory cell structure according to claim 4, wherein, this First Transition layer first to be penetrated bottom hole this residual first dielectric layer by this and is combined with this first barrier layer and is formed; And this second transition zone second to be penetrated bottom hole this residual second dielectric layer by this and is combined with this second barrier layer and is formed.
7. memory cell structure according to claim 6, wherein, the material of this First Transition layer and this second transition zone is HfO
x, HfO
xn
y, MgO
x, MgO
xn
y, NiO
x, NiO
xn
y, TaO
xn
y, TaO
x, TaN
x, TiO
xn
y, TiO
x, or TiN
x.
8. memory cell structure according to claim 1, wherein, also comprises one first plain conductor of first direction, is contacted with this First Transition layer in this first metal layer; Also comprise one second plain conductor of second direction in 3rd metal level, be formed at this and second penetrate hole overhead surface.
9. memory cell structure according to claim 8, wherein, this first direction is mutually vertical with this second direction.
10. memory cell structure according to claim 1 wherein, this first metal layer, this second metal level, is copper, aluminium or tungsten with the material of the 3rd metal level.
11. memory cell structures according to claim 1, wherein, the material of this first dielectric layer and this second dielectric layer is SiO
2.
In 12. 1 kinds of nonvolatile memories, the manufacture method of memory cell structure, comprises the following steps:
One first dielectric layer is formed above a first metal layer;
Formed in this first dielectric layer and one first penetrate hole, and this first penetrates this first dielectric layer of residual fraction bottom hole;
First penetrate hole inner surface in this and be formed at one first barrier layer;
Form one second metal level to be filled in this and first to penetrate hole;
One second dielectric layer is formed in this second metal level and this first dielectric layer;
Formed in this second dielectric layer and one second penetrate hole, and this second penetrates this second dielectric layer of residual fraction bottom hole, wherein this second penetrates hole and is positioned at this second metal layer;
Second penetrate hole inner surface in this and be formed at one second barrier layer;
Form one the 3rd metal level to be filled in this and second to penetrate hole; And
First to penetrate bottom hole this residual first dielectric layer with this first barrier layer and then form a First Transition layer in conjunction with this, and second penetrate this second dielectric layer and this second barrier layer of remaining bottom hole in conjunction with this and then form one second transition zone.
13. manufacture methods according to claim 12, wherein, this First Transition layer and this second transition zone one of them be a resistance element, and another is a diode.
14. manufacture methods according to claim 13, wherein, in a set condition, this resistance element possesses low-resistance value; And remove set condition in one, this resistance element possesses high resistance.
15. manufacture methods according to claim 12, wherein the material of this first barrier layer and this second barrier layer is Hf, HfO
x, HfO
xn
y, Mg, MgO
x, MgO
xn
y, NiO
x, NiO
xn
y, TaO
xn
y, Ta, TaO
x, TaN
x, TiO
xn
y, Ti, TiO
x, or TiN
x.
16. manufacture methods according to claim 12, wherein, the material of this First Transition layer and this second transition zone is HfO
x, HfO
xn
y, MgO
x, MgO
xn
y, NiO
x, NiO
xn
y, TaO
xn
y, TaO
x, TaN
x, TiO
xn
y, TiO
x, or TiN
x.
17. manufacture methods according to claim 12, wherein, also comprise one first plain conductor of first direction, are contacted with this First Transition layer in this first metal layer; Also comprise one second plain conductor of second direction in 3rd metal level, be formed at this and second penetrate hole overhead surface.
18. manufacture methods according to claim 17, wherein, this first direction is mutually vertical with this second direction.
19. manufacture methods according to claim 12 wherein, this first metal layer, this second metal level, are copper, aluminium or tungsten with the material of the 3rd metal level.
20. manufacture methods according to claim 12, wherein, the material of this first dielectric layer and this second dielectric layer is SiO
2.
21. 1 kinds of nonvolatile memories, comprising:
One first plain conductor;
One first memory cell structure, the first end of this first memory cell structure is connected to this first plain conductor;
One second memory cell structure, the first end of this second memory cell structure is connected to this first plain conductor;
One second plain conductor, is connected to the second end of this first memory cell structure;
One the 3rd plain conductor, is connected to the second end of this second memory cell structure;
One the 3rd memory cell structure, the first end of the 3rd memory cell structure is connected to this second plain conductor;
One the 4th memory cell structure, the first end of the 4th memory cell structure is connected to the 3rd plain conductor; And
One the 4th plain conductor, is connected to the second end of the 3rd memory cell structure and the second end of the 4th memory cell structure;
Wherein, this first memory cell structure, this second memory cell structure, the 3rd memory cell structure and all comprise the First Transition layer and one second transition zone that are connected in series in the 4th memory cell structure.
22. nonvolatile memories according to claim 21, wherein, this First Transition layer and this second transition zone one of them be a resistance element, and another is a diode.
23. nonvolatile memories according to claim 22, wherein, in a set condition, this resistance element possesses low-resistance value; And remove set condition in one, this resistance element possesses high resistance.
24. nonvolatile memories according to claim 21, wherein, the material of this First Transition layer and this second transition zone is HfO
x, HfO
xn
y, MgO
x, MgO
xn
y, NiO
x, NiO
xn
y, TaO
xn
y, TaO
x, TaN
x, TiO
xn
y, TiO
x, or TiN
x.
25. nonvolatile memories according to claim 21, wherein, this first plain conductor and the 4th plain conductor present a first direction and arrange; This second plain conductor and this privates present a second direction layer and arrange, and this first direction is mutually vertical with this second direction.
26. nonvolatile memories according to claim 21, wherein, this first plain conductor and the 4th plain conductor are as bit line; This second plain conductor and this privates are as character line.
27. nonvolatile memories according to claim 21, wherein, the material of this first plain conductor, this second plain conductor, the 3rd plain conductor and the 4th plain conductor is copper, aluminium or tungsten.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040159828A1 (en) * | 2002-08-02 | 2004-08-19 | Unity Semiconductor, Inc. | Resistive memory device with a treated interface |
| CN101315942A (en) * | 2007-05-30 | 2008-12-03 | 三星电子株式会社 | Resistive random access memory device |
| CN101667588A (en) * | 2008-09-04 | 2010-03-10 | 旺宏电子股份有限公司 | High density resistance based semiconductor device and manufacturing method thereof |
| US20130122651A1 (en) * | 2010-07-27 | 2013-05-16 | Panasonic Corporation | Manufacturing method of non-volatile memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040159828A1 (en) * | 2002-08-02 | 2004-08-19 | Unity Semiconductor, Inc. | Resistive memory device with a treated interface |
| CN101315942A (en) * | 2007-05-30 | 2008-12-03 | 三星电子株式会社 | Resistive random access memory device |
| CN101667588A (en) * | 2008-09-04 | 2010-03-10 | 旺宏电子股份有限公司 | High density resistance based semiconductor device and manufacturing method thereof |
| US20130122651A1 (en) * | 2010-07-27 | 2013-05-16 | Panasonic Corporation | Manufacturing method of non-volatile memory device |
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