CN104952795A - Three-dimensional integrated circuit device structure and manufacturing method thereof - Google Patents
Three-dimensional integrated circuit device structure and manufacturing method thereof Download PDFInfo
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- CN104952795A CN104952795A CN201510226919.7A CN201510226919A CN104952795A CN 104952795 A CN104952795 A CN 104952795A CN 201510226919 A CN201510226919 A CN 201510226919A CN 104952795 A CN104952795 A CN 104952795A
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- electronic circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
Abstract
The invention is applicable to the field of integrated circuit production and provides a manufacturing method of a three-dimensional integrated circuit. The method includes the steps of A, providing a substrate; B, forming an amorphous semiconductor layer on the substrate, performing metal induced side crystallization, and manufacturing a first electronic circuit component layer accordingly; C, forming a passivation oxidation layer on the ith electronic circuit component layer, and manufacturing the i+1th electronic circuit component layer on the passivation oxidation layer, wherein i is a natural number with the initial value being 1; D, electrically connecting each electronic circuit component in the i+1th electronic circuit component layer to corresponding electronic circuit components of previously formed electronic circuit component layers; E, repeating the step B to the step D in a way that the step length of i is 1 until the integrated circuit with the target layer is manufactured. The method has the advantages that the electronic circuit components can be manufactured simply and flexibly on any existing structures, a 3D structure with numerous layers of circuit components can be manufactured, and the problem that a polycrystalline silicon thin film transistor is poor in performance can be solved.
Description
Technical field
The invention belongs to technical field of integrated circuits, particularly relate to a kind of three dimensional integrated circuits device architecture and preparation method thereof.
Background technology
The future of integrated circuit (IC) (Integrated Circuit) depends on 3-D (three-Dimensional, three-dimensional) structure, the advantage that multilayer IC circuit not only has SOI device is possessed in addition as reduced interconnection length by perpendicular interconnection, reducing chip area, reduce RC time delay, improving the advantages such as circuit level.
3-D integrated circuit is the structure adopting device layer successively to superpose, and is isolated between adjacent layer by insulation film.The challenge of current development 3-D technology has:
Make the second layer or more high-rise in high-quality monocrystalline silicon formation device on the insulating material.Current preparation method is generally laser recrystallization technique and selective epitaxial outgrowth technology.But these methods are all extremely complicated, easily cause dislocation defects.Latest find one method is with germanium ion side direction recrystallization polysilicon membrane, but the crystallite dimension of this kind of method is restricted to several microns.
Have also appeared a kind of novel recrystallization method at present---metal inducement side crystallization (Metal Induced Lateral Crystallization, MILC), it manufactures high-quality Si film by the mode of formation Thin Film Transistor (TFT) (Thin Film Transistor:TFT).First, deposit on silicon chip
low temperature SiO2 (Low Temperature Oxide, LTO), deposit at temperature 550 DEG C subsequently
amorphous silicon, then opens an elongate trench at the adjacent region of crystallization knot of wanting, and in body structure surface deposit skim about
ni, needs bottom surface and the sidewall of paying special attention to groove in this step.Continue to carry out side crystallization in 25 hours at temperature 550 DEG C, because amorphous silicon crystal turns each face for groove into, to such an extent as to crystallization with the surface of amorphous silicon with per hour
speed eliminate from groove.After Ni and LTO is completely removed, silicon chip 900 DEG C of short annealings 30 minutes to expand silicon particle size.This technology is generally used to make NMOS and pmos fet.In a single die, if crystallite dimension is enough large, then most device all has 1 micron channel lengths and the channel direction characteristic perpendicular to the length direction of groove.But in a single die, due to the unordered existence of crystal boundary, even if channel length is short in 1 micron, long channel device can not be fully formed, and orientation can not parallel with trench length direction completely.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of three dimensional integrated circuits and preparation method thereof, aim to provide one and can make electronic circuit components and parts on bottom makes, also can manufacture three dimensional integrated circuits preparation method and the three-dimensional integrated circuit structure of infinite layers circuit components simultaneously.
The present invention is achieved in that a kind of preparation method of three dimensional integrated circuits device architecture, comprises the following steps:
Steps A, provides bottom;
Step B, forms an amorphous semiconductor layer at described bottom, carries out the crystallization process of metal inducement side to described amorphous semiconductor layer, and makes the first electronic circuit component layer accordingly;
Step C, the i-th electronic circuit component layer forms a passivating oxide layer, and described passivating oxide layer makes the i-th+1 electronic circuit component layer; Wherein, i is natural number and initial value is 1;
Step D, is electrically connected to the corresponding electronic circuit element of the described all electronic circuit component layers formed before by each electronic circuit component in described i-th+1 electronic circuit component layer;
Step e, with the step-length of i be the mode repeated execution of steps B of 1 to step D, until produce the integrated circuit of the target number of plies.
Further, step B specifically comprises:
Step B1, described bottom is formed an amorphous semiconductor layer;
Step B2, the amorphous semiconductor layer described in remove portion, forms some silicon island in precalculated position;
Step B3, performs the crystallization process of metal inducement side to each silicon island, makes each silicon island form independently semiconductor crystal;
Step B4, described semiconductor crystal makes at least one electronic circuit component.
Further, step B2 specifically comprises:
Remove the amorphous semiconductor of predetermined dimension in the precalculated position of described amorphous semiconductor layer, to form some grooves, the part between described groove is silicon island.
Further, step B2 is also included in depositing metal on each described groove and forms the process of some metal tapes, and described metal tape connects described amorphous semiconductor, and described some metal tapes form metal zone;
In step B3, described metal inducement side crystallization processing procedure comprises:
First annealing stage, in first annealing temperature and the first annealing time of setting, by means of the monolateral formation one independently semiconductor crystal of every strip metal band at the determining area of each metal zone;
Second annealing stage, comprises the second annealing temperature and the second annealing time, and described second annealing temperature is higher than described first annealing temperature, and described second annealing time is shorter than described first annealing time.
Further, the length of described metal tape is less than the width of the required semiconductor crystal made.
The present invention also provides a kind of three dimensional integrated circuits device architecture, and described three dimensional integrated circuits device architecture is that the method according to any one of claim 1 to 5 is made.
Compared with prior art, beneficial effect is in the present invention: the present invention can the making electronic circuit components and parts of simple and flexible, and also can manufacture the 3D structure of infinite layers circuit components, no longer prior art can only be fabricated onto two layers simultaneously.Method provided by the present invention does not need to use special manufacturing technology, uses general 2-D structure correlation technique.Because field-effect transistor can be accurately positioned on a crystal grain, we can by preparing the transistor with single crystal characteristics to the accurate control of polysilicon membrane.Therefore, by the present invention, not only can solve the problem of polycrystalline SiTFT poorer performance, also can prepare the circuit components of one deck or more layer in any structure (such as MEMS) existed.
Accompanying drawing explanation
Fig. 1 is the process chart of the preparation method of a kind of three dimensional integrated circuits that the embodiment of the present invention provides.
Fig. 2 is the structural representation of the first technology that the embodiment of the present invention provides.
Fig. 3 is the structural representation of the second technology that the embodiment of the present invention provides.
Fig. 4 is the detailed construction schematic diagram of the second technology that Fig. 3 provides.
Fig. 5 is the performance plot of the field-effect transistor manufactured by the embodiment of the present invention.
Fig. 6 is the Performance comparision table of the field-effect transistor manufactured with prior art of the field-effect transistor that provides of Fig. 5.
Fig. 7 is the use schematic diagram of the electronic circuit component that the embodiment of the present invention manufactures.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As shown in Figure 1, be the process chart of a kind of preparation method of three dimensional integrated circuits.
First, growth or deposit one insulating oxide 3 on silicon chip 1, then on insulating oxide 3, grow the thin amorphous silicon layer of one deck 5, as shown in Fig. 1 (a).In subsequent treatment, amorphous silicon layer 5 can set up silicon (Si) island 11 in the position of predetermined formation electronic circuit component, and it is slightly larger than the area of the field-effect transistor of expection.
Then one deck low temperature oxide layer (LTO) 7 is grown at body structure surface.Remove part LTO, deposit one metal level 9, as shown in Fig. 1 (b).Removing the LTO of ad-hoc location makes metal level 9 contact with amorphous silicon layer 5, can the process of initialization side direction crystallization.The LTO removed is slender type, and each defines a groove (trench).Described groove extends at longitudinal direction, forms specific length, as shown in Fig. 1 (b).As can be seen from the figure metal level 9 is filled with the trench area of LTO, but in practical application, the metal of described metal level 9 only covers lower surface and the sidewall of described groove.
The first annealing stage in the crystallization process of metal inducement side, generally get medium temperature 550 DEG C--625 DEG C, continue for an hour or multiple hours, after carrying out metal inducement side crystallization, remove metal level 9.The amorphous silicon layer 5 of crystallization is exposed and photoetching, forms Si island 11, as shown in Fig. 1 (c).
Then at temperature 700 DEG C-1100 DEG C, carry out the second annealing stage, relative first annealing stage, the lasting time is shorter, at 900 DEG C, only need lasting 30 minutes or 1 hour.In a particular application, the second annealing stage also can carry out before exposing the amorphous silicon layer 5 of crystallization.
Ensuing technological process is similar to the manufacture method of traditional SOI, makes circuit element 2,4, in silicon island 11 as shown in Fig. 1 (d).Circuit element 2,4 Zhong Liangge n+ district is source region and drain region respectively, and p-district is channel region.Channel region covers a thin insulating oxide layer, then depositing polysilicon grid on insulating oxide.In embody rule, if the insulating oxide on silicon island 11 is formed by growth instead of deposit, it possesses better quality by than known generation type.
Further technological process comprises photoetching polysilicon gate and forms one or more grid and growth of passivation oxide layer 13.If the device size manufactured and the crystallite dimension of silicon island 11 comparable, then the performance of device is similar to the MOSFET manufactured on the monosilicon, is better than the performance of the TFT of other manufactures.
Carry out chemico-mechanical polishing CMP (Chemical-Mechanical Polish) below, planarization passivating oxide layer 13 is as shown in Fig. 1 (d).The technique of the electronic circuit component layer that the upper surface that passivating oxide layer is 13 layers is formed corresponds to above-described technique and carries out.Repeat technical process above, then use conventional method to make Metal Contact 15, its structure is as Fig. 1 (e).It has the circuit element 6 of the second layer (in figure B), covering second passivating oxide layer 16 on it.Circuit element 6 Zhong Liangge p+ district is source region and drain region respectively, and n-district is channel region.Channel region covers a thin insulating oxide layer, then depositing polysilicon grid on insulating oxide, polysilicon gate top is connected with Metal Contact 15.
In order to form one or more layers, above-mentioned manufacturing process can be repeated.
In the present embodiment, be do not have circuit element 3 times at insulating oxide, in embody rule process, above-mentioned technique can on a structure as bulk wafer or soi structure make.
Shown in Fig. 2 is the first technology by controlling crystal boundary in amorphous silicon layer 5 used in an embodiment, is the structure chart of Fig. 1 top plan.Groove 17 is parts that low temperature oxide layer (LTO) 7 is removed, and metal level 9 can connect amorphous silicon layer 5 by groove 17.In this specific embodiment, the region of having removed in each groove 17 corresponding diagram 1 (b), Fig. 1 (d) and Fig. 2.
During annealing, each groove 17 both sides respectively forms a monocrystalline 19.The length x1 of each groove 17 is slightly less than the width x2 of monocrystalline 19.Crystal boundary 21 is between groove 17 adjacent between two, and therefore the position of each crystal grain corresponds to the position of groove 17.
Two kinds of different field-effect transistors are described in Fig. 2, comprising: along the A shape device 23 in crystallization direction, comprise source region, drain region 27 and channel region 25; Perpendicular to the B shape device 29 in crystallization direction, comprise source region, drain region 33 and channel region 31.
According to length and the width of the field-effect transistor of required making, whole channel region can be positioned on a monocrystalline by regulating the direction of transistor.
In figure 3, the second technology is by controlling the pattern of the pre-determining silicon island, position of crystal boundary before depositing metal.In the second technology, part amorphous silicon layer 5 remove to expose insulating oxide 3, but in silicon island 35 except.Then the metal of deposit random length in groove 37.In the present embodiment, groove 37 represents in 1 (b), the region of the groove removed in Fig. 1 (d) and Fig. 3.Silicon island 35 is wide is y, consistent with the width of the crystallization direction achieving crystallization perpendicular to MILC.
As shown in Figure 3, for A type device 33, the A type device 33 formed on silicon island 35 is fully formed in a crystal, raceway groove 39 is parallel to crystallization direction.Because A type device 33 is fully formed in a crystal, therefore channel width need be less than silicon island width y.In actual applications, the transistor having wider raceway groove be obtained, the structure of Fig. 4 can be adopted.Have many silicon island in Fig. 4, each silicon island all has source region, channel region 41 and drain region, and (described metal tape for described groove is filled with metal and be formed into) is carried out being connected by the metal tape 43,45 of respective electrical conductance in the source region of different crystal grain and drain region.Same, grid, on channel region, are connected by metal tape 47 between grid.Wc is the width of each channel region 41.
Below by way of idiographic flow, the preparation method to a kind of three dimensional integrated circuits provided by the invention sets forth, and the ground floor of circuit element is manufactured on si sheet, and concrete technological process is as follows:
Initialization SIMOX SOI sheet (
), then use oxidation reaction and HF oxidation removal Si sheet thickness extremely
; Etching Si sheet, until oxygen buried layer, activates active area.Then standard SOI CMOS technology is carried out as threshold value Channeling implantation, long grid oxygen, polygate electrodes, source/drain injection, doping, short annealing.So far device ground floor completes.Deposit below
lTO, recycling chemico-mechanical polishing cmp planarizationization surface and time etching, finally obtaining interlevel oxidation layer thickness is
The device second layer is based upon the top of oxide layer, first deposit
amorphous silicon, carries out recrystallization with MILC, window deposition Determination of Trace Nickel suitable on amorphous silicon film.Side direction annealing is carried out to formed amorphous silicon film, and carry out 60 hours crystallizations under N2 atmosphere He at 560 DEG C of temperature.After nickel is removed, amorphous silicon film, temperature 900 DEG C, carries out 1 hour recrystallization.The crystallite dimension of LPSOI (large-grain polysilicon-on-insulator film) layer is about greater than 80um.The standard SOI CMOS technology being similar to ground floor is used to manufacture the second layer of device.Finally, complete Metal Contact and interconnection process, so far, the 3-D structure of integrated circuit completes.In order to simplification of flowsheet, in this flow process, use one layer metallization.
The channel length of bottom MOSFETs and top layer MOSFETs is 0.54um and 0.71um respectively, this two-layer transistor characteristic very similar.The top layer device be based upon on LPSOI (large-grain polysilicon-on-insulator film) does not have large leakage current and the little subthreshold value factor, this illustrates in testing, do not run into any crystal boundary, then device should be based upon on larger monocrystalline silicon.The performance of the field-effect transistor manufactured on LPSOI layer is described how by comparing in the mobility of different layers NMOSFETs and PMOSFETs.Top layer LPSOI layer all has similar carrier mobility with bottom soi layer.
Fig. 5 (a) and 5 (b) are the Id-Vd characteristic curve of bottom and top layer device respectively.All field-effect transistors all have SOI characteristic.They are all voltage devices, can realize low-voltage and low-power circuits.The combination of different top layers and bottom device can form 3-D circuit.
The table that Fig. 6 provides is the TFT of MOSFETs, MILC manufacture that embodiment manufactures, the Performance comparision without high temperature TFT tri-kinds of devices of MILC manufacture.
The thickness of tox:MOSFET oxide layer in table; Tox gate oxide thickness; Idsat drain saturation current; W field-effect transistor width; L field effect transistor length of tube; Grid voltage added by VG.
Fig. 7 is the practical application that we invent, and this invention is through being commonly used to manufacture circuit element in MEMS (micro-electronic mechanical system) system.MEMS system is an electrochemistry microcellulor: light propagates into photodiode 53 by chamber 51.Photodiode 53 comprises circuit element, and the polysilicon LPSOI (large-grain polysilicon-on-insulator film) 55 li in a large crystal grain dielectric substrate.MEMS also comprises the field-effect transistor 57 using the present invention with LPSOI film.MEMS and magnet 59 interact.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a preparation method for three dimensional integrated circuits device architecture, is characterized in that, comprises the following steps:
Steps A, provides bottom;
Step B, forms an amorphous semiconductor layer at described bottom, carries out the crystallization process of metal inducement side to described amorphous semiconductor layer, and makes the first electronic circuit component layer accordingly;
Step C, the i-th electronic circuit component layer forms a passivating oxide layer, and described passivating oxide layer makes the i-th+1 electronic circuit component layer; Wherein, i is natural number and initial value is 1;
Step D, is electrically connected to the corresponding electronic circuit element of the described all electronic circuit component layers formed before by each electronic circuit component in described i-th+1 electronic circuit component layer;
Step e, with the step-length of i be the mode repeated execution of steps B of 1 to step D, until produce the integrated circuit of the target number of plies.
2. preparation method as claimed in claim 1, it is characterized in that, step B specifically comprises:
Step B1, described bottom is formed an amorphous semiconductor layer;
Step B2, the amorphous semiconductor layer described in remove portion, forms some silicon island in precalculated position;
Step B3, performs the crystallization process of metal inducement side to each silicon island, makes each silicon island form independently semiconductor crystal;
Step B4, described semiconductor crystal makes at least one electronic circuit component.
3. preparation method as claimed in claim 2, it is characterized in that, step B2 specifically comprises:
Remove the amorphous semiconductor of predetermined dimension in the precalculated position of described amorphous semiconductor layer, to form some grooves, the part between described groove is silicon island.
4. preparation method as claimed in claim 3, it is characterized in that, step B2 is also included in depositing metal on each described groove and forms the process of some metal tapes, and described metal tape connects described amorphous semiconductor, and described some metal tapes form metal zone;
In step B3, described metal inducement side crystallization processing procedure comprises:
First annealing stage, in first annealing temperature and the first annealing time of setting, by means of the monolateral formation one independently semiconductor crystal of every strip metal band at the determining area of each metal zone;
Second annealing stage, comprises the second annealing temperature and the second annealing time, and described second annealing temperature is higher than described first annealing temperature, and described second annealing time is shorter than described first annealing time.
5. preparation method as claimed in claim 4, is characterized in that, the length of described metal tape is less than the width of the required semiconductor crystal made.
6. a three dimensional integrated circuits device architecture, is characterized in that, described three dimensional integrated circuits device architecture is that the method according to any one of claim 1 to 5 is made.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316770A (en) * | 2001-03-15 | 2001-10-10 | 东南大学 | Process for preparing polysilicon film |
| US20030068871A1 (en) * | 2001-09-28 | 2003-04-10 | Man Sun John Chan | Three dimensional integrated circuits |
| CN1479355A (en) * | 2002-08-26 | 2004-03-03 | 中国科学院微电子中心 | Fluted plane bigrid structure MOS device and its manufacturing method |
| CN101097926A (en) * | 2006-06-26 | 2008-01-02 | 株式会社液晶先端技术开发中心 | Thin-film semiconductor device, thin-film transistor, and method of fabricating thin-film transistor |
| CN101834138A (en) * | 2010-02-09 | 2010-09-15 | 广东中显科技有限公司 | Method for preparing transistor device of crystallized thin film |
-
2015
- 2015-05-06 CN CN201510226919.7A patent/CN104952795A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316770A (en) * | 2001-03-15 | 2001-10-10 | 东南大学 | Process for preparing polysilicon film |
| US20030068871A1 (en) * | 2001-09-28 | 2003-04-10 | Man Sun John Chan | Three dimensional integrated circuits |
| CN1479355A (en) * | 2002-08-26 | 2004-03-03 | 中国科学院微电子中心 | Fluted plane bigrid structure MOS device and its manufacturing method |
| CN101097926A (en) * | 2006-06-26 | 2008-01-02 | 株式会社液晶先端技术开发中心 | Thin-film semiconductor device, thin-film transistor, and method of fabricating thin-film transistor |
| CN101834138A (en) * | 2010-02-09 | 2010-09-15 | 广东中显科技有限公司 | Method for preparing transistor device of crystallized thin film |
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