CN104952713A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN104952713A CN104952713A CN201410111507.4A CN201410111507A CN104952713A CN 104952713 A CN104952713 A CN 104952713A CN 201410111507 A CN201410111507 A CN 201410111507A CN 104952713 A CN104952713 A CN 104952713A
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- layer
- etching stop
- metal
- stop layer
- gate
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a manufacturing method for a semiconductor device. The manufacturing method comprises the following steps: forming a gate trench in a substrate, and forming a high-k gate dielectric layer in the gate trench; forming an etching stop layer on the high-k gate dielectric layer; forming an oxygen gettering metal layer on the etching stop layer, and carrying out thermal annealing; taking the etching stop layer as a stop layer, and removing the oxygen gettering metal layer; forming a metal gate electrode on the etching stop layer. In the manufacturing method provided by the invention, after the oxygen gettering metal layer is formed and the thermal annealing is carried out to reduce the thickness of a small interface layer, the oxygen gettering metal layer is removed to reduce the thickness of the whole gate stack.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of manufacture method of semiconductor device.
Background technology
Integrated circuit technique is by Moore's Law sustainable development, and characteristic size constantly reduces, and integrated level improves constantly, and function is more and more stronger.At present, the characteristic size of mos field effect transistor (MOSFET) has entered sub-50nm.With the continuous reduction of device feature size, if the grid still adopting traditional gate silicon oxide medium/polysilicon to be formed are stacking, gate medium electric leakage can exponentially rule sharply increase, and poly-Si depletion effect is more and more serious, and polysilicon resistance also can increase thereupon.
In order to overcome above difficulty, industrial quarters starts to adopt high-k gate dielectric and metal gate electrode to form novel grid stacked structure (high k/ metal-gate structures) and replaces traditional grid stacking.In high k/ metal gate process, in deposition or high-temperature thermal annealing technique, inevitably can form the boundary layer of silicon dioxide between substrate and high-k gate dielectric layer, this can increase the equivalent oxide thickness of device, affects the performance of device.
In order to reduce the thickness of boundary layer, at present, a kind of feasible method increases oxygen gettering metal layer in the gate, reduces the thickness of this boundary layer.But the gross thickness T of high k/ metal gate can be increased like this
total, along with the continuous reduction of the long Lg of rear grid technique MOS device grid, the gross thickness T of high k/ metal gate
totalneed to reduce: T
total≤ L
g/ 2, the reduction of the gross thickness of high k/ metal gate cannot be met when the long Lg of grid constantly reduces.
Summary of the invention
Object of the present invention is intended at least solve above-mentioned technological deficiency, provides a kind of manufacture method of semiconductor device, while the thickness reducing boundary layer, reduces the thickness that grid are stacking.
The invention provides a kind of manufacture method of semiconductor device, comprising:
Substrate forms gate groove;
High-k gate dielectric layer is formed in gate groove;
High-k gate dielectric layer forms etching stop layer;
Etching stop layer is formed oxygen gettering metal layer, and carries out thermal annealing;
Take etching stop layer as stop-layer, remove oxygen gettering metal layer;
Etching stop layer forms metal gates.
Optionally, step etching stop layer forming metal gates is specially:
Deposit is used for the first metal layer of first kind device;
Take etching stop layer as stop-layer, etching first metal layer, only forms the first metal layer on first kind device;
Deposit is used for the second metal level of Second Type device;
Fill gate groove, and carry out planarization, to form metal gate.
Optionally, described etching stop layer is Ta metal alkyl materials.
Optionally, described etching stop layer is TaN, TaCN or TaSiN.
Optionally, the material of described oxygen gettering metal layer is Ti, Al or Hf.
Optionally, APM corrosive liquid is adopted to remove this oxygen gettering metal layer.
The manufacture method of the semiconductor device that the embodiment of the present invention provides, formed oxygen gettering metal layer thermal annealing with the thickness reducing boundary layer after, by the removal of this oxygen gettering metal layer, to reduce the stacking thickness of whole grid.Further, in double grid technique, etching stop layer when this etching stop layer is the first metal layer forming first kind device, Simplified flowsheet step, and effectively reduce the stacking thickness of grid, improve the accessible site degree of device.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1 shows the flow chart of the manufacture method of the semiconductor device according to the embodiment of the present invention;
Fig. 2-7 shows the schematic cross-section forming each manufacture process of semiconductor device according to the manufacture method of the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
As the description of background technology, utilize oxygen gettering metal layer to be conducive to the thickness of boundary layer to reduce, but the thickness of whole gate stack can be increased, after the long constantly reduction of grid, the requirement of the stacking whole thickness of device grids cannot be met, grid technique especially.For this reason, the present invention proposes a kind of manufacture method of semiconductor device, as shown in Figure 1, comprising:
Substrate forms gate groove;
High-k gate dielectric layer is formed in gate groove;
High-k gate dielectric layer forms etching stop layer;
Etching stop layer is formed oxygen gettering metal layer, and carries out thermal annealing;
Take etching stop layer as stop-layer, remove oxygen gettering metal layer;
Etching stop layer forms metal gates.
In the present invention, oxygen gettering metal layer thermal annealing is formed with after the thickness reducing boundary layer, by the removal of this oxygen gettering metal layer, to reduce the stacking thickness of whole grid.
After method of the present invention application in grid technique, below with reference to the schematic cross-section of flow chart and manufacture process, to adopting manufacture method of the present invention to carry out in rear grid technique, embodiment prepared by device is described in detail.
First, pseudo-gate device (scheming not shown) is formed.
Particularly, first provide substrate 100, shown in figure 2.
In an embodiment of the present invention, described Semiconductor substrate can be Si substrate, Ge substrate, SiGe substrate, SOI(silicon-on-insulator, Silicon On Insulator) or GOI(germanium on insulator, Germanium On Insulator) etc.In other embodiments, described Semiconductor substrate can also be the substrate comprising other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., it can also be laminated construction, such as Si/SiGe etc., all right other epitaxial structures, such as SGOI(silicon germanium on insulator) etc.Described Semiconductor substrate can be formed with isolated area 102, and described isolated area can comprise silicon dioxide or other can separate the material of the active area of device.In the present embodiment, described substrate is silicon substrate.
Then, boundary layer (scheming not shown) is formed.
In the present embodiment, the hot mode grown can form boundary layer over the substrate, in embodiments of the present invention, boundary layer is SiO
2.
Then, the source-drain area (108,110) in the side wall 116 on pseudo-grid (scheming not shown), pseudo-grid sidewall, pseudo-grid both sides substrate, the metal silicide layer 112 on source-drain area and interlayer dielectric layer 114 is formed.
Described dummy grid can be amorphous silicon, polysilicon or silica etc., in the present embodiment, can be amorphous silicon.
Described side wall can have single or multiple lift structure, can by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low k dielectric material and combination thereof, and/or other suitable materials are formed.In the present embodiment, be three-decker.
Described source-drain area (108,110) can by according to the transistor arrangement expected, implanted with p-type or N-shaped alloy or impurity are formed in described substrate.In the present embodiment, first area 104 for the formation of the device of the first kind, as nMOS device, second area 106 for the formation of the device of Second Type, as pMOS device.
Can by suitable deposition process deposit dielectric material, such as unadulterated silica (SiO
2), doping silica (as Pyrex, boron-phosphorosilicate glass etc.), silicon nitride (Si
3n
4) or other low k dielectric materials, then carry out planarization, such as CMP(chemico-mechanical polishing), form described interlayer dielectric layer (ILD).
Then, pseudo-grid are removed stacking, to form gate groove 118, as shown in Figure 2.
Wet etching and/or dry ecthing removing can be used.In the present embodiment, Tetramethylammonium hydroxide (TMAH) can be passed through and remove amorphous silicon, like this, form gate groove 118 in the region in original pseudo-grid region, and further boundary layer is removed.
Then, again boundary layer 120 is formed, shown in figure 3.
In the present embodiment, boundary layer 120 is silica, its formation method can be the conventional methods such as PECVD, HDPCVD, MBE, ALD, it can also be chemical oxidation method, such as in the deionized water containing finite concentration ozone, soak 20s, make the boundary layer 120 of the surperficial oxidized formation silica of the substrate 100 of silicon material.This thin layer boundary layer is for reducing the interface state density between substrate 100 and the gate dielectric layer of high-g value formed afterwards.
Then, in gate groove, high-k gate dielectric layer 122 is formed, shown in figure 3.
Described high-k gate dielectric layer is the dielectric material relative to silica with high dielectric constant, include but not limited to nitride, metal oxide (being mainly subgroup and lanthanide element oxide) and Perovskite Phase oxide, nitride is SiN such as, metal oxide and Perovskite Phase oxide such as Al
2o
3, Ta
2o
5, TiO
2, ZnO, ZrO
2, HfO
2, CeO
2, Y
2o
3, La
2o
3deng, Perovskite Phase oxide such as PbZrxTi1-xO
3(PZT), BaxSr1-xTiO
3(BST) etc.Formation method can be the conventional methods such as CVD, PVD, ALD.Subsequently, adopt deposition after annealing (PDA), such as anneal 15s at 450 DEG C, to improve the quality of high-k gate dielectric layer.
Then, high-k gate dielectric layer forms etching stop layer 126, shown in figure 3.
In the present embodiment, this etching stop layer is TaN, for the etching stop layer that follow-up oxygen gettering metal layer is removed, meanwhile, is also in double grid technique, forms the etching stop layer during metal gates of a types of devices.In other embodiments, this etching stop layer can also be other Ta metal alkyl materials, such as TaCN, TaSiN etc.
Then, etching stop layer forms oxygen gettering metal layer 128, as shown in Figure 3, and carry out thermal annealing.This oxygen gettering metal layer can reduce the thickness of boundary layer 120, thus reduces the EOT of device.In the present embodiment, the material of described oxygen gettering metal layer is Ti, Al or Hf.Oxygen gettering metal layer is easy to and combination with oxygen, avoids too much oxygen and substrate interface to react the increase causing EOT.The temperature of thermal annealing can be 350 DEG C, and the time can be 10min.
Then, take etching stop layer as stop-layer, remove oxygen gettering metal layer 128, as shown in Figure 4.
Wet etching and/or dry ecthing can be used to remove this oxygen gettering metal layer.In the present embodiment, APM corrosive liquid (NHOH:H can be adopted
2o
2: H
2o) carry out wet etching and remove this oxygen gettering metal layer.
Then, this etching stop layer forms metal gates, with reference to shown in 5-7.
Described metal gates can be one or more layers structure, and can comprise metal material or polysilicon or their combination, metal material is Ti, TiAl such as
x, TiN, TaN
x, HfN, TiC
x, TaC
xetc..
In the present embodiment, for double grid technique forms metal gates, namely nMOS and pMOS device area forms dissimilar metal gates respectively.In the present embodiment, particularly, shown in figure 6, first, deposit the first metal layer, such as, for pMOS, can select TiN, Ru etc.; Then, with etching stop layer 126 for stop-layer, etch described the first metal layer, only on the region 106 of pMOS device, form the first metal layer 132; Then, continue deposit second metal level 130, such as, for nMOS, can Al, AlTi etc. be selected; Then, continue deposit the 3rd metal level 134, such as, can select TiN, TaN; Then, filling metal material 136 is carried out, such as W.Finally, carry out adopting the method for CMP to carry out planarization, until expose interlayer dielectric layer 114, thus form replacement gate in gate groove, as shown in Figure 7.
Then, as required, the subsequent machining technology of device is completed.Such as source and drain contact and metal interconnecting layer (scheming not shown) etc.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (6)
1. a manufacture method for semiconductor device, is characterized in that, comprises step:
Substrate forms gate groove;
High-k gate dielectric layer is formed in gate groove;
High-k gate dielectric layer forms etching stop layer;
Etching stop layer is formed oxygen gettering metal layer, and carries out thermal annealing;
Take etching stop layer as stop-layer, remove oxygen gettering metal layer;
Etching stop layer forms metal gates.
2. manufacture method according to claim 1, is characterized in that, the step that etching stop layer is formed metal gates is specially:
Deposit is used for the first metal layer of first kind device;
Take etching stop layer as stop-layer, etching first metal layer, only forms the first metal layer on first kind device;
Deposit is used for the second metal level of Second Type device;
Fill gate groove, and carry out planarization, to form metal gate.
3. method according to claim 1 and 2, is characterized in that, described etching stop layer is Ta metal alkyl materials.
4. method according to claim 3, is characterized in that, described etching stop layer is TaN
x, TaCN or TaSiN.
5. method according to claim 1, is characterized in that, the material of described oxygen gettering metal layer is Ti, Al or Hf.
6. method according to claim 5, is characterized in that, adopts APM corrosive liquid to remove this oxygen gettering metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410111507.4A CN104952713A (en) | 2014-03-24 | 2014-03-24 | Manufacturing method for semiconductor device |
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|---|---|---|---|
| CN201410111507.4A CN104952713A (en) | 2014-03-24 | 2014-03-24 | Manufacturing method for semiconductor device |
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| CN104952713A true CN104952713A (en) | 2015-09-30 |
Family
ID=54167284
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| CN201410111507.4A Pending CN104952713A (en) | 2014-03-24 | 2014-03-24 | Manufacturing method for semiconductor device |
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Citations (7)
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| CN102194692A (en) * | 2010-03-04 | 2011-09-21 | 中国科学院微电子研究所 | Production method for semiconductor device |
| CN102237398A (en) * | 2010-04-20 | 2011-11-09 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| US20120129310A1 (en) * | 2010-11-22 | 2012-05-24 | Weonhong Kim | Methods of fabricating a semiconductor device having a high-k gate dielectric layer and semiconductor devices fabricated thereby |
| US20130026579A1 (en) * | 2011-07-26 | 2013-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Techniques Providing High-K Dielectric Metal Gate CMOS |
| CN103545190A (en) * | 2012-07-16 | 2014-01-29 | 中国科学院微电子研究所 | Gate structure forming method, semiconductor device forming method and semiconductor device |
| CN103545189A (en) * | 2012-07-16 | 2014-01-29 | 中国科学院微电子研究所 | Gate structure, semiconductor device and forming method of both |
| CN103545191A (en) * | 2012-07-16 | 2014-01-29 | 中国科学院微电子研究所 | Gate structure forming method, semiconductor device forming method and semiconductor device |
-
2014
- 2014-03-24 CN CN201410111507.4A patent/CN104952713A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194692A (en) * | 2010-03-04 | 2011-09-21 | 中国科学院微电子研究所 | Production method for semiconductor device |
| CN102237398A (en) * | 2010-04-20 | 2011-11-09 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| US20120129310A1 (en) * | 2010-11-22 | 2012-05-24 | Weonhong Kim | Methods of fabricating a semiconductor device having a high-k gate dielectric layer and semiconductor devices fabricated thereby |
| US20130026579A1 (en) * | 2011-07-26 | 2013-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Techniques Providing High-K Dielectric Metal Gate CMOS |
| CN103545190A (en) * | 2012-07-16 | 2014-01-29 | 中国科学院微电子研究所 | Gate structure forming method, semiconductor device forming method and semiconductor device |
| CN103545189A (en) * | 2012-07-16 | 2014-01-29 | 中国科学院微电子研究所 | Gate structure, semiconductor device and forming method of both |
| CN103545191A (en) * | 2012-07-16 | 2014-01-29 | 中国科学院微电子研究所 | Gate structure forming method, semiconductor device forming method and semiconductor device |
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Application publication date: 20150930 |