CN104935405B - Method suitable for DS-1 frame receiving side analysis - Google Patents
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- CN104935405B CN104935405B CN201510227749.4A CN201510227749A CN104935405B CN 104935405 B CN104935405 B CN 104935405B CN 201510227749 A CN201510227749 A CN 201510227749A CN 104935405 B CN104935405 B CN 104935405B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
- H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
Abstract
A parsing method applied to a receiving side of a DS-1 frame, the method comprising the steps of: and receiving data from the DS-1PHY, and transmitting the obtained data to a programmable logic array (FPGA) for correlation processing to obtain a frame header position of the DS-1 frame. And resolving each time slot of the obtained DS-1 frame according to a frame format specified by an ITU-T G.704 protocol.
Description
Technical field
The invention belongs to the communications fields PDH, and in particular to DS-1 frame receiving side analytic methods, and realize said function
Chip, UE, instrument etc..
Background technology
DS-1 Transmission systems are early stage PDH communication system, it is answered 24 railway digital voice channels by the principle of time-division multiplex
It closes on the IA High Speed Channel of a 1.544Mb/s.By ITU-T, G.704 standard defines compound frame format.It includes 24 DS0
(64kbps) time slot is numbered from 1 to 24, and each time slot 8bit is 192bit total.The basic frame of DS-1 frames further includes a F bit
Position (framing bit) indicates the beginning of current frame end and next frame as frame lock bit.Therefore a complete DS-1
Frame includes 1 frame lock bit and 24 time slots totally 193 bit, and the code stream is serial code stream, previous frame and the close phase of next frame
Even no gap, as shown in Figure 4.The parsing of DS-1 frames parses frame synchronization sequence by DS multi-frames, to orient frame lock bit.
G.704 standard defines two kinds of DS-1 frame multiple connection modes, respectively SF frames and ESF frames to ITU-T.
SF frame formats such as table one：
Table one
ESF frame formats such as table two：
Table two
DS-1 receiving side analytic methods are i.e. in one group of serial sequence, and according to ITU-T, G.704 defined multi-frame format carries
F bit sequences are taken out, to position DS-1 frames.In short, if can extract 24 F bits therein meets ITU-T
G.704 defined multi-frame sequence, then it is assumed that DS-1 frames can be positioned.G.704 according to ITU-T, 24 F bit sequences of SF frames
For：24 bit sequences of 1000_1101_1100_1000_1101_1100, ESF frame are：xxx0_xxx0_xxx1_xxx0_
Xxx1_xxx1, wherein x represent arbitrary value.
It is used as frame alignment since DS-1 frames only rely on this 1 bit, existing scheme is mostly based on traversal search at present, takes
It is longer.
Invention content
Present invention aim to address longer due to solving the parsing time that frame method is brought using tradition in DS-1 receivers
The problem of, the present invention provides a kind of methods of fast resolving DS-1 frames.
It is provided by the invention to be suitable for DS-1 frame receiving side fast resolving methods, it comprises the steps of：
The 1st, the electric signal in line side is converted to the serial digital sequence of logic side after line side PHY processing, and
It is transmitted to programmable logic array (FPGA).Obtained Serial No. is stored to RAM by programmable logic array (FPGA)
In, in order to achieve the purpose that quick-searching DS-1 frames, following processing is done to RAM：
1.1st, it is 13 bits that setting RAM, which is address bus bit wide,.
1.2nd, base address of high 5 bit as each basic frame storage provides, DS-1 multi-frames are most according to ITU-T standard
A height of 24 frame, therefore base address of 5 bits as basic frame is chosen, meet：
25>24。
1.3rd, storage address of low 8 bit as each bit of basic frame provides, the basic frames of DS-1 according to ITU-T standard
For 193 bits, meet：
28>193。
Mode of operation is as follows, a counter is arranged, low 8 bit each clock cycle of address, counter counts were extremely from adding
It is zeroed when 193, i.e., when one complete DS-1 frame is zeroed.And high 5 bit adds 1 simultaneously, and so on.By such storage side
Formula has obtained a storage array for being similar to matrix.Each row of matrix are a basic frame of DS-1, and matrix is each
The combination of capable then bit for different DS-1 frame same positions.By the control to address ram, read according to the row of matrix
RAM.Mode of operation is as follows：One counter is set, when reading RAM, from adding, least-significant byte remains unchanged high 5 of address, when
When counter counts are to 24, then it represents that have read a line.If reading the next line of matrix, the least-significant byte for controlling address ram adds 1
.
2nd, by carrying out parallel traversal search to RAM, obtain the X of DS-1 frames, Y coordinate；
Parallel traversal search method is that the RAM of 193 rows obtained by the 1st step is divided into 5 sections, is drawn by 5 search
The characteristic sequence for holding up the compound DS-1 frames of parallel search to achieve the purpose that shorten search time, and is finally found multiple in a matrix
The sequence of standardization.
Sequence search circuit is built by FPGA, searching method is as follows：
2.1st, RAM is read by row, if the sequences match that 24 obtained bit values are defined with ITU-T standard, retains
Current location；If mismatched with the sequence that ITU-T standard defines, shifting function is carried out to 24 bit values of reading.If
Still without successful match after shifting 24 times, then next line data are read, repeatedly, until the whole 193 row data of traversal.
2.2nd, for acceleration detection process, using parallel search mode.According to above-mentioned testing principle, needed under limiting case
It matches 193x24=4632 times, for successful match in a short time, 193 row data is divided into 5 regions of search, it is each
Section parallel search, if search successful match, retains current line position and set (Y-axis position), column position (X-axis position) is right
Subsequent DS-1 multi-frames carry out duplicate acknowledgment operation, with the sequence phase for preventing random bearer service data from by chance being defined with standard
Together.If follow-up multi-frame is in same position still successful match, then it is assumed that DS-1 multi-frames detect successfully.The number of duplicate acknowledgment can
Different settings is carried out according to different load patterns, is set and column position until finding an accurate line position.
3rd, using obtained X, Y coordinate extracts DS-1 frame sequences.Since the transmission form of DS-1 frames is continuous and first
What tail connected, therefore the starting point of write-in RAM randomly selects in step 1, system is not aware that the starting randomly selected
The offset of point and DS-1 frame multi-frame heads.So the purpose of this step is i.e. using the X obtained in the 2nd step, Y-coordinate value is written
The offset of the starting point and DS-1 frame multi-frame heads of RAM.Specific operation process is：
3.1 are arranged a counter in FPGA, and counter clear when first time RAM being written then often is write
Enter the 1 bit counter and adds 1, it is so past until 193 bits, that is, a counter O reset when DS-1 frame frame length is written
It is multiple.The purpose of the counter is the relative position for the starting point that record randomly selects.
3.2 have obtained the coordinate value of matrix X, Y in step 2.By the definition before us, the line number of X representing matrixes should
Line number represents offset of the starting point of the starting point and multi-frame that randomly select in a DS-1 frame at a distance from the first row, should
Value is less than 193；The columns of Y representing matrixes, the columns represent rising for the starting point and multi-frame randomly selected at a distance from first row
The number of the DS-1 frames of initial point apart, the value are less than 24；As from the foregoing：The initial position distance write-in RAM's of DS-1 multi-frames rises
The position D of initial point is：
D=Y × 193+X.
The advantages of the present invention：
Data are stored in RAM by the present invention in programmable logic array (FPGA) by matrix form storage mode, using simultaneously
Row searching method accelerates DS-1 frame detection process.
Description of the drawings：
Fig. 1 is DS-1 frame detection system block schematic illustrations；
Fig. 2 is the signal flow graph of DS-1 frames detection；
Fig. 3 is that RAM matrix forms store schematic diagram；
Fig. 4 is DS-1 frame code stream schematic diagrames；
Fig. 5 is search routine schematic diagram；
Fig. 6 is to demarcate DS-1 multi-frame starting point schematic diagrames by matrix coordinate point；
Fig. 7 writes RAM emulation schematic diagrames；
Fig. 8 reads RAM and emulates schematic diagram；
Fig. 9 displacement matching emulation schematic diagrames；
Figure 10 coordinates extract frame head and emulate schematic diagram.
Specific implementation mode
Below in conjunction with the accompanying drawings and example, detailed description of the present invention technical solution.All the elements of the present invention have existed
It is realized in FPGA, the XC6SLX45 of the Spartan6 series of FPGA models Xilinx.In order to realize this in limited resource
All details of invention have carried out simplification appropriate on the algorithm of the present invention under the premise of not influencing performance.
1st, DS-1 frame code streams, stream rate 1.544Mhz are obtained by PHY.Use is incited somebody to action with road clock inside FPGA
To code stream stored into RAM according to matrix form storage method, the comprehensive resources and performance the considerations of under, this programme uses width
It is 1, the block RAM that depth is 8192 is as storage medium.Using this line clock, that is, 1.544Mhz clocks clock is write as RAM's.
One DS-1 multi-frame is made of 24 DS-1 frames, and each DS-1 frames are made of 193bit, therefore two countings are arranged in FPGA
Device, counter 1 calculate the number of each bit in DS-1 single frames, and counter 2 calculates the number of DS-1 frames.Counter 1 is being counted extremely
It is zeroed after 193, expression has been filled with a DS-1 frame, unison counter 2 plus 1, repeatedly until being filled with 24 DS-1 frames.
The simulation waveform of FPGA is shown in Fig. 7, and it is line clock to write clock, and when writing first frame, a write address high position is 0, and low level adds 1, is writing
When the second frame, high 5 plus 1, low level zero is again from adding, and address is that 16 systems indicate in figure.It may finally obtain as shown in Figure 3
Storage array.The matrix column determines by the least-significant byte of address ram, the row of the matrix by address ram high 5 determinations.It lifts
, A1 in figure, 1 is first row the first row, and address is 13 ' b0_0000_0000_0000 (FPGA is started counting up from 0), and A2,1 is
Second row first row, address are that 13 ' b0_0000_0000_0001, A3,2 are the third line secondary series, and address is 13 ' b0_0010_
0000_0001, and so on.
During write operation, the position of first point of write-in in entire DS-1 multi-frames be it is random, i.e., we
Which frame of this in multi-frame is not known, does not know the point is which bit of 193 bits in DS-1 frames yet.Although this point
Position in frame is random, but the position by the point is needed to record in FPGA.Method is one counter of setting,
Using the point as starting point, counter 0, whenever come in the data counter from plus 1, when filling it up with a DS-1 multi-frame, i.e.,
The counter clear is done from adding, and so on again after 193x24 bit.With this counter coordinate the most, the purpose is to record
The position of the point of first write-in RAM, as the reference coordinate for calculating frame head.Subsequent operation will be explained how to look for from sequence
To the start position of DS-1 multi-frames, the coordinate that subsequent operation obtains is the relative displacement of this coordinate.
Have in this programme FPGA in addition clock is as system clock all the way, clock frequency 60Mhz, this programme is with this clock
Reading clock as RAM.The data in RAM are read by row according to matrix form storage method, and are sent to matching search circuit.It reads
The process taken is as follows, and one counter of setting is reset, table since a line of matrix has 24 after the counter counts to 24
Show a line for having read matrix.It has been noted that the matrix column is determined by the least-significant byte of address ram in previous step, the matrix
High 5 determinations gone by address ram.Therefore address control method is to keep the least-significant byte of address constant, i.e., row remain unchanged, high
5 reset from after add operation, meter to 24, and expression has read 24 bits of a line.If reading next line, address
Least-significant byte adds 1.To read the emulation schematic diagram of the first row in Fig. 8, wherein it is system clock to read clock, address least-significant byte is read not
Become, high 5 add certainly, and address is that 16 systems indicate in figure.
What a line 24bit the 2nd, read in previous step was indicated is the bit of the same position of 24 DS-1 frames.Institute
Meaning same position refers to the position offset relative to frame lock bit (F bits).Therefore 24 bits and ITU- that can will be obtained
The DS-1 sequence heads that TG.704 is defined compare.Due to not can determine which DS-1 frame be multi-frame in first frame, than
It needs to carry out shifting function during relatively.Identifying code is：
assign a[23:0]={ b [22:0],b[23]}；
Wherein b is the sequence before displacement, and a is the sequence after displacement.What if the sequence read from RAM was defined with standard
Sequence simultaneously mismatches, then needs to carry out shifting function, be compared again after displacement.If still can not be with standard after shifting 24 times
The sequences match of definition then illustrates in this line and does not include DS-1 frame heads, the next line for reading RAM is needed to be compared.
If in multi-shift, matching sequence repeatedly is obtained after line feed operation, then the line number currently read is the Y of matrix
Value, the number of displacement are the X values of matrix, and the coordinate of the matching sequence is:(X,Y).In fig.9, S_shift_line_data
The data as read from RAM, the data each clock cycle carry out a shifting function, if obtained sequence with
G.704, the sequence that ITU-T is defined is identical, then by correlating markings position 1.In figure, when
S_shift_line_data==24 ' b000110111001_000110111001
When, S_head_flag_sf sets 1, shows to detect SF frame sequence heads.The coordinate of current location is obtained simultaneously,
S_sync_pos_x, S_sync_pos_y show the X-coordinate and Y coordinate of current location respectively, and the coordinate of X is the seat of 90, Y here
It is designated as 1.
There is still a need for carry out duplicate acknowledgment operation after obtaining the DS-1 sequence heads that G.704 ITU-T defines.Because of DS-1 frames
The business code flow of carrying is random, and the case where being likely encountered is the sequence that the sequence of random code stream composition is by chance defined with standard
It arranges identical, can then lead to erroneous judgement in this way.Therefore need after matching record matching coordinate, will storage RAM refresh after same
Position carries out repeated matching.If successful match is remained to after being repeated several times, it may be considered that finding DS-1 multi-frame heads.It repeats
Matched number can carry out different settings with the random degree of reference code shape.Whole search routine figure is as shown in Figure 5.Letter speech
RAM is written in column using matrix form storage mode in it, and RAM is read by row, often reads and once carries out matching comparison, if matching
It is unsuccessful, shifting function is carried out, then carries out matching comparison again.If finding still to be unable to successful match after shifting 24 times,
The next line data in RAM are then read, repeatedly.If successful match, current (X, Y) coordinate value is recorded, is repeated
Confirmation operation.
Parallel search circuit is more, and the speed of search is faster, but the resource occupied is also more, and this programme comprehensive resources are examined
Consider and uses five groups of matching search circuit parallel searches.The 0th~39 of five groups of matching search circuit difference searching matrix formula storage RAM
Row, 40~79 rows, 80~119 rows, 120~159 rows, 160~193 rows.If searching out the DS-1 sequences that G.704 ITU-T defines
Row head then carries out duplicate acknowledgment operation.If it is confirmed that success, then preserve current X, Y-coordinate value is simultaneously stopped other matching search
Circuit works.After five groups of parallel search circuits, 40 row data are at most searched for per group searching circuit, matching can be accelerated to search for
Process, be completed in a short time matching.In the limiting case, i.e., matching sequence is found when reading 193 row, then it is this parallel
The method of search will be 5 times faster than traversal search line by line.
3rd, the X for detecting matching search circuit, Y-coordinate value are demarcated as the initial position of DS-1 multi-frames.Scaling method
As follows, in fig. 6, it is supposed that the matching sequence coordinate value that (3,4) position shown in figure is, i.e.,
X=3,
Y=4,
Due to having recorded the position of write-in starting point, then in the serial sequence of entire DS-1 multi-frames, DS- in step 1
The position D of starting point of the initial position distance write-in RAM of 1 multi-frame is：
D=Y × 193+X.
The method for obtaining DS-1 multi-frame initial point positions in this way is as follows：One counter is set in FPGA, in the first step
The counter is 0 when the position of starting point is written, and is done from add operation whenever FPGA receives the bit counter, when the counting
At the time of the value of device is equal to D, the bit that FPGA is received is then the starting point of entire DS-1 multi-frames.In the simulation waveform of Figure 10,
S_frame_cnt is frame count, and from 0 meter to 192, total 193bit, i.e., one complete DS-1 frame, S_frame_num is frame
How many DS-1 frames counting number characterizes.Work as S_frame_num=0, while being the of write-in RAM when S_frame_cnt=0
The counter of one data, S_frame_cnt and S_frame_num compositions is above-mentioned reference coordinate.We are upper
Know that the coordinate of X-axis is 90 in one step, Y axis coordinate 1, the i.e. first write-in point DS-1 frames 90 of distance 1 bit of distance
Position be DS-1 multi-frame heads, O_t1_data_pulse is the mark of the position.
Since the frame length of each DS-1 frames is fixed as 193 bits, using the multi-frame initial position as basic point, every 193
Bit is the starting point of next DS-1 frames, and so on, can be from the F ratios positioned in the DS-1 code streams of input in DS-1 frames
The position of spy and multi-frame head, to achieve the purpose that each time slot of parsing.
Claims (1)
1. one kind being suitable for DS-1 frame receiving side analytic methods, it is characterised in that described method includes following steps：
1st, the electric signal in line side is converted to the serial digital sequence of logic side after line side PHY processing, and transmit
To programmable logic array (FPGA), DS-1 frames are stored into RAM with a matrix type in FPGA；By DS-1 frames with matrix
Form store into RAM the specific steps are：
1.1st, it is 13 bits that setting RAM, which is address bus bit wide,；
1.2nd, base address of high 5 bit as each basic frame storage；
1.3rd, storage address of low 8 bit as each bit of basic frame；
Mode of operation is as follows, a counter is arranged, low 8 bit each clock cycle of address, counter counts were to one from adding
It is zeroed when complete DS-1 frame lengths, that is, is zeroed when counting up to 193；And high 5 bit adds 1 simultaneously, and so on；It is deposited by such
Storage mode has obtained a storage array for being similar to matrix；Each row of matrix are a basic frame of DS-1, and matrix
It is then the combination of the bit of different DS-1 frames same positions per a line；By the control to address ram, read according to the row of matrix
RAM；Mode of operation is as follows：One counter is set, when reading RAM, from adding, least-significant byte remains unchanged high 5 of address, when
When counter counts are to 24, then it represents that have read a line；If reading the next line of matrix, the least-significant byte for controlling address ram adds 1
；
2nd, by carrying out parallel traversal search to RAM, obtain the X of DS-1 frames, Y coordinate；
Parallel traversal search method is that the RAM of 193 rows obtained by the 1st step is divided into 5 sections, simultaneously by 5 search engines
Row searches for the characteristic sequence of compound DS-1 frames, to achieve the purpose that shorten search time, and finally finds compound mark in a matrix
Accurate sequence；
3rd, using obtained X, Y coordinate extracts DS-1 frame sequences；Coordinate extract the step of be specially：
The starting position coordinates for the composite standard sequence that 2nd step obtains are demarcated as to the starting point of DS-1 multi-frames, that is, it is multiple to obtain DS-1
Frame initial point position, using the multi-frame initial position as basic point, every the starting point that 193 bits are next DS-1 frames.
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| CN1184387A (en) * | 1996-11-29 | 1998-06-10 | 富士通株式会社 | Reception pointer processing apparatus in SDH transmission system |
| CN1206153A (en) * | 1997-07-07 | 1999-01-27 | 三星电子株式会社 | Method and apparatus for reducing jitter or wander on internet working between ATM network and PDH network |
| CN1612516A (en) * | 2003-10-31 | 2005-05-04 | 上海贝尔阿尔卡特股份有限公司 | Automatic selector of clock source for synchronous digital series system |
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