CN104935338A - Method and system for extending DDS output signal frequency range - Google Patents
Method and system for extending DDS output signal frequency range Download PDFInfo
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Abstract
The invention discloses a method and system for extending a DDS output signal frequency range. The method comprises the following steps: firstly decoding a frequency control word and generating a reset signal according to the change condition of the control word, and then obtaining an initial phase of each of N paths of DDS IP cores in real time according to the frequency control word and the reset signal; and generating N paths of DDS data according to the frequency control word, the reset signal and the initial phases, and generating a phase marking signal for marking the phase relation among the N paths of DDS data, and finally realigning and combining the DDS data according to the marking signal to obtain a continuous signal, and converting the continuous signal into an analog signal to output. The system comprises a frequency control word generating module, an initial phase management module, a data production module, a data post-processing module and a digital-to-analog conversion module. The problem that the frequency range of signals generated in the existing DDS technology is limited by a work clock is solved, so that the output signal frequency range can reach several times of the work clock.
Description
Technical field
The invention belongs to information transmission and treatment technology, signal generator and equipment total digitalization field, the particularly a kind of method and system expanding DDS output signal frequency scope.
Background technology
In fields such as signal generator, equipment total digitalizations, the main method that system produces signal is direct digital frequency synthesis technology (DDS), namely utilize digital processing technology to form a waveform outputed signal, then reconstruct a sine wave or required signal waveform by a digital to analog converter.DDS technology can provide excellent phase noise, and frequency resolution is high, and this is mainly limited to the length of DDS phase accumulator.
According to the generation principle of DDS, the major defect of DDS is that reference frequency output is narrow, be only the half of input clock frequency, when utilizing FPGA (Field-Programmable Gate Array, field programmable gate array)+DAC (digital-to-analogue conversion) technology produce DDS signal time, reference frequency output is limited to the work clock of FPGA device, the DDS IP kernel work clock of V7 Series FPGA as up-to-date in Xilinx company is 550MHz the soonest, then the highest frequency exporting DDS signal is only 275MHz.Narrower reference frequency output can not meet the application of the occasions such as broadband signal generation, thus can not play DDS technology Low phase noise, high-resolution and the controllable advantage of frequency in broadband signal field.
Summary of the invention
In order to solve the technical problem that above-mentioned background technology proposes, the present invention aims to provide a kind of method and system expanding DDS output signal frequency scope, solve existing DDS technology and produce the limited problem with work clock of signal frequency range, make output signal frequency scope can reach the several times of work clock.
In order to realize above-mentioned technical purpose, technical scheme of the present invention is:
Expand a method for DDS output signal frequency scope, the method utilizes N road parallel DDS output data to carry out frequency range expansion, and by output signal frequency scope expansion N doubly, wherein N gets the power side of 2, comprises the following steps:
(1) be 32 binary frequency control words by the FREQUENCY CONTROL Instruction decoding from host computer, and produce reset signal according to the situation of change of this frequency control word;
(2) according to the dynamic change of the initial phase of frequency control word and reset signal real-time management N road DDS IP kernel;
(3) according to frequency control word, reset signal and initial phase, utilize N road DDS IP kernel to generate N road DDS data, and generate the marking signal being used for identifying phase relation between the DDS data of N road;
(4) according to id signal, DDS data permutation is combined, make the Phase Continuation combining rear DDS data;
(5) analogue data is become to export DDS data transaction.
Expand a system for DDS output signal frequency scope, comprise frequency control word generation module, first phase administration module, data generating module, Data Post module and D/A converter module;
Described frequency control word generation module comprises frequency control data receiving element, decoder and reset signal generation unit; Described frequency control data receiving element receives the instruction of host computer, and parses output frequency value according to communication protocol; This output frequency value is decoded as 32 binary frequency control words by described decoder; The change of described reset signal generation unit frequency control word produces reset signal, if the frequency control word of this clock cycle input changes compared to the frequency control word of last periodical input, the reset signal that then reset signal generation unit exports is 1, otherwise the reset signal exported is 0;
The frequency control word that described first phase administration module exports according to frequency control word generation module and reset signal produce N road DDS data initial phase value separately, a first phase management phase using N number of clock cycle as first phase administration module, when reset signal is 1, first phase administration module collection frequency control word now, and in this first phase management phase, exporting N road DDS data initial phase value separately, the initial phase value that adjacent two first phase management phases export is continuous print;
Described data generating module comprises N road DDS IP kernel arithmetic element and marking signal generation unit, described N road DDS IP kernel arithmetic element generates N road DDS data according to frequency control word, reset signal and N road DDS data initial phase value separately, described marking signal generation unit generates phase flag signal, in order to indicate the phase relation between the DDS data of N road;
Described Data Post module comprises format conversion unit and phase place sequencing unit, and N road DDS data are offset binary form from complementary binary format conversion by described format conversion unit; The discontinuous DDS data arrangement of N road phase place after transcoding is become the DDS data of Phase Continuation by described phase place order module according to Such phase marking signal;
DDS data are converted to analog signal output by described D/A converter module.
Wherein, the decoding formula of above-mentioned decoder is,
In above formula, the decimal value of Δ θ represented by binary frequency control word, f
outfor output frequency value, f
clkfor the work clock of DDS IP kernel.
Wherein, above-mentioned reset signal generation unit comprises comparator and the delayer of clock synchronous, comparator comprises input port A and input port B, the frequency control word that decoder generates sends into the input port A of comparator and the input of delayer respectively, delayer sends after the clock cycle of frequency control word time delay into input port B, comparator exports reset signal according to the value of input port A and input port B, when the value that input port A inputs equals the value of input port B input, the reset signal that comparator exports is 0, otherwise, the reset signal that comparator exports is 1.
Wherein, above-mentioned Data Post module also comprises parallel serial conversion unit, and the DDS data that the N road that phase place sequencing unit exports by described parallel serial conversion unit walks abreast are converted to two-way serial data and give D/A converter module.
Wherein, above-mentioned D/A converter module is AD9739.
Adopt the beneficial effect that technique scheme is brought:
The present invention can change output signal frequency scope in real time according to user's request, and numeric field process advantage can be utilized to correct DDS output amplitude frequency curve, controls the frequency range, the amplitude characteristic that output signal under the condition not changing system hardware.In addition, the present invention can select the figure place of frequency control word according to application demand, figure place is wider, then the frequency resolution outputed signal is higher, the Phase Truncation Error that system is introduced also can be lower, meets the application in wideband-radar signal generation, radio freqency simulation system etc.Output signal frequency can be expanded to original N doubly by the present invention, and the hot-tempered index of the letter not affecting output signal, thus except the application in fields such as wideband radars, the fields such as the Wideband Signal Processing, broadband connections, broadband D/A system test can also be widely used in.
Accompanying drawing explanation
Fig. 1 is system architecture diagram of the present invention;
Fig. 2 is reset signal generation unit schematic diagram of the present invention;
Fig. 3 is the schematic diagram of first phase administration module of the present invention;
Fig. 4 is the analogous diagram that the present invention produces DDS data;
Fig. 5 is the sequential chart that the present invention produces DDS data;
Fig. 6 is the phase diagram of DDS data before and after phase place of the present invention sequence;
Fig. 7 is parallel-serial conversion sequential chart of the present invention.
Embodiment
Below with reference to accompanying drawing, technical scheme of the present invention is described in detail.
The invention provides a kind of method expanding DDS output signal frequency scope, the method utilizes DDS that N road walks abreast, close limit output data to carry out frequency range expansion, thus output signal frequency scope is expanded to original N doubly, wherein N gets the power side of 2, comprises the following steps:
(1) be 32 binary frequency control words by the FREQUENCY CONTROL Instruction decoding from host computer, and produce reset signal according to the situation of change of this frequency control word;
(2) according to the dynamic change of the initial phase of frequency control word and reset signal real-time management N road DDS IP kernel;
(3) according to frequency control word, reset signal and initial phase, utilize N road DDS IP kernel to generate N road DDS data, and generate the marking signal being used for identifying phase relation between the DDS data of N road;
(4) according to id signal, DDS data permutation is combined, make the Phase Continuation combining rear DDS data;
(5) analogue data is become to export DDS data transaction.
System architecture diagram of the present invention as shown in Figure 1, utilizes this system to realize the method for above-mentioned expansion DDS output signal frequency scope.This system is made up of FPGA device and D/A converter module, and described FPGA device comprises frequency control word generation module, first phase administration module, data generating module and Data Post module.
Frequency control word generation module, be that 32 binary frequency control words deliver to first phase administration module by the frequency control data Instruction decoding from host computer, and control first phase administration module and data generating module according to the situation of change generation reset signal rst_dds of frequency control word.
First phase administration module, carrys out the dynamic change of the initial phase of real-time management multichannel DDS IP kernel according to frequency control word and reset signal.
Data generating module, according to frequency control word, reset signal and initial phase, utilizes DDS IP kernel to generate DDS data, and generates marking signal write_flag for Data Post module according to phase relation.
Data Post module, by the offset binary form of complement format data transformation required for D/A converter module, then according to the phase relation between the parallel data of write_flag signal indication, data permutation is combined, make the Phase Continuation combining rear data, finally data are delivered to D/A converter module and export.
D/A converter module, is converted to analog signal output by the digital signal that FPGA produces.
Hereafter the course of work of whole system is described in detail, for convenience of description, hereafter using 8 times (namely N gets 8) expansion DDS output signal frequency scope as explanation.
Frequency control word generation module, comprises frequency control data receiving element, decoder and reset signal generation unit.Frequency control data receiving element receives the instruction that host computer issues, and parses output frequency value according to JTAG/USB communication protocol.This output frequency value is decoded as 32 binary frequency control words and delivers to first phase administration module by decoder, and controls first phase administration module and data generating module according to the situation of change generation reset signal rst_dds of frequency control word.Wherein, the decoding formula of decoder is
Δ θ is binary frequency control word b
31b
30b
0represented decimal value, f
outfor the output frequency value received, f
clkfor the work clock of DDS IP kernel, select frequency control word to be 32, then output signal frequency resolution is f
clk/ 2
32=0.559Hz.The schematic diagram of reset signal generation unit as shown in Figure 2, comprise comparator and the delayer of a clock synchronous, the frequency control word of input is first through the input port A of comparator, first phase administration module and data generating module is delivered to again through delayer, simultaneously, frequency control word after time delay delivers to the input port B of comparator, the frequency control word inputted with next cycle compares, if A=B, then control word is constant, reset signal rst_dds=0, otherwise, frequency control word input changes, the process starting next frequency exports, reset signal rst_dds=1.
First phase administration module, carrys out the dynamic change of the initial phase of real-time management multichannel DDS according to frequency control word and reset signal, as shown in Figure 3, comprise the adder of clock synchronous, shift unit, counter and block unit.According to DDS principle, when frequency control word is Δ θ, to produce DDS data are phase intervals is the discrete sampling data of Δ θ.When adopting 8 road concurrent techniques to realize frequency range expansion in the present invention, front 8 clock cycle, the first via exports the discrete data that 8 phase intervals are Δ θ, phase range is [0,7 Δ θ], second tunnel exports that 8 phase intervals are Δ θ, phase range is [8 Δ θ, 15 Δ θ] discrete data, then the i-th tunnel exports the discrete data that 8 phase intervals are Δ θ, phase range is [(8i-8) Δ θ, (8i-1) Δ θ], i=1,2 ..., 8; Ensuing 8 cycles, the first via exports that 8 phase intervals are Δ θ, phase range is [64 Δ θ, 64 Δ θ+7 Δ θ] discrete data, i-th tunnel exports the discrete data that 8 phase intervals are Δ θ, phase range is [64 Δ θ+(8i-8) Δ θ, 64 Δ θ+(8i-1) Δ θ].
According to upper type, high-frequency signal can be produced export in low work clock situation, and the DDS data phase produced is continuous, with the stage that 8 clock cycle are a first phase management, the first phase dynamic change situation of Ze Mei road DDS is: the initial phase value in each stage equals initial phase value on last stage and adds 64 Δ θ.In order to strictly control first phase management phase change situation, utilize 8 counters to count, counter adds 1 in each clock cycle, when maximum be added to 7 time become 0 again, again add up.Count 0 when stage starts, at the end of the stage, be counted as 7.Shift unit is the advantage utilizing fpga logic computing, realizes, by can obtain the first phase value of 8 road DDS data to the shifting function of frequency control word by shifting function the multiplication and division operation of data.Adder adds up to the phase place of each first phase management phase, when Counter Value equals 7, then on original basis, adds 64 Δ θ in the next clock cycle to the first phase of each DDS.In figure 3, A
0for frequency control word has just changed the first phase value of Shi Mei road DDS, A
incfor the phase accumulation value of each first phase management phase, cnt is clock counter.In first phase management first stage, i.e. front 8 clock cycle, adder exports and equals A
0, when cnt gets back to again 0, adder exports and equals B+A
inc.What adder exported is the data of 38, by blocking unit 38 bit data is blocked into the initial phase value of 32
Data generating module, comprises 8 road DDS IP kernel arithmetic element and marking signal generation units, and 8 road DDS IP kernel arithmetic elements, according to frequency control word, reset signal and initial phase, generate 8 road DDS data
marking signal generation unit phase relation generates marking signal write_flag for Data Post module.
Produce the analogous diagram of DDS data as shown in Figure 4, wherein PINC_IN is frequency control word input, POFF_IN is the input of first phase value, SCLR is reset signal (rst_dds) input, SINE is the DDS data exported, PHASE_OUT exports phase place corresponding to data, and Ready is the marking signal after DDS work effectively.Produce the sequential chart of DDS data as shown in Figure 5, when Ready is effective, (Ready=1) starts counting, and after having served as 8 clock cycle, write_flag becomes high level signal, otherwise is in low level state always.
Data Post module, comprise format conversion unit, phase place sequencing unit and parallel serial conversion unit, format conversion unit is by the offset binary form of complement format data transformation required for D/A conversion unit, then phase place sequencing unit combines data permutation according to the phase relation between the parallel data of write_flag signal indication, make the Phase Continuation combining rear data, finally by parallel serial conversion module, data are delivered to DAC device and export.
The specific implementation of format conversion unit is the data exported DDS
highest order
with 1 XOR negate, other positions and 0 XOR remain unchanged, and finally obtain data data
i(decimal system).
The phase relation schematic diagram of phase place sequence front and back DDS data as shown in Figure 6, phase place sequencing unit is for phase place sorts initial signal with write_flag signal, the discontinuous DDS data arrangement of 8 tunnel phase place is become the parallel data of Phase Continuation, specific implementation comprises 16 counters and 8x16 14 bit registers.
The operation of counter: when after write_flag signal effectively (becoming 1), counter counts from 0, i.e. datareg_cnt=0, when again counting from 0 after datareg_cnt count down to 15.
The operating procedure of register:
For each DDS IP i distributes 16 14 bit registers, namely reg_dout_i_1, reg_dout_i_2 ..., reg_dout_i_16, then 8 parallel DDS need the register of 8 groups 16 14 altogether, and each DDS correspondence is one group of register wherein.
As datareg_cnt=0, by the data data that DDS produces
ideposit reg_dout_i_1 respectively; Then give parallel serial conversion unit by the value in high 8 registers in first group of register of DDS 1 correspondence, by reg_dout_1_9 ..., 8x 14bit data in reg_dout_1_16 give parallel serial conversion unit.
As datareg_cnt=1, by the data data that DDS produces
ideposit reg_dout_i_2 respectively; Then give parallel serial conversion unit by the value in high 8 registers in first group of register of DDS 2 correspondence, by reg_dout_2_9 ..., 8x 14bit data in reg_dout_2_16 give parallel serial conversion unit.
Successively 1 is added to datareg_cnt, as datareg_cnt=7, by the data data that DDS produces
ideposit reg_dout_i_8 respectively; Then give parallel serial conversion unit by the value in high 8 registers in first group of register of DDS 8 correspondence, by reg_dout_8_9 ..., 8x 14bit data in reg_dout_8_16 give parallel serial conversion unit.
As datareg_cnt=8, by the data data that DDS produces
ideposit reg_dout_i_9 respectively; Then give parallel serial conversion unit by the value in low 8 registers in first group of register of DDS 1 correspondence, by reg_dout_1_1 ..., 8x 14bit data in reg_dout_1_8 give parallel serial conversion unit.
Successively 1 is added to datareg_cnt, as datareg_cnt=15, by the data data that DDS produces
ideposit reg_dout_i_16 respectively; Then give parallel serial conversion unit by the value in low 8 registers in first group of register of DDS 8 correspondence, by reg_dout_8_1 ..., 8x 14bit data in reg_dout_8_8 give parallel serial conversion unit.
After above-mentioned counter cycle execution terminates, counter restarts counting from 0, and the operation of register goes to the operating procedure of datareg_cnt=0.
Parallel serial conversion unit is the two-way serial data slow 8 channel parallel datas being converted to speed, and the speed of its serial data is 4 times of parallel data speed.Parallel-serial conversion design in the present invention is based on Xilinx OSERDES IP kernel, and as shown in Figure 7, be the parallel DDS data (D1 ~ D4) of 300MHz by input 4 road 14bit, speed, output is a road 14bit, speed is the serial data of 1.2GHz.Parallel serial conversion unit utilizes two groups of OSERDES, 8 road 300MHz data is converted to 2 road 1.2GHz data and gives D/A converter module.
D/A converter module, the 2 tunnel serial datas that parallel serial conversion unit exports are converted into analog signal output, and the present invention adopts AD9739.
Above embodiment is only and technological thought of the present invention is described, can not limit protection scope of the present invention with this, and every technological thought proposed according to the present invention, any change that technical scheme basis is done, all falls within scope.
Claims (6)
1. expand a method for DDS output signal frequency scope, it is characterized in that, the method utilizes the N road DDS that walks abreast to export data and carry out frequency range expansion, and by output signal frequency scope expansion N doubly, wherein N gets the power side of 2, comprises the following steps:
(1) be 32 binary frequency control words by the FREQUENCY CONTROL Instruction decoding from host computer, and produce reset signal according to the situation of change of this frequency control word;
(2) according to the dynamic change of the initial phase of frequency control word and reset signal real-time management N road DDS IP kernel;
(3) according to frequency control word, reset signal and initial phase, utilize N road DDS IP kernel to generate N road DDS data, and generate the marking signal being used for identifying phase relation between the DDS data of N road;
(4) according to id signal, DDS data permutation is combined, make the Phase Continuation combining rear DDS data;
(5) analogue data is become to export DDS data transaction.
2. expand a system for DDS output signal frequency scope, it is characterized in that: comprise frequency control word generation module, first phase administration module, data generating module, Data Post module and D/A converter module;
Described frequency control word generation module comprises frequency control data receiving element, decoder and reset signal generation unit; Described frequency control data receiving element receives the instruction of host computer, and parses output frequency value according to communication protocol; This output frequency value is decoded as 32 binary frequency control words by described decoder; The change of described reset signal generation unit frequency control word produces reset signal, if the frequency control word of this clock cycle input changes compared to the frequency control word of last periodical input, the reset signal that then reset signal generation unit exports is 1, otherwise the reset signal exported is 0;
The frequency control word that described first phase administration module exports according to frequency control word generation module and reset signal produce N road DDS data initial phase value separately, a first phase management phase using N number of clock cycle as first phase administration module, when reset signal is 1, first phase administration module collection frequency control word now, and in this first phase management phase, exporting N road DDS data initial phase value separately, the initial phase value that adjacent two first phase management phases export is continuous print;
Described data generating module comprises N road DDS IP kernel arithmetic element and marking signal generation unit, described N road DDS IP kernel arithmetic element generates N road DDS data according to frequency control word, reset signal and N road DDS data initial phase value separately, described marking signal generation unit generates phase flag signal, in order to indicate the phase relation between the DDS data of N road;
Described Data Post module comprises format conversion unit and phase place sequencing unit, and N road DDS data are offset binary form from complementary binary format conversion by described format conversion unit; The discontinuous DDS data arrangement of N road phase place after transcoding is become the DDS data of Phase Continuation by described phase place order module according to Such phase marking signal;
DDS data are converted to analog signal output by described D/A converter module.
3. a kind of system expanding DDS output signal frequency scope according to claim 2, is characterized in that: the decoding formula of described decoder is,
Wherein, the decimal value of Δ θ represented by binary frequency control word, f
outfor output frequency value, f
clkfor the work clock of DDS IP kernel.
4. a kind of system expanding DDS output signal frequency scope according to claim 2, it is characterized in that: described reset signal generation unit comprises comparator and the delayer of clock synchronous, comparator comprises input port A and input port B, the frequency control word that decoder generates sends into the input port A of comparator and the input of delayer respectively, delayer sends after the clock cycle of frequency control word time delay into input port B, comparator exports reset signal according to the value of input port A and input port B, when the value that input port A inputs equals the value of input port B input, the reset signal that comparator exports is 0, otherwise, the reset signal that comparator exports is 1.
5. a kind of system expanding DDS output signal frequency scope according to claim 2, it is characterized in that: described Data Post module also comprises parallel serial conversion unit, the DDS data that the N road that phase place sequencing unit exports by described parallel serial conversion unit walks abreast are converted to two-way serial data and give D/A converter module.
6. a kind of system expanding DDS output signal frequency scope according to claim 2, is characterized in that: described D/A converter module is AD9739.
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| US6091356A (en) * | 1998-10-05 | 2000-07-18 | Sensor Concepts Incorporated | Chirp source with rolling frequency lock for generating linear frequency chirps |
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