CN104934428A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN104934428A CN104934428A CN201410103887.7A CN201410103887A CN104934428A CN 104934428 A CN104934428 A CN 104934428A CN 201410103887 A CN201410103887 A CN 201410103887A CN 104934428 A CN104934428 A CN 104934428A
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Abstract
The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; groove isolation structures formed in the substrate; grid electrodes formed on the surfaces, between the adjacent groove isolation structures, of the substrate; and first dielectric layers formed on the side walls of the grid electrodes, wherein at least the first dielectric layers are partially arranged on the surfaces, between the adjacent groove isolation structures, of the substrate to enable the width of each grid electrode to be smaller than the width of the substrate surface between the adjacent groove isolation structures. According to the invention, two first dielectric layers are arranged on two sides of each grid electrode, so that on the premise that the width between the adjacent groove isolation structures is unchanged, the distance between the adjacent grid electrodes is increased, the short channel effect of the semiconductor device is further improved, and the performance of the semiconductor device is improved.
Description
Technical field
The application relates to semiconductor integrated circuit manufacture technology field, in particular to a kind of semiconductor device and preparation method thereof.
Background technology
Along with the integrated level in semiconductor integrated circuit is more and more higher, the distance in semiconductor device between grid is more and more less, causes the short-channel effect of semiconductor device more and more obvious, and then causes the hydraulic performance decline of semiconductor device.Such as, in the manufacturing process of flush type flash memory, the distance between grid (comprise floating boom and be formed at the control gate on floating boom) is very little, causes the coupled ratio between floating boom to decline, and then reduces the read-write speed of flash memory.
As shown in Figure 1 to Figure 3, illustrated therein is the method step forming the groove isolation construction between grid and grid in a kind of making of semiconductor device, it comprises: first, at the middle formation shallow trench 21 ' of substrate 10 ' and the isolated substance layer 22 ' being arranged in shallow trench 21 ', wherein substrate 10 ' is also formed with oxide skin(coating) 30 ', and then forms basal body structure as shown in Figure 1; Then, the substrate 10 ' between adjacent isolated substance layer 22 ' formed on the surface grid preparation layers 40 ' ', and then form basal body structure as shown in Figure 2; Finally, planarized gate preparation layers 40 ' ' to form grid 40 ', and removal unit divides isolation material layer 22 ', forms groove isolation construction 20 ', and then form basal body structure as shown in Figure 3.
In the manufacturing process of above-mentioned semiconductor device, form grid width be more than or equal to the width of substrate between groove isolation construction, the distance between neighboring gates is less than or equal to the width of groove isolation construction.At present, technical staff's width attempted by increasing groove isolation construction increases the distance between grid.But the increase of the width of groove isolation construction can reduce the integrated level of semiconductor device, and then limit further developing of semiconductor integrated circuit.
Summary of the invention
The application aims to provide a kind of semiconductor device and preparation method thereof, to increase the spacing of grid in semiconductor device, improves the performance of semiconductor device.
To achieve these goals, according to an aspect of the application, provide a kind of semiconductor device, this semiconductor device comprises: substrate; Groove isolation construction, is formed in substrate; Grid, is formed on the surface of the substrate between adjacent trenches isolation structure; First medium layer, is formed on the sidewall of grid, and is arranged on the substrate surface between adjacent trenches isolation structure at least partly, with the width making the width of grid be less than the substrate surface between adjacent trenches isolation structure.
Further, in the semiconductor device that the application is above-mentioned, the material of first medium layer be selected from SiN, SiON and SiCN one or more.
Further, in the semiconductor device that the application is above-mentioned, between grid and substrate, arrange second dielectric layer, second dielectric layer is connected to form groove structure with two the first medium layers being positioned at grid both sides, and described grid is formed in described groove structure.
Further, in the semiconductor device that the application is above-mentioned, arrange the 3rd dielectric layer between second dielectric layer and substrate, preferably the 3rd dielectric layer is oxide skin(coating).
Further, in the semiconductor device that the application is above-mentioned, semiconductor device comprises further: be formed at the 4th dielectric layer on the exposed surface of grid, groove isolation construction and first medium layer, preferably the 4th dielectric layer is preferably ONO layer.
According to the another aspect of the application, provide a kind of manufacture method of semiconductor device, this manufacture method comprises the following steps: provide substrate; Form shallow trench in the substrate and be arranged in the isolated substance layer of shallow trench, the upper surface of isolated substance layer is higher than the upper surface of substrate; Forming first medium layer higher than on the isolated substance layer sidewall of substrate top surface, and substrate surface between adjacent first medium layer is forming grid; Removal unit divides isolation material layer, forms groove isolation construction.
Further, in the manufacture method of the above-mentioned semiconductor device of the application, the step forming first medium layer comprises: on the sidewall and upper surface of isolated substance layer, form medium preparation layers; And remove the medium preparation layers be positioned on isolated substance layer upper surface, form first medium layer.
Further, in the manufacture method of the above-mentioned semiconductor device of the application, in the step forming first medium layer, substrate simultaneously between adjacent separator matter layer forms second dielectric layer, between adjacent separator matter layer, two first medium layers and second dielectric layer form groove structure, and grid is formed in groove structure.
Further, in the manufacture method of the above-mentioned semiconductor device of the application, the step forming first medium layer and second dielectric layer comprises: on the sidewall and upper surface of isolated substance layer, and substrate surface between adjacent separator matter layer forms the medium preparation layers arranged continuously; And remove the medium preparation layers be positioned on isolated substance layer upper surface, form first medium layer and second dielectric layer.
Further, in the manufacture method of the above-mentioned semiconductor device of the application, form first medium layer, the step of second dielectric layer and grid comprises: on the sidewall and upper surface of isolated substance layer, and substrate surface between adjacent separator matter layer forms the medium preparation layers arranged continuously; Grid preparation layers is formed in medium preparation layers between adjacent separator matter layer; Planarization, removes the medium preparation layers that is positioned on isolated substance layer upper surface, and higher than the grid preparation layers of isolated substance layer upper surface, forms first medium layer, second dielectric layer and grid.
Further, in the manufacture method of the above-mentioned semiconductor device of the application, medium preparation layers is selected from any one or more in SiN, SiON and SiCN.
Further, in the manufacture method of the above-mentioned semiconductor device of the application, after formation medium preparation layers, ion implantation is carried out to the substrate between adjacent separator matter layer.
Further, in the manufacture method of the above-mentioned semiconductor device of the application, after the gate formation, ion implantation is carried out to grid.
Further, in the manufacture method of the above-mentioned semiconductor device of the application, between second dielectric layer and substrate, form the 3rd dielectric layer, the step forming the 3rd dielectric layer is: form the 3rd medium preparation layers on the surface of a substrate; And etching the 3rd medium preparation layers and substrate, form shallow trench in the substrate, and using residue the 3rd medium preparation layers as the 3rd dielectric layer.
Further, in the manufacture method of the above-mentioned semiconductor device of the application, this manufacture method comprises further: after formation groove isolation construction, the exposed surface of grid, first medium layer and groove isolation construction forms the 4th dielectric layer, and preferably the 4th dielectric layer is ONO layer.
A kind of semiconductor device of technical scheme of application the application and preparation method thereof, the both sides sidewall that grid is adjacent with groove isolation construction forms first medium layer, makes the distance between the outer surface of two of grid both sides first medium layers be more than or equal to the width of the substrate surface between groove isolation construction.By arranging two first medium layers in grid both sides, under the prerequisite not changing width between adjacent trenches isolation structure, add the distance between neighboring gates, and then improve the short-channel effect of semiconductor device, thus improve the performance of semiconductor device.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows in the manufacture method of existing semiconductor device, formed in the substrate shallow trench and be arranged in shallow trench isolated substance layer after matrix cross-sectional view;
Fig. 2 shows in Fig. 1 the matrix cross-sectional view after forming grid between adjacent separator matter layer;
Fig. 3 shows the matrix cross-sectional view removed in Fig. 2 after part isolation material layer formation groove isolation construction;
Fig. 4 shows the cross-sectional view of the semiconductor device provided according to the execution mode of the application;
Fig. 5 shows the schematic flow sheet of the manufacture method of the semiconductor device provided according to the execution mode of the application;
Fig. 6 shows in the manufacture method of the semiconductor device provided at the execution mode of the application, provides the cross-sectional view of the matrix after substrate;
Fig. 7 shows the matrix cross-sectional view after the isolated substance layer forming shallow trench and be arranged in shallow trench in substrate shown in Fig. 6;
Fig. 8-1 shows and form first medium layer on the sidewall of the layer of isolated substance shown in Fig. 7, and the matrix cross-sectional view after substrate surface between adjacent first medium layer forms grid;
Fig. 8-2 shows and form first medium layer on the sidewall of the layer of isolated substance shown in Fig. 7, substrate between adjacent separator matter layer forms second dielectric layer, and the matrix cross-sectional view after substrate surface between adjacent first medium layer forms grid;
Fig. 9 shows the matrix cross-sectional view after the layer of partial partition matter shown in removal Fig. 8-2 formation groove isolation construction; And
Figure 10 shows the matrix cross-sectional view on the sidewall of the layer of first medium shown in Fig. 9 and the surface of grid after formation the 4th dielectric layer.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
As what introduce in background technology, along with the integrated level in semiconductor integrated circuit is more and more higher, distance in semiconductor device between grid is more and more less, causes the short-channel effect of semiconductor device more and more obvious, and then causes the hydraulic performance decline of semiconductor device.Present inventor studies for the problems referred to above, proposes a kind of semiconductor device.As shown in Figure 4, this semiconductor device comprises substrate 10, groove isolation construction 20, grid 40 and first medium layer 31.Groove isolation construction 20 is formed in substrate 10.Grid 40 is formed at substrate 10 between adjacent trenches isolation structure 20 on the surface.First medium layer 31 is formed on the sidewall of grid 40, and is arranged on substrate 10 between adjacent trenches isolation structure 20 at least partly on the surface, with the width making the width of grid 40 be less than substrate 10 surface between adjacent trenches isolation structure 20.
In this semiconductor device that the application provides, by arranging two first medium layers 31 respectively in grid 40 both sides, under the prerequisite not changing width between adjacent trenches isolation structure, the width of grid between relative decrease adjacent trenches isolation structure 20, add the width between neighboring gates, and then improve the short-channel effect of semiconductor device, thus improve the performance of semiconductor device.When this semiconductor device is flush type flash memory, the increase of the distance between grid (comprise floating boom and be formed at the control gate on floating boom), can improve the coupled ratio between floating boom, and then improves the read-write speed of flash memory.
In above-mentioned semiconductor device, first medium layer 31 can be the common dielectric material in this area.Preferably, first medium layer 31 is nitride, is more preferably any one or more in SiN, SiON and SiCN.Above-mentioned first medium layer 31 can and grid 40 between form good combination, be conducive to the performance improving semiconductor device further.
In above-mentioned semiconductor device, second dielectric layer 32 can be set between grid 40 and substrate 10, improve the puncture voltage of grid 40 with the potential barrier increased between grid 40 and substrate 10.Preferably this second dielectric layer 32 is connected to form groove structure with two the first medium layers 31 being positioned at grid both sides, and grid 40 is formed in this groove structure.Above-mentioned second dielectric layer 32 can be one-body molded with first medium layer 31, and both materials are identical, is preferably one or more in SiN, SiON and SiCN.Meanwhile, in above-mentioned semiconductor device, can also the 3rd dielectric layer 33 be set between second dielectric layer 32 and substrate 10, to increase the potential barrier between grid 40 and substrate 10 further.Preferably, the 3rd dielectric layer 33 is oxide skin(coating).
In the semiconductor device that the application is above-mentioned, semiconductor device comprise further be formed at grid 40, groove isolation construction 20 and first medium layer 31 exposed surface on the 4th dielectric layer 34.Preferably, preferably the 4th dielectric layer 34 is ONO layer.Above-mentioned ONO layer is oxide/nitride/oxide, is more preferably SiO
2/ SiN/SiO
2layer.Other grid 40 structure can also be formed on the 4th dielectric layer 34, to form stacked grid 40 in the manufacturing process of some semiconductor device.Such as in the manufacturing process of memory, at above-mentioned grid 40(as floating boom) upper form ONO layer after, formation control grid on ONO layer.
Meanwhile, present invention also provides a kind of manufacture method of semiconductor device.As shown in Figure 5, this manufacture method comprises the following steps: provide substrate 10; In substrate 10, form shallow trench 21 and be arranged in the isolated substance layer 22 of shallow trench 21, the upper surface of isolated substance layer 22 is higher than the upper surface of substrate 10; Forming first medium layer 31 higher than on isolated substance layer 22 sidewall of substrate top surface, and the substrate 10 between adjacent first medium layer 31 forms grid 40 on the surface; Removal unit divides isolation material layer 22, forms groove isolation construction 20.The method utilizes groove isolation construction 20 in forming process, need first to be formed the structure of isolated substance layer 22, and the sidewall of isolated substance layer 22 is formed first medium layer 31, and then the substrate 10 between adjacent first medium layer 31 forms grid 40 on the surface.The method technique is simple, easily operates, is formed harmless to grid, without impact, is applicable to large-scale production.
Illustrative embodiments according to the application will be described in more detail below.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
Fig. 6 to Figure 10 shows the manufacturing method of semiconductor device provided according to the application, the cross-sectional view of the matrix obtained after each step.Below in conjunction with Fig. 6 to Figure 10, further illustrate the manufacture method of the semiconductor device that the application provides.
First, provide substrate 10, and then form basal body structure as shown in Figure 6.Above-mentioned substrate 10 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), SiGe (GeSi) or carborundum (SiC), also can be silicon-on-insulator (SOI), germanium on insulator (GOI), or can also be other material, the III-V such as such as GaAs.
After substrate 10 is provided, in substrate 10, forms shallow trench 21 and the isolated substance layer 22 being arranged in shallow trench 21, and then form basal body structure as shown in Figure 7.At a kind of Alternate embodiments, one can be comprised in during the semiconductor for preparation and be positioned at grid 40(or optional second dielectric layer) and substrate 10 between the 3rd dielectric layer 33, usually the 3rd dielectric layer 33 is oxide skin(coating), and it may be used for increasing the potential barrier between grid 40 and substrate 10.Now, in substrate 10, form shallow trench 21 comprise with the step of the isolated substance layer 22 being arranged in shallow trench 21: first form the 3rd medium preparation layers on the surface at substrate 10; And by order etching the 3rd medium preparation layers and substrate 10, form shallow trench 21 in substrate 10, and using residual oxide preparation layers as the 3rd dielectric layer 33; In shallow trench 21, form isolated substance layer 22 further, and then form basal body structure as shown in Figure 7.
In a kind of execution mode of the application, after the step of isolated substance layer 22 forming shallow trench 21 and be arranged in shallow trench 21 in substrate 10, the sidewall of isolated substance layer 22 is formed first medium layer 31, and the substrate 10 between adjacent first medium layer 31 forms grid 40 on the surface, and then form the basal body structure as shown in Fig. 8-1.In a kind of preferred implementation of the application, the step forming first medium layer 31 comprises: on the sidewall and upper surface of isolated substance layer 22, form medium preparation layers; And remove the medium preparation layers be positioned on isolated substance layer 22 upper surface, the first medium layer 31 be positioned on isolated substance layer 22 sidewall can be formed, after grid 40 to be formed, namely this first medium layer 31 is positioned on the grid 40 both sides sidewall adjacent with groove isolation construction 20.
Preferably, above-mentioned medium preparation layers be selected from SiN, SiON and SiCN one or more, the technique forming above-mentioned medium preparation layers is chemical vapour deposition (CVD) or nitrogen treatment.In a kind of alternative of the application, adopt plasma reinforced chemical vapour deposition technique to prepare SiN layer, its process conditions are: with SiH
4and NH
3for reacting gas, wherein SiH
4flow be 300 ~ 500 cc/min, NH
3flow be 800 ~ 1200 cc/min, the pressure in chamber is 1 ~ 100torr, and radio-frequency power is 800 ~ 1200W, and sedimentation time is 10 ~ 60S.Remove the step of the medium preparation layers be positioned on isolated substance layer 22 upper surface, can include but not limited to adopt CMP (Chemical Mechanical Polishing) process or wet-etching technology, those skilled in the art can be selected from suitable technique and parameter thereof according to actual process demand.
In the another kind of execution mode of the application, after the step of isolated substance layer 22 forming shallow trench 21 and be arranged in shallow trench 21 in substrate 10, in the above-mentioned first medium layer 31 of formation and grid 40 step, when forming first medium layer 31, substrate 10 between adjacent separator matter layer 22 can form second dielectric layer 32, and two first medium layers 31 form groove structure with second dielectric layer 32 between adjacent separator matter layer 22, then in groove structure, form grid 40, and then form the basal body structure as shown in Fig. 8-2.Now, in the step forming first medium layer 31 and second dielectric layer 32, a kind of preferred implementation comprises: on the sidewall and upper surface of isolated substance layer 22, and the substrate 10 between adjacent separator matter layer 22 forms the medium preparation layers arranged continuously on the surface; And remove the medium preparation layers be positioned on isolated substance layer 22 upper surface, form first medium layer 31 and second dielectric layer 32.Preferably, above-mentioned medium preparation layers be selected from SiN, SiON and SiCN one or more, the technique forming above-mentioned medium preparation layers is chemical vapour deposition (CVD) or nitrogen treatment.The step removing the medium preparation layers be positioned on isolated substance layer 22 upper surface can include but not limited to adopt CMP (Chemical Mechanical Polishing) process or wet-etching technology, and those skilled in the art can be selected from suitable technique and parameter thereof according to actual process demand.
At the above-mentioned first medium layer 31 of formation, in the step of second dielectric layer 32 and grid 40, another kind of preferred implementation is: on the sidewall and upper surface of isolated substance layer 22, and the upper surface of substrate 10 between adjacent separator matter layer 22 forms the medium preparation layers arranged continuously; Grid preparation layers is formed in medium preparation layers between adjacent separator matter layer 22; Planarization, removes the medium preparation layers that is positioned on isolated substance layer 22 upper surface, and higher than the grid preparation layers of isolated substance layer 22 upper surface, forms first medium layer 31, second dielectric layer 32 and grid 40, and then form the basal body structure as shown in Fig. 8-2.Above-mentioned medium preparation layers is selected from any one or more in SiN, SiON and SiCN, and the technique forming above-mentioned medium preparation layers is chemical vapour deposition (CVD) or nitrogen treatment.Remove the medium preparation layers be positioned on isolated substance layer 22 upper surface, with the step of the grid preparation layers higher than isolated substance layer 22 upper surface, can include but not limited to adopt CMP (Chemical Mechanical Polishing) process or wet-etching technology, those skilled in the art can be selected from suitable technique and parameter thereof according to actual process demand.
In formation above-mentioned first medium layer 31, alternatively second dielectric layer 32 and grid 40 step, ion implantation can be carried out to the substrate 10 between adjacent separator matter layer 22, to improve the threshold voltage of formed semiconductor device after formation medium preparation layers.Similarly, ion implantation can also be carried out to grid 40 after formation grid 40.The ion of above-mentioned ion implantation can be P type ion or N-type ion, and the process conditions of ion implantation can set according to actual process demand.
Complete and form first medium layer 31 on the sidewall of isolated substance layer 22, and after the substrate 10 between adjacent first medium layer 31 forms the step of grid 40 on the surface, removal unit divides isolation material layer 22 to form groove isolation construction 20, and then forms basal body structure as shown in Figure 9.The technique removing above-mentioned isolated substance layer 22 can be wet-etching technology, and those skilled in the art can be selected from suitable technique and parameter thereof according to actual process demand.After it should be noted that removal unit divides isolation material layer 22, form the surface remaining isolated substance layer 22 in groove isolation construction 20 and higher or lower than the surface of substrate 10, also can flush with the surface of substrate 10.
After the above-mentioned groove isolation construction 20 of formation, the 4th dielectric layer 34 can also be formed on the exposed surface at grid 40, first medium layer 31 and groove isolation construction 20, and then form basal body structure as shown in Figure 10.Preferably, the 4th dielectric layer 34 is ONO layer.Above-mentioned ONO layer is oxide/nitride/oxide, is more preferably SiO
2/ SiN/SiO
2layer.In the manufacturing process of some semiconductor device, other grid 40 structure can also be formed on the 4th dielectric layer 34, to form stacked grid 40.Such as in the manufacturing process of memory, at above-mentioned grid 40(as floating boom) upper form ONO layer after, formation control grid on ONO layer.
From above description, can find out, the application's the above embodiments achieve following technique effect: on the both sides sidewall that grid is adjacent with groove isolation construction, define first medium layer, make the distance between the outer surface of two of grid both sides first medium layers be more than or equal to the width of the substrate surface between groove isolation construction.Therefore, the distance between neighboring gates is increased, and then improves the performance of semiconductor device.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (15)
1. a semiconductor device, is characterized in that, described semiconductor device comprises:
Substrate;
Groove isolation construction, is formed in described substrate;
Grid, is formed on the surface of the substrate between adjacent described groove isolation construction;
First medium layer, is formed on the sidewall of described grid, and is arranged on the surface of the substrate between adjacent described groove isolation construction at least partly, with the width making the width of described grid be less than the substrate surface between adjacent described groove isolation construction.
2. semiconductor device according to claim 1, is characterized in that, the material of described first medium layer be selected from SiN, SiON and SiCN one or more.
3. semiconductor device according to claim 1 and 2, it is characterized in that, between described grid and substrate, arrange second dielectric layer, described second dielectric layer is connected to form groove structure with two the described first medium layers being positioned at grid both sides, and described grid is formed in described groove structure.
4. semiconductor device according to claim 3, is characterized in that, arranges the 3rd dielectric layer between described second dielectric layer and substrate, and preferably described 3rd dielectric layer is oxide skin(coating).
5. semiconductor device according to claim 4, it is characterized in that, described semiconductor device comprises further: be formed at the 4th dielectric layer on the exposed surface of described grid, groove isolation construction and first medium layer, and preferably described 4th dielectric layer is preferably ONO layer.
6. a manufacture method for semiconductor device, is characterized in that, described manufacture method comprises the following steps:
Substrate is provided;
In described substrate, form shallow trench and be arranged in the isolated substance layer of described shallow trench, the upper surface of described isolated substance layer is higher than the upper surface of described substrate;
Forming first medium layer higher than on the described isolated substance layer sidewall of described substrate top surface, and substrate surface between adjacent described first medium layer is forming grid;
Remove the described isolated substance layer of part, form groove isolation construction.
7. manufacture method according to claim 6, is characterized in that, the step forming described first medium layer comprises:
The sidewall and upper surface of described isolated substance layer form medium preparation layers; And remove the medium preparation layers be positioned on described isolated substance layer upper surface, form described first medium layer.
8. manufacture method according to claim 6, it is characterized in that, in the step forming described first medium layer, substrate simultaneously between adjacent described isolated substance layer forms second dielectric layer, between adjacent described isolated substance layer, two described first medium layers and described second dielectric layer form groove structure, and described grid is formed in described groove structure.
9. manufacture method according to claim 8, is characterized in that, the step forming described first medium layer and second dielectric layer comprises:
On the sidewall and upper surface of described isolated substance layer, and substrate surface between adjacent described isolated substance layer is formed the medium preparation layers arranged continuously; And remove the medium preparation layers be positioned on described isolated substance layer upper surface, form described first medium layer and second dielectric layer.
10. manufacture method according to claim 8, is characterized in that, form described first medium layer, the step of described second dielectric layer and described grid comprises:
On the sidewall and upper surface of described isolated substance layer, and substrate surface between adjacent described isolated substance layer is formed the medium preparation layers arranged continuously;
Grid preparation layers is formed in medium preparation layers between adjacent described isolated substance layer;
Planarization, removes the medium preparation layers that is positioned on described isolated substance layer upper surface, and higher than the grid preparation layers of described isolated substance layer upper surface, forms described first medium layer, described second dielectric layer and described grid.
11. manufacture methods according to claim 7 or 9, it is characterized in that, described medium preparation layers is selected from any one or more in SiN, SiON and SiCN.
12. manufacture methods according to claim 7 or 9, is characterized in that, after the described medium preparation layers of formation, carry out ion implantation to the substrate between adjacent described isolated substance layer.
13. manufacture methods according to claim 6, is characterized in that, after the described grid of formation, carry out ion implantation to described grid.
14. manufacture methods according to claim 8, is characterized in that, between described second dielectric layer and substrate, form the 3rd dielectric layer, the step forming described 3rd dielectric layer is:
Described substrate surface forms the 3rd medium preparation layers; And etch described 3rd medium preparation layers and substrate, in described substrate, form shallow trench, and described 3rd medium preparation layers will be remained as the 3rd dielectric layer.
15. manufacture methods according to claim 6, it is characterized in that, described manufacture method comprises further: after the described groove isolation construction of formation, the exposed surface of described grid, described first medium layer and described groove isolation construction forms the 4th dielectric layer, and preferably described 4th dielectric layer is ONO layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110911476A (en) * | 2018-09-14 | 2020-03-24 | 长鑫存储技术有限公司 | Embedded grid structure and manufacturing method thereof |
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| CN102005375A (en) * | 2009-09-02 | 2011-04-06 | 中芯国际集成电路制造(上海)有限公司 | Method for constructing floating gate |
| US20130081301A1 (en) * | 2011-09-30 | 2013-04-04 | Applied Materials, Inc. | Stiction-free drying of high aspect ratio devices |
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| EP2284870A1 (en) * | 2009-08-12 | 2011-02-16 | Imec | Method for forming a floating gate non-volatile memory cell |
| CN102005375A (en) * | 2009-09-02 | 2011-04-06 | 中芯国际集成电路制造(上海)有限公司 | Method for constructing floating gate |
| US20130081301A1 (en) * | 2011-09-30 | 2013-04-04 | Applied Materials, Inc. | Stiction-free drying of high aspect ratio devices |
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Application publication date: 20150923 |