CN104934415A - Chip stacking interposer structure with passive component and manufacturing method thereof - Google Patents
Chip stacking interposer structure with passive component and manufacturing method thereof Download PDFInfo
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- CN104934415A CN104934415A CN201410100081.2A CN201410100081A CN104934415A CN 104934415 A CN104934415 A CN 104934415A CN 201410100081 A CN201410100081 A CN 201410100081A CN 104934415 A CN104934415 A CN 104934415A
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Abstract
The invention discloses a chip stacking interposer structure with a passive component. The chip stacking interposer structure comprises an interposer layer, a capacitor, a first contact window and a second contact window. The capacitor is embedded into the interposer layer or is above the interposer layer. The capacitor comprises a first electrode, a second electrode and dielectric between the first electrode and the second electrode. The first contact window is connected with the first electrode. The second contact window is connected with the second electrode. Furthermore the first contact window and the second contact window are arranged at the same side or different sides of the interposer layer.
Description
technical field
The present invention relates to a kind of integrated circuit structure and manufacture method thereof, and particularly relate to a kind of chip-stacked intermediary agent structure and the manufacture method thereof with passive device.
Background technology
For improving integrated level and the usefulness of integrated circuit, can by multiple chip-stacked, and with silicon perforation (the Through-Silicon Via in intermediary agent structure (Interposer), TSV) and circuit redistribution layer (Redistribution Layer, RDL) as the electric connection structure between chip.
But, existing silicon perforation/circuit redistribution layer manufacture craft does not comprise the manufacturing step of the passive devices such as capacitor, resistor and inductance, so when needs passive device, must the passive device that manufactures separately of connection in addition, and increase the trouble in manufacture craft.
Moreover, existing circuit redistribution layer manufacture craft is often 4 ×/6 × back segment (Back End of Line, BEOL) damascene manufacture craft, it comprises the steps such as groove/interlayer hole etching, copper seed deposition, copper electrochemical plating, chemomechanical copper grinding, and has the problem of high cost.
Summary of the invention
An object of the present invention is to provide a kind of chip-stacked intermediary agent structure with passive device, and it can remove the trouble of the passive device that other connection manufactures separately from.
Another object of the present invention is to provide a kind of manufacture method with the chip-stacked intermediary agent structure of passive device, it, except the trouble of passive device can removed other connection from and manufacture separately, can reduce the cost of circuit redistribution layer manufacture craft in certain embodiments.
For reaching above-mentioned purpose, of the present invention one towards the chip-stacked intermediary agent structure with passive device (passive component) comprise intermediary layer, capacitor, the first contact hole and the second contact hole.Capacitor is embedded in intermediary layer or is positioned on intermediary layer, comprise the first electrode, a dielectric medium and the second electrode, wherein dielectric medium is between the first the second electrodes, and the first electrode of part is not overlapping with the second electrode, and the second electrode is partly not overlapping with the first electrode.First contact hole and the first Electrode connection, the second contact hole and the second Electrode connection, and the first contact hole and the second contact hole are in the same side of intermediary layer.The example of this kind of intermediary agent structure is found in aftermentioned first to fourth embodiment of the present invention.
Of the present invention above-mentioned towards an embodiment in, described intermediary agent structure also comprises the first side that an insulating barrier is positioned at intermediary layer, wherein the first contact hole and the second contact hole are arranged in described insulating barrier, and are each passed through the first electrode and the second electrode and extend in intermediary layer.The example of this kind of structure is found in the aftermentioned first embodiment of the present invention.
Of the present invention above-mentioned towards another embodiment in, described intermediary agent structure also comprises the first side that the first insulating barrier is positioned at intermediary layer, and wherein the first contact hole and the second contact hole are arranged in the first insulating barrier, but not through this first electrode and this second electrode.The example of this kind of structure is found in aftermentioned second, third embodiment of the present invention.Described intermediary agent structure also comprises the via holes of substrate (through-substrate via) being arranged in intermediary layer, and is arranged in the first insulating barrier and by the metal wire above via holes of substrate.The example of this kind of structure is found in the aftermentioned fourth embodiment of the present invention.In the case, described intermediary agent structure also comprises the second insulating barrier between the surface and the first insulating barrier of the first side of intermediary layer, wherein the first electrode and the second electrode have part at least between the first insulating barrier and the second insulating barrier, and this metal wire more extends in the second insulating barrier.The example of this kind of structure is found in the aftermentioned third embodiment of the present invention.In addition, the size of this metal wire can measure-alike with this via holes of substrate, or different from the size of this via holes of substrate (example of this kind of structure is found in aftermentioned 3rd, the 4th embodiment of the present invention).
Another side of the present invention to the chip-stacked intermediary agent structure with passive device comprise intermediary layer, capacitor, the first contact hole and the second contact hole.Capacitor is embedded in intermediary layer or is positioned on intermediary layer, comprises the first electrode, a dielectric medium and the second electrode, and wherein dielectric medium is between the first the second electrodes.First contact hole and the first Electrode connection, the second contact hole and the second Electrode connection, and first, second contact hole is at the not homonymy of intermediary layer.The example of this kind of structure is found in aftermentioned 5th, the 6th embodiment of the present invention.
Above-mentioned another side of the present invention to an embodiment in, described intermediary agent structure also comprises the first side that an insulating barrier is positioned at intermediary layer, and wherein the first contact hole is arranged in this insulating barrier, and the second contact hole is arranged in intermediary layer and extends to the second side of this intermediary layer.
The manufacture method with the chip-stacked intermediary agent structure of passive device of the present invention comprises: intermediary layer is provided, formed in intermediary layer or on intermediary layer containing the first electrode, the second electrode and dielectric medium between the two capacitor, form the first contact hole and the first Electrode connection, and formation the second contact hole and the second Electrode connection.
In an embodiment of said method of the present invention, the method forming capacitor comprises: sequentially form the first electrode, described dielectric medium and the second electrode, some of first electrode is not overlapping with the second electrode, second electrode of part is not overlapping with the first electrode, and the first contact hole and the second contact hole are in the same side of intermediary layer.The example of this kind of method is found in aftermentioned first to fourth embodiment of the present invention.
Above-described embodiment also comprises: form insulating barrier in the first side of intermediary layer, and via holes of substrate is formed in insulating barrier and intermediary layer, in insulating barrier, form first and second contact hole, first, second contact hole is each passed through first, second electrode and extends in intermediary layer simultaneously.The example of this kind of method is found in the aftermentioned first embodiment of the present invention.
Or above-described embodiment also comprises: form an insulating barrier in the first side of intermediary layer, form via holes of substrate in insulating barrier and intermediary layer, and in insulating barrier, form the first contact hole and the second contact hole, it is not through this first electrode and this second electrode.The example of this kind of method is found in aftermentioned second, third embodiment of the present invention.
Or above-described embodiment also comprises: form via holes of substrate in intermediary layer, form the first insulating barrier in the first side of intermediary layer, and while first and second contact hole of formation, in the first insulating barrier, form the metal wire above by via holes of substrate.The example of this kind of method is found in the aftermentioned fourth embodiment of the present invention.In the case, above-described embodiment also comprises: after via holes of substrate is formed, before capacitor formed, form the step of the second insulating barrier at intermediary layer first side surface, wherein the one the second electrodes have part at least between the one the second insulating barriers, and metal wire more extends in the second insulating barrier.The example of this kind of method is found in the aftermentioned third embodiment of the present invention.
In another embodiment of said method of the present invention, the first contact hole and the second contact hole are at the not homonymy of intermediary layer.The example of this kind of method is found in aftermentioned 5th, the 6th embodiment of the present invention.
Another embodiment above-mentioned also comprises: form an insulating barrier in the first side of intermediary layer, wherein the first contact hole is arranged in insulating barrier, and the second contact hole is arranged in intermediary layer, and extends to the second side of intermediary layer.The example of this kind of method is found in the aftermentioned fifth embodiment of the present invention.In the case, this another embodiment also comprises: while formation second contact hole, form via holes of substrate in intermediary layer, and in insulating barrier, forms the metal wire above by via holes of substrate while formation first contact hole.
Or, another embodiment above-mentioned also comprises: before formation first electrode, form via holes of substrate in intermediary layer, formed by the metal wire above via holes of substrate, form the first insulating barrier over the metal lines, form the second insulating barrier after formation of the second electrode, and form the second contact hole in the second insulating barrier.The example of this kind of method is found in the aftermentioned sixth embodiment of the present invention.In the case, this another embodiment also comprises: before formation is by the metal wire above via holes of substrate, form a conductive layer on the interposer; Form patterning photoresist oxidant layer on the electrically conductive, wherein have a groove to expose the conductive layer of part and by above via holes of substrate, and above-mentioned metal wire will be formed in this groove afterwards; And after being to form metal wire in this groove, remove patterning photoresist oxidant layer.
Because chip-stacked intermediary agent structure of the present invention or its manufacture method incorporate the passive devices such as capacitor or its manufacture craft, therefore the trouble of the passive device that other connection manufactures separately can be removed from.
In addition, as adopted the method for the above-mentioned metal wire sequentially formed in conductive layer, patterning photoresist oxidant layer and photoresist oxidant layer opening to form circuit redistribution layer, then because not needing etching or cmp step, therefore the cost of circuit redistribution layer manufacture craft can obviously reduce.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A ~ 1E is the generalized section with the manufacture method of the chip-stacked intermediary agent structure of passive device of first embodiment of the invention, and wherein Fig. 1 E shows this structure.
Fig. 2 A ~ 2B is the generalized section with the manufacture method of the chip-stacked intermediary agent structure of passive device of second embodiment of the invention, and wherein Fig. 2 B shows this structure.
Fig. 3 A ~ 3C is the generalized section with the manufacture method of the chip-stacked intermediary agent structure of passive device of third embodiment of the invention, and wherein Fig. 3 C shows this structure.
Fig. 4 is the generalized section with the manufacture method of the chip-stacked intermediary agent structure of passive device of fourth embodiment of the invention, and shows this structure.
Fig. 5 A ~ 5B is the generalized section with the manufacture method of the chip-stacked intermediary agent structure of passive device of fifth embodiment of the invention, and wherein Fig. 5 B shows this structure.
Fig. 6 A ~ 6G is the generalized section with the manufacture method of the chip-stacked intermediary agent structure of passive device of sixth embodiment of the invention, and wherein Fig. 6 G shows this structure.
Fig. 7 is the upper schematic diagram with the chip-stacked intermediary agent structure of various passive device of one embodiment of the invention.
Symbol description
100,300,500,600: intermediary layer
102,308,506: the groove forming capacitor
103,116,302,309,502,507,602: lining
104,108,606,616,620,628: conductive layer
104a, 310,508,616a: hearth electrode
106,312,510,618: dielectric medium
108a, 314,512,620a: top electrode
104b, 310a: the underlapped part of hearth electrode 104a
108b, 314a: the underlapped part of top electrode 108a
110,316,514,622: capacitor
112,306,318,516,614,624: insulating barrier
114a: via holes of substrate opening
114b, 114c, 200a, 200b, 320b, 320c, 518b: contact window
118a, 304,504a, 604a, via holes of substrate
118b, 118c, 202a, 202b, 322b, 322c, 504b, 520b, 604b, 604c, 604c ', 634b: contact hole
320a, 518a: the groove inlayed
322a, 520a: metal wire
608,630: patterning photoresist oxidant layer
610,626: the opening in patterning photoresist oxidant layer
612: metal level
614a: separator
616a: resistor
632: the groove in patterning photoresist oxidant layer
634a: interlayer hole
Embodiment
Below will further illustrate the present invention by several embodiment and accompanying drawing, it is not intended to as limiting the scope of the invention.Wherein, first to fourth embodiment be about aforementioned of the present invention previous towards, some of first electrode is not overlapping with the second electrode, and the second electrode of part is not overlapping with the first electrode, and the first contact hole and the second contact hole are in the same side of intermediary layer.5th and the 6th embodiment be about aforementioned of the present invention rear one towards, wherein the first contact hole and the second contact hole are at the not homonymy of intermediary layer.
And from the manufacture method of intermediary agent structure, capacitor can be manufactured as first and second embodiment before via holes of substrate is formed, or manufacture after via holes of substrate is formed as the 3rd to the 6th embodiment.First contact hole of capacitor and the second contact hole can be manufactured with via holes of substrate as the first embodiment simultaneously, or as manufactured after via holes of substrate as the second to the 4th embodiment, or as the five or six embodiment one and via holes of substrate manufactures simultaneously and another one is manufactured after via holes of substrate.
Figure 1A ~ 1E is the generalized section of the manufacture method of the chip-stacked intermediary agent structure of the tool passive device of first embodiment of the invention, and wherein Fig. 1 E shows this structure.
Please refer to Figure 1A, first provide intermediary layer 100, its material is such as silicon or glass.Then in intermediary layer 100, groove 102 is formed, lining 103 and conductive layer 104 is sequentially formed again on intermediary layer 100 with groove 102, wherein the material of lining 103 is such as silica, and the material of conductive layer 104 is such as doping compound crystal silicon or metal, the metal be wherein suitable for is such as titanium nitride, titanium, tantalum, tantalum nitride or aluminium.In addition, when the material of intermediary layer 100 is the insulating material such as glass, lining 103 can be dispensed.
Please refer to Figure 1B, then conductive layer 104 is patterned as hearth electrode 104a, more sequentially form dielectric medium 106 and conductive layer 108 on intermediary layer 100 with groove 102, wherein conductive layer 108 maybe can fill up groove 102.The material of dielectric medium 106 is such as silicon oxide/silicon nitride/silicon oxide (ONO) composite bed, silica, silicon nitride, aluminium oxide, hafnium oxide (HfO
2), zirconia (ZrO
x) or mixing/laminated material etc.The example of the material of conductive layer 108 is identical with the example of the material of conductive layer 104.
Please refer to Fig. 1 C, then conductive layer 108 is patterned as top electrode 108a, thus make capacitor 110.Above patterned conductive layer 104 and conductive layer 108 design used make hearth electrode 104a have a part 104b on intermediary layer 100 surface not overlapping with top electrode 108a, and top electrode 108a has a part 108b on intermediary layer 100 not overlapping with hearth electrode 104a simultaneously.Next on intermediary layer 100 with capacitor 110, cover insulating barrier 112, its material is such as silica, silicon nitride, silicon oxynitride or cryogenic oxidation silicon (LTO) etc.
Please refer to Fig. 1 D, then in intermediary layer 100, form the via holes of substrate opening 114a holding via holes of substrate (through-substrate via) through insulating barrier 112, formed through insulating barrier 112 simultaneously and be each passed through not overlapping with the top electrode 108a part 104b of hearth electrode 104a, not overlapping with the hearth electrode 104a part 108b of top electrode 108a and contact window 114b, 114c of extending into intermediary layer 100.Then, form the lining 116 of via holes of substrate at the sidewall of via holes of substrate opening 114a, its method is such as first deposit one deck blanket to cover lining material and remove lining material in the region of contact window 114b, 114c again.The material of lining 116 is such as silica.In addition, when the material of intermediary layer 100 is the insulating material such as glass, lining 116 can be dispensed.
Please refer to Fig. 1 E, then in via holes of substrate opening 114a, via holes of substrate 118a is formed, simultaneously in contact window 114b, 114c, form contact hole 118b, 118c respectively, it is each passed through not overlapping with the top electrode 108a part 104b of hearth electrode 104a, not overlapping with the hearth electrode 104a part 108b of top electrode 108a and enters intermediary layer 100.The manufacture craft forming via holes of substrate 118a and contact hole 118b and 118c can comprise deposit barrier layers and/or crystal seed layer, step such as electrochemistry plating (Electrochemical Plating, ECP) and cmp etc.The material of via holes of substrate 118a and contact hole 118b and 118c is such as copper.In addition, when the material of intermediary layer 100 is silicon, via holes of substrate 118a is silicon perforation (TSV), and the via holes of substrate below in the second to the 6th embodiment and other embodiments unaccounted is also like this.
Fig. 2 A ~ 2B is the generalized section of the manufacture method of the chip-stacked intermediary agent structure of the tool passive device of second embodiment of the invention, and wherein Fig. 2 B shows this structure.
Please refer to Fig. 2 A, first form capacitor 110 and cover insulating barrier 112, its method is such as the explanation of the corresponding Figure 1A ~ 1C according to the first embodiment.In intermediary layer 100, the via holes of substrate opening 114 holding via holes of substrate is formed again through insulating barrier 112.Then on insulating barrier 112, form the lining 116 of via holes of substrate with the sidewall of via holes of substrate opening 114, then form via holes of substrate 118 in via holes of substrate opening 114, its formation method and material are such as aforementioned person.
Please refer to Fig. 2 B, then in insulating barrier 112, form contact window 200a, 200b, it exposes not overlapping with the top electrode 108a part 104b of hearth electrode 104a, not overlapping with the hearth electrode 104a part 108b of top electrode 108a respectively.Then in contact window 200a, 200b, form contact hole 202a, 202b respectively, it contacts not overlapping with the top electrode 108a part 104b of hearth electrode 104a, not overlapping with the hearth electrode 104a part 108b of top electrode 108a respectively.
Fig. 3 A ~ 3C is the generalized section of the manufacture method of the chip-stacked intermediary agent structure of the tool passive device of third embodiment of the invention, and wherein Fig. 3 C shows this structure.
Please refer to Fig. 3 A, first in intermediary layer 300, form via holes of substrate 304 across lining 302, then form insulating barrier 306 on intermediary layer 300 with via holes of substrate 304.Then in insulating barrier 306 with intermediary layer 300, groove 308 is formed, lining 309 is formed again on insulating barrier 306 with groove 308, then on the part surface of insulating barrier 306 with groove 308, form hearth electrode 310, its method is such as the explanation of the relevant hearth electrode 104a of corresponding Figure 1A ~ 1B according to the first embodiment.
Please refer to Fig. 3 B, then above insulating barrier 306 with groove 308, sequentially form dielectric medium 312 and top electrode 314, thus make capacitor 316.Wherein, form hearth electrode 310 and top electrode 314 design used makes hearth electrode 310 have a part 310a on intermediary layer 300 surface not overlapping with top electrode 314, while top electrode 314 have a part 314a on intermediary layer 300 not overlapping with hearth electrode 310.Then on insulating barrier 306 and capacitor 316, another insulating barrier 318 is covered.
Please refer to Fig. 3 C, then in insulating barrier 318 and 306, groove 320a is formed, simultaneously in insulating barrier 318, form contact window 320b, 320c, it exposes not overlapping with the top electrode 314 part 310a of hearth electrode 310, not overlapping with the hearth electrode 310 part 314a of top electrode 314 respectively.Then in groove 320a, metal wire 322a is formed as circuit redistribution layer, and contact hole 322b, 322c is formed respectively in contact window 320b, 320c, it contacts not overlapping with the top electrode 314 part 310a of hearth electrode 310, not overlapping with the hearth electrode 310 part 314a of top electrode 314 respectively.The size W of metal wire 322a
1the size W of via holes of substrate 304 can be greater than
2, as shown in the figure.The size of metal wire 322a also may with measure-alike (not the illustrating) of via holes of substrate 304.
Fig. 4 is the generalized section with the manufacture method of the chip-stacked intermediary agent structure of passive device of fourth embodiment of the invention, and shows this structure.
Please refer to Fig. 4, the difference of this 4th embodiment and aforementioned third embodiment is, does not form insulating barrier 306, and directly in intermediary layer 300, forms groove 308, and carry out the manufacture craft of subsequent capacitance device 316 after forming via holes of substrate 304.Therefore, metal wire 322a is only formed in insulating barrier 318.In addition, the thickness of insulating barrier 318 can optionally increase, and has required thickness to make metal wire 322a.
Fig. 5 A ~ 5B is the generalized section of the manufacture method of the chip-stacked intermediary agent structure of the tool passive device of fifth embodiment of the invention, and wherein Fig. 5 B shows this structure.
Please refer to Fig. 5 A, first in intermediary layer 500, form via holes of substrate 504a and contact hole 504b across lining 502, wherein the form of contact hole 504b is identical with via holes of substrate 504a.Then in intermediary layer 500, form groove 506, then form lining 507 in groove 506.Then above intermediary layer 500 with groove 506, form hearth electrode 508, dielectric medium 510 and top electrode 512, thus make capacitor 514, wherein hearth electrode 508 contacts with contact hole 504b.This top electrode 512, dielectric medium 510 are such as defined by same patterning cover curtain layer with hearth electrode 508 and obtain, thus having the border trimmed.
Please refer to Fig. 5 B, then on intermediary layer 500 with capacitor 514, cover insulating barrier 516, more simultaneously in wherein forming the groove 518a exposing via holes of substrate 504a, and expose the contact window 518b of a part of top electrode 512.Then in groove 518a, form metal wire 520a as circuit redistribution layer, and form contact hole 520b in contact window 518b, it contacts with top electrode 512.
Fig. 6 A ~ 6G is the generalized section of the manufacture method of the chip-stacked intermediary agent structure of the tool passive device of sixth embodiment of the invention, and wherein Fig. 6 G shows this structure.
Please refer to Fig. 6 A, first in intermediary layer 600, the contact hole 604b of hearth electrode of via holes of substrate 604a and 604a ', capacitor is formed across lining 602, and contact hole 604c and the 604c ' of resistor, the wherein form of contact hole 604b, 604c, 604c ' and via holes of substrate 604a, 604a ' identical.Then on above resulting structures, form conductive layer 606, it such as comprises barrier layer and/or crystal seed layer.The material of barrier layer is such as titanium nitride, titanium, tantalum or tantalum nitride etc., and the material of crystal seed layer is such as copper.
Please refer to Fig. 6 B, then on conductive layer 606, form patterning photoresist oxidant layer 608, wherein have multiple opening 610 to expose via holes of substrate 604a, 604a the partial electroconductive layer 606 of ' with contact hole 604b, 604c, 604c ' top.Then in opening 610, insert metal level 612 as the first metal layer (M1) and contact hole 604b, 604c, 604c ' extension, its method be such as electrochemistry plating (ECP).
Please refer to Fig. 6 C, then remove patterning photoresist oxidant layer 608, then remove the conductive layer 606 not being covered, typically with metal layers 612 coverings.Then, intermediary layer 600 with the surface of metal level 612 form insulating barrier 614, and its material is such as silica, silicon nitride, silicon oxynitride or cryogenic oxidation silicon (LTO) etc.
Please refer to Fig. 6 D, then patterned insulation layer 614, the partial metal layers 612 of electrical isolation to leave separator 614a being positioned at needing on via holes of substrate 604a '.Then on above resulting structures, sequentially form conductive layer 616, dielectric layer 618 and conductive layer 620, wherein the material of conductive layer 616 and 620 be such as titanium nitride, titanium, tantalum, tantalum nitride, aluminium or the compound crystal silicon etc. that adulterates, the material of dielectric layer 618 is such as silicon oxide/silicon nitride/silicon oxide (ONO) composite bed, silica, silicon nitride, aluminium oxide, hafnium oxide, zirconia (ZrO
x) or mixing/laminated material.
Please refer to Fig. 6 E, then patterned conductive layer 620, dielectric layer 618 and conductive layer 616, to form the capacitor 622 containing hearth electrode 616a, dielectric layer 618 and top electrode 620a, and resistor 616a.Contact hole 604b is electrically connected with hearth electrode 616a via the conductive layer 606 on it and metal level 612.Meanwhile, the two ends of resistor 616a respectively with contact hole 604c, 604c ' be electrically connected via conductive layer 606 therebetween and metal level 612.Then on resulting structures, form insulating barrier 624, it is such as a photoresist oxidant layer.Then in insulating barrier 624, form most openings 626, it exposes part top electrode 620a respectively, and the partial metal layers 612 above via holes of substrate 604a.Then in photoresist oxidant layer 624 with opening 626, form conductive layer 628, it such as comprises barrier layer and/or crystal seed layer, and wherein the example of the material of barrier layer and crystal seed layer as previously mentioned.
Please refer to Fig. 6 F, on conductive layer 628, then form another patterning photoresist oxidant layer 630, wherein have groove 632 to expose the conductive layer 628 of part, comprise the partial electroconductive layer 628 being arranged in opening 626.Then in opening 626 and groove 632, metal material is inserted, to form interlayer hole 634a in the opening 626 above via holes of substrate 604a, form the contact hole 634b of top electrode 620a in opening 626 above top electrode 620a, and in groove 632, form the second metal level (M2) 634c.
Please refer to Fig. 6 G, then remove patterning photoresist oxidant layer 630, then remove not by the conductive layer 628 of interlayer hole 634a, contact hole 634b and metal level 634c covering.
Though above embodiment only illustrates be integrated in capacitor in intermediary agent structure and resistor structure, inductance also can be integrated in intermediary agent structure.Fig. 7 is the upper schematic diagram with the chip-stacked intermediary agent structure of various passive device of one embodiment of the invention.
Please refer to Fig. 7, this intermediary agent structure has multiple via holes of substrate 10, and incorporates capacitor 20, resistor 30 and inductance 40, and its respective pin is connected to different via holes of substrates 10.Wherein, capacitor 20 has hearth electrode 22 and top electrode 24, to increase surface area and capacitance in this hearth electrode 22 and the extensible groove 26 entering to be formed in intermediary layer of top electrode 24, as previously mentioned.
In sum, because the chip-stacked intermediary agent structure of the above embodiment of the present invention or its manufacture method incorporate the passive device such as capacitor, resistor or its manufacture craft, therefore the trouble of the passive device that other connection manufactures separately can be removed from.
In addition, as adopted the method as described in above-mentioned 6th embodiment to form circuit redistribution layer, then because not needing etching or cmp step, therefore the cost of circuit redistribution layer manufacture craft can obviously reduce.
Although with the open the present invention of embodiment; but itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; a little change and retouching can be done, therefore being as the criterion of should defining depending on the claim of enclosing of protection scope of the present invention.
Claims (20)
1. there is a chip-stacked intermediary agent structure for passive device, comprising:
Intermediary layer;
Capacitor, be embedded in this intermediary layer or be positioned on this intermediary layer, comprise the first electrode, dielectric medium and the second electrode, wherein this dielectric medium is between this first electrode and this second electrode, this first electrode of part is not overlapping with this second electrode, and this second electrode of part is not overlapping with this first electrode;
First contact hole, with this first Electrode connection; And
Second contact hole, with this second Electrode connection,
Wherein this first contact hole and this second contact hole are in the same side of this intermediary layer.
2. there is the chip-stacked intermediary agent structure of passive device as claimed in claim 1, also comprise insulating barrier, be positioned at the first side of this intermediary layer, wherein this first contact hole and this second contact hole are arranged in this insulating barrier, and are each passed through this first electrode and this second electrode and extend in this intermediary layer.
3. there is the chip-stacked intermediary agent structure of passive device as claimed in claim 1, also comprise the first insulating barrier, be positioned at the first side of this intermediary layer, wherein this first contact hole and this second contact hole are arranged in this first insulating barrier, but not through this first electrode and this second electrode.
4. there is the chip-stacked intermediary agent structure of passive device as claimed in claim 3, also comprise
Via holes of substrate, is arranged in this intermediary layer; And
Metal wire, is arranged in this first insulating barrier and by above this via holes of substrate.
5. there is the chip-stacked intermediary agent structure of passive device as claimed in claim 4, also comprise the second insulating barrier, between the surface and this first insulating barrier of this first side of this intermediary layer, wherein this first electrode and this second electrode have part at least between this first insulating barrier and this second insulating barrier, and this metal wire also extends in this second insulating barrier.
6. there is the chip-stacked intermediary agent structure of passive device as claimed in claim 4, wherein the size of this metal wire and the measure-alike of this via holes of substrate.
7. have the chip-stacked intermediary agent structure of passive device as claimed in claim 4, wherein the size of this metal wire is different with the size of this via holes of substrate.
8. there is a chip-stacked intermediary agent structure for passive device, comprising:
Intermediary layer;
Capacitor, is embedded in this intermediary layer or is positioned on this intermediary layer, comprises the first electrode, dielectric medium and the second electrode, and wherein this dielectric medium is between this first electrode and this second electrode;
First contact hole, with this first Electrode connection; And
Second contact hole, with this second Electrode connection,
Wherein this first contact hole and this second contact hole are at the not homonymy of this intermediary layer.
9. there is the chip-stacked intermediary agent structure of passive device as claimed in claim 8, also comprise insulating barrier, be positioned at the first side of this intermediary layer, wherein this first contact hole is arranged in this insulating barrier, and this second contact hole is arranged in this intermediary layer and extends to the second side of this intermediary layer.
10. there is a manufacture method for the chip-stacked intermediary agent structure of passive device, comprising:
One intermediary layer is provided;
In this intermediary layer or on this intermediary layer, form a capacitor, this capacitor comprises the first electrode, a dielectric medium and the second electrode, and wherein this dielectric medium is between this first electrode and this second electrode;
Form the first contact hole and this first Electrode connection; And
Form the second contact hole and this second Electrode connection.
11. manufacture methods as claimed in claim 10 with the chip-stacked intermediary agent structure of passive device, the method wherein forming this capacitor comprises: sequentially form this first electrode, this dielectric medium and this second electrode, this first electrode some of is not overlapping with this second electrode, this second electrode of part is not overlapping with this first electrode, and this first contact hole and the second contact hole are in the same side of this intermediary layer.
12. manufacture methods as claimed in claim 11 with the chip-stacked intermediary agent structure of passive device, also comprise:
An insulating barrier is formed in the first side of this intermediary layer; And
A via holes of substrate is formed in this insulating barrier and this intermediary layer, simultaneously in this insulating barrier, form this first contact hole and this second contact hole, this first contact hole and this second contact hole are each passed through this first electrode and this second electrode and extend in this intermediary layer.
13. manufacture methods as claimed in claim 11 with the chip-stacked intermediary agent structure of passive device, also comprise:
An insulating barrier is formed in the first side of this intermediary layer;
A via holes of substrate is formed in this insulating barrier and this intermediary layer; And
In this insulating barrier, form this first contact hole and this second contact hole, this first contact hole and this second contact hole be not through this first electrode and this second electrode.
14. manufacture methods as claimed in claim 11 with the chip-stacked intermediary agent structure of passive device, also comprise:
A via holes of substrate is formed in this intermediary layer;
The first insulating barrier is formed in the first side of this intermediary layer; And
While this first contact hole of formation and this second contact hole, formed by the metal wire above this via holes of substrate in this first insulating barrier.
15. manufacture methods as claimed in claim 14 with the chip-stacked intermediary agent structure of passive device, also comprise: after this via holes of substrate is formed, before this capacitor formed, the second insulating barrier is formed on the surface of this first side of this intermediary layer, wherein this first electrode and this second electrode have part at least between this first insulating barrier and this second insulating barrier, and this metal wire more extends in this second insulating barrier.
16. manufacture methods as claimed in claim 10 with the chip-stacked intermediary agent structure of passive device, wherein this first contact hole and this second contact hole are at the not homonymy of this intermediary layer.
17. manufacture methods as claimed in claim 16 with the chip-stacked intermediary agent structure of passive device, also comprise: form an insulating barrier in the first side of this intermediary layer, wherein this first contact hole is arranged in this insulating barrier, and this second contact hole is arranged in this intermediary layer, and extend to the second side of this intermediary layer.
18. manufacture methods as claimed in claim 17 with the chip-stacked intermediary agent structure of passive device, also comprise:
While this second contact hole of formation, in this intermediary layer, form a via holes of substrate; And
While this first contact hole of formation, formed in this insulating barrier by the metal wire above this via holes of substrate.
19. manufacture methods as claimed in claim 16 with the chip-stacked intermediary agent structure of passive device, also comprise:
Before this first electrode of formation, in this intermediary layer, form a via holes of substrate;
Formed by the metal wire above this via holes of substrate;
This metal wire is formed the first insulating barrier;
After this second electrode of formation, form the second insulating barrier; And
This second contact hole is formed in this second insulating barrier.
20. manufacture methods as claimed in claim 19 with the chip-stacked intermediary agent structure of passive device, also comprise
Before formation is by the metal wire above this via holes of substrate, form a conductive layer on the interposer;
This conductive layer is formed a patterning photoresist oxidant layer, wherein has a groove to expose this conductive layer of part in this patterning photoresist oxidant layer and by above this via holes of substrate, and this metal wire will be formed in this groove afterwards; And
After forming this metal wire in the groove, remove this patterning photoresist oxidant layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410100081.2A CN104934415A (en) | 2014-03-18 | 2014-03-18 | Chip stacking interposer structure with passive component and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410100081.2A CN104934415A (en) | 2014-03-18 | 2014-03-18 | Chip stacking interposer structure with passive component and manufacturing method thereof |
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| CN104934415A true CN104934415A (en) | 2015-09-23 |
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| US20030201476A1 (en) * | 2002-04-25 | 2003-10-30 | Chartered Semiconductor Manufacturing Ltd. | Adjustable 3D capacitor |
| TW200807687A (en) * | 2006-06-15 | 2008-02-01 | Freescale Semiconductor Inc | Mim capacitor integration |
| US20100224960A1 (en) * | 2009-03-04 | 2010-09-09 | Kevin John Fischer | Embedded capacitor device and methods of fabrication |
| CN102543948A (en) * | 2012-02-09 | 2012-07-04 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN103346141A (en) * | 2012-01-06 | 2013-10-09 | 马克西姆综合产品公司 | Semiconductor device integrated with capacitor |
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|---|---|---|---|---|
| US20030201476A1 (en) * | 2002-04-25 | 2003-10-30 | Chartered Semiconductor Manufacturing Ltd. | Adjustable 3D capacitor |
| TW200807687A (en) * | 2006-06-15 | 2008-02-01 | Freescale Semiconductor Inc | Mim capacitor integration |
| US20100224960A1 (en) * | 2009-03-04 | 2010-09-09 | Kevin John Fischer | Embedded capacitor device and methods of fabrication |
| CN103346141A (en) * | 2012-01-06 | 2013-10-09 | 马克西姆综合产品公司 | Semiconductor device integrated with capacitor |
| CN102543948A (en) * | 2012-02-09 | 2012-07-04 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
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Application publication date: 20150923 |