CN104932985A - eDRAM (enhanced Dynamic Random Access Memory)-based GPGPU (General Purpose GPU) register filter system - Google Patents
eDRAM (enhanced Dynamic Random Access Memory)-based GPGPU (General Purpose GPU) register filter system Download PDFInfo
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- CN104932985A CN104932985A CN201510362198.2A CN201510362198A CN104932985A CN 104932985 A CN104932985 A CN 104932985A CN 201510362198 A CN201510362198 A CN 201510362198A CN 104932985 A CN104932985 A CN 104932985A
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Abstract
The invention discloses an eDRAM (enhanced Dynamic Random Access Memory)-based GPGPU (General Purpose GPU) register filter system. A register file is built with an eDRAM instead of an SRAM (Static Random Access Memory); the register file is used for storing data; and the data stored in the register file is refreshed regularly with a refresh strategy in order to ensure the data integrity. A GPGPU register file is built with a 3T1D-eDRAM or 1T1C-eDRAM instead of the SRAM. A refresh method comprises: (1) refresh operation: one refresh operation includes one reading operation and one writing operation on data in a register item in a way of taking the register item as a unit; and one register item consists of 32 32-bit registers; and (2) refresh method: repeated refresh operation is implemented according to a certain way to finish refresh of the whole register file. In particular, three refresh strategies such as bank bubble refresh and bank roaming refresh are adopted, so that the problem of loss of the data in the register file outside a life cycle is solved, and the integrity of the data is ensured.
Description
Technical field
The present invention relates to a kind of GPGPU system architecture, particularly a kind of GPGPU register file system based on eDRAM.
Technical background
GPGPU (General Purpose GPU, i.e. general-purpose computations graphic process unit) is applied in general-purpose computations in the multinuclear epoch more and more widely, facilitates the parallel processing of data greatly.In GPGPU, large-scale data parallel has benefited from higher memory bandwidth and a large amount of parallel threads.Ensure there is no freely switching of cost between a large amount of parallel thread, need a large amount of registers to preserve content and the state of all active threads.
Traditional GPGPU register file system is built by SRAM and forms.SRAM needs at least six transistors, and has higher leakage current, and this makes traditional SRAM register file system be easy to occupy large stretch of chip area and consume more energy.
In-line memory eDRAM storer has higher frequency range and the performance of finer and close framework, because eDRAM adopts the design being integrated in chip internal, therefore in initial designs, the bus-bar design that width can be adopted very high, owing to being just designed at chip stage, therefore do not need the pin count after changing chip package or the wiring scale of PCB.Therefore just can very laborsaving in the fabrication phase below.And on performance, with the in-line memory of the bus-bar of 256-bit width design, as long as clock pulse arrives 500MHz, the frequency range performance of 128Gb/s can be reached, and Stand Alone Memory controller has been compared in the lifting of bus-bar width, relatively simple and easy many especially.
Although eDRAM requires higher process technique, but because eDRAM and 1T-SRAM is equally the technology adopting one-transistor and Single Capacitance (1T1C) to reach, even if compare with the 6T framework of traditional embedded SRAM, less transistor AND gate electric capacity, the representative lower maintenance power consumption of work and less transistor size, although SRAM itself can be maintained electric charge, still need the current sinking continued to refresh unlike eDRAM and maintain data, do not need extra voltage to maintain action in theory, but in the part of crystal, still can be subject to the impact of processing procedure and framework problem own, and have the situation of electric leakage.
Summary of the invention
The technical problem to be solved in the present invention is, provides the register file system of a kind of GPGPU based on eDRAM, makes it to have better extensibility, energy efficiency and technique tolerance compared with traditional GPGPU register file system.
The object of the invention is to be achieved through the following technical solutions: a kind of GPGPU register file system based on eDRAM, is characterized in that:
1) SRAM is replaced to build register file with eDRAM; Register file is for storing data;
2) use flushing policy, the data stored in regular refresh register file, guarantee data integrity.
Further, GPGPU register file system, replaces SRAM to build GPGPU register file with 3T1D-eDRAM.3T1D DRAM refers to 3-transistor, 1-diode dynamic memory cells.
Further, GPGPU register file system, replaces SRAM to build GPGPU register file with 1T1C-eDRAM.Refer to one-transistor and Single Capacitance (1T1C).
Flushing policy based on the GPGPU register file system of eDRAM comprises: 1) refresh operation: in units of register entries, and a refresh operation is perform a read operation to the data in a register entries, a write operation; A register entries is made up of 32 32 bit registers; 2) method for refreshing: according to certain mode (comprising the method for step 1), implement repeatedly refresh operation, complete the refreshing of whole register file.3T1D DRAM refers to 3-transistor, 1-diode dynamic memory cells.Refer to one-transistor and Single Capacitance (1T1C).
Method for refreshing based on the GPGPU register file system of eDRAM comprises following three kinds:
1, completely register file refreshes: utilize a rolling counters forward, chooses a suitable time freezing register
File, during this period, implements refresh operation successively to the register entries of register file, until whole register file completes refreshing, and register file of then thawing and counter reset; The choosing of refresh time ensure to complete Refresh Data within data life cycles;
2, use bank bubble to refresh: when two registers are at same bank, cannot read, warp0 needs to wait for one-period more simultaneously, in this process, other bank of register file are idle, can implement refresh operation, and this is exactly bank bubble.Each register entries associates a counter, utilize the bank bubble plate bubble of a bubble detecting device detected register file, when bank bubble being detected, utilize a refreshing generator to need the register entries refreshed to implement refresh operation to one, reset corresponding counter simultaneously; If do not have enough bank bubble to ensure to complete the refreshing of whole register file within data life cycles, choose suitable time, complete register file is implemented to remaining register and refreshes;
Bank bubble described in said process comprises:
Article one, instruction needs multiple Data distribution8 of access at identical register file bank, and the access of these data needs serial to carry out, and therefore instruction needs to wait for multiple data access cycle, has other register file bank idle in the process of wait; Register file, not in the state of operating at full capacity, namely in one cycle, has register file bank idle; Bank comprises some register entries;
3, use bank roaming to refresh: a rolling counters forward is set, selects the roaming register file bank that suitable time starts one by one, at every turn to a register entries enforcement refresh operation of current bank; Repeat step above until whole register file is refreshed; Counter reset; Each refreshing is because comprise a read operation, a write operation; A counter is set, often crosses one-period counter and add 1.Refresh from the beginning, each register entries only refreshing a bank, different bank interlace refreshs, repeats step above until all bank are refreshed, the arrival register sum of counter, counter reset.Repeat process above, enter next round and refresh.The time that this strategy brush complete register needs is long, but in the process refreshed, the bank of all the other free time can process common read and write access.
Can be destroyed when carrying out read operation based on the data in the GPGPU register file system of 1T1C-eDRAM, for alleviating the impact of this destructive read operation, the present invention proposes a kind of register file bank organizational form and the GPGPU warp scheduling strategy for this organizational form, and the method is applied to the GPGPU register file system based on 1T1C-eDRAM; Described register file organization mode is on the basis of traditional register file organization mode, bank is divided into two groups; Described warp dispatching method is that warp scheduler launches odd number warp and even number warp in turn in the continuous print cycle, and odd number warp accesses first group of bank, and even number warp accesses second group of bank; If odd number/even number the warp be not ready for current, allows sequential filming even number/odd number warp.
Beneficial effect, the present invention is the register file system based on eDRAM.Due to eDRAM (enhancing dynamic RAM) higher transistor density and less energy leakage, register file system of the present invention, compared with legacy register file system, has the transistor density of twice and the energy leakage lower than an order of magnitude.Certainly based on the problem that the register file systems face data of eDRAM were lost outward in life cycle, register file system of the present invention needs regularly to perform refresh operation.Especially, because the data in the register file system reached based on 1T1C-eDRAM, i.e. one-transistor and Single Capacitance (1T1C) can be destroyed when carrying out read operation, this type systematic provides method and alleviates this destructiveness and all operate the impact brought.
The present invention contrasts existed system and has following contribution: 1) designed and Implemented the GPGPU register file system based on 3T1D-eDRAM and the GPGPU register file system based on 1T1C-eDRAM.There is better extendability, energy efficiency and technique tolerance than traditional GPGPU register file system based on SRAM.2) three kinds of Refresh Data strategies are provided, solve the problem can lost in life cycle based on the data in the GPGPU register file of eDRAM outward; Ensure the integrality of data.3) the GPGPU register file read operation based on 1T1C-eDRAM can destroy by the data read, and proposes for this problem the impact that a kind of method that GPGPU register file organization mode and warp scheduling strategy combine alleviates this destructive read operation.Make system of the present invention more perfect by these strategies and method.Adopt in-line memory scheme, there is lower system power consumption, utilize eDRAM design chips, because whole I/O just completes in the circuit of chip internal, gate stage, do not need to expend electric power in addition to drive external device (ED), compared with the mode of external memorizer, except more this advantage of power saving, also effectively clock pulse can be promoted.Although eDRAM requires higher process technique, but because eDRAM and 1T-SRAM is equally the technology adopting one-transistor and Single Capacitance (1T1C) to reach, even if compare with the 6T framework of traditional embedded SRAM, less transistor AND gate electric capacity, the representative lower maintenance power consumption of work and less transistor size.Analysis result shows, the present invention and tradition based on SRAM GPGPU register file system compared with, present better extensibility, energy efficiency and technique tolerance.
Accompanying drawing explanation
Fig. 1 a is register file system schematic of the present invention; 1b is the bank schematic diagram of register file in 1a;
Fig. 2 is 3T1D-eDRAM schematic diagram of the present invention;
Fig. 3 is 1T1C-eDRAM schematic diagram of the present invention;
Fig. 4 is the schematic flow sheet that the present invention uses bank bubble method for refreshing;
Fig. 5 is the register bank organizational form schematic diagram that the present invention is based on 1T1C-eDRAM register file system.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described.Wherein english terminology is the term that those skilled in the art are familiar with: Bank Arbtrator resolver Crosstar intersection star Collector Unit converges unit.
The present invention is the GPGPU register file system based on eDRAM, and the structure of register file system as shown in Figure 1.The present invention adopts the register file bank (having some register entries) in 3T1D-eDRAM structure register file system as shown in Figure 2.Generally speaking, on the process node of 45nm, the size of a 3T1D storage unit is 37 square millimeters, the register file system built by such 3T1D storage unit, a read operation needs 340fJ energy, one time write operation needs 134fJ energy, and the leakage energy of each bank is 17.2uW.The present invention also adopts the register file bank in 1T1C-eDRAM structure register file system as shown in Figure 3.Generally speaking, on the process node of 45nm, the size of a 1T1C storage unit is 18 square millimeters, the register file system built by such 1T1C storage unit, a read operation needs 281fJ energy, one time write operation needs 108fJ energy, and the leakage energy of each bank is 4.08uW.
Have life cycle based on the data stored in the GPUGPU register file system of eDRAM, exceeding life cycle data will lose, and the invention provides three kinds of flushing policy refresh data within data life cycles, guarantees data integrity.
The basic step of 3 kinds of flushing policy is described in detail: 1) register file refreshes completely: in setting GPGPU register file system, have 1024 register entries below by several embodiment, be divided into 16 bank (four layers of activewarp0-4 (referring to the warp that can be scheduled enlivened), every layer of 16 register entries), the life cycle of data is 512 cycles.Each refreshing, because comprise a read operation, a write operation, needs 2 cycles.A counter is set, often crosses one-period counter and add 1.When the numerical value of counter is 384, freeze whole register file, common register access is blocked, all bank in parallel refresh register, register entries serial in same bank refreshes, and have 64 register entries in a bank, refreshing whole register file needs 128 cycles, the numerical value of this hour counter is just in time 512, and all data complete brush again within life cycle.After whole register file has refreshed, counter resets, and register file recovers common access.When needing again to refresh, repeat process above, start next round and refresh.
2) bank bubble is used to refresh: the structure of setting GPGPU register file system as shown in Figure 1.Arrange a counter to each register entries, after each refreshing, counter resets.
As shown in Figure 2, bubble detecting device is responsible for detecting bank bubble.
For the warp0 (active warp0) in Fig. 1 b, if need in warp0 implementation to read R0 and R8, because these two registers are at same bank, cannot read simultaneously, warp0 needs to wait for one-period more, and in this process, other bank of register file are idle, can implement refresh operation, this is exactly bank bubble.Similarly, in current GPGPU, warp generally once accesses 1 to 2 registers, and register file is but divided into the bank of 8 or more, like this, some bank certainly will be had in register access process to be idle, can implement refresh operation, this is also bank bubble.When bubble detecting device detects a bank bubble, simple Compare Logic circuit detection counter value in idle bank is used to be less than the register entries of a threshold value, refresh maker and refresh these register entries detected at random, the register entries being positioned at different bank can be refreshed simultaneously, and the register entries being arranged in same bank can only refresh by Stochastic choice one.Generally speaking, bank bubble is a lot, utilizes bank bubble can refresh the data of whole register file within data life cycles.If but utilize bank bubble to be not enough to refreshing, according to the value of counter, select the time freezing register file that is suitable, complete register file is implemented to the register also do not refreshed and refreshes.
3) bank roaming is used to refresh: have 512 register entries in setting GPGPU register file system, be divided into 16 bank, the life cycle of data is 1024 cycles.Each refreshing, because comprise a read operation, a write operation, needs 2 cycles.A counter is set, often crosses one-period counter and add 1.Refresh from the beginning, each register entries only refreshing a bank, different bank interlace refreshs, repeats step above until all bank are refreshed, and the value of counter is just 1024, counter reset.Repeat process above, enter next round and refresh.The time that this strategy brush complete register needs is long, but in the process refreshed, the bank of all the other free time can process common read and write access.
Can be destroyed when carrying out read operation based on the data in the GPGPU register file system of 1T1C-eDRAM, for alleviating the impact of this destructive read operation, the present invention proposes a kind of method that register file bank organizational form and warp scheduling strategy combine, and describes the basic step of the method below by an embodiment in detail:
16 bank are had, 4 active warp in setting GPGPU register file system.As shown in Figure 3 register file bank is divided into two groups, bank0-7 forms first group of bank, bank8-15 and forms second group of bank, warp is divided into two groups according to No. warp simultaneously, then odd number warp is distributed to first group of bank, even number warp is distributed to second group of bank.Warp scheduler launches odd number warp and even number warp in turn in the continuous print cycle.When odd number warp is launched into first group of bank, need one-period to perform read operation, because read operation can destroy data, next cycle needs execution written-back operation.After launching odd number warp, an even number warp is transmitted into second group of bank at next cycle by warp scheduler immediately, because odd number warp is different with the bank that even number warp accesses, even if so their read operations need two cycles and by sequential filming, they do not conflict to the access of bank.By the transmitting odd number warp that replaces continuously and even number warp to different bank groups, dramatically reduce destructive read operation impact by the mode of a kind of similar pipeline.In above process, if one because writing of causing of read operation can operate, the write operation common with is identical can be merged into a write operation and perform.If the warp schedulable be not ready in another group warp in the process of scheduling, allow the warp of same group of sequential filming, in this case, if the written-back operation that the read operation of the warp instruction of current transmitting and upper one-period launch warp instruction is conflicted, the warp instruction of current transmitting needs to wait for.
In a word, the present invention uses the eDRAM of two types to replace SRAM to build GPGPU register file, the problem using 3 kinds of different flushing policy to solve the data based on eDRAM register file to lose in life cycle, a kind of method using register file bank organizational form and warp scheduling strategy to combine slows down the impact based on 1T1C-eDRAM register file destructive read operation.Although in order to these strategies and method addressing these problems proposition can increase some hardware costs and lower the performance of system to a certain extent, but due to eDRAM relative to SRAM at transistor density, the huge advantage of energy-conservation aspect, the register file system that the present invention proposes presents better extendability on the whole than legacy system, energy efficiency and technique tolerance.
Fig. 4 is the schematic flow sheet that the present invention uses bank bubble method for refreshing; From Bank0 to BankN-1, the flow process that refreshControll refresh control refreshes multiple bank register file, in bank register file, article one, instruction needs multiple Data distribution8 of access at identical register file bank, the access of these data needs serial to carry out, therefore instruction needs to wait for multiple data access cycle, has other register file bank idle in the process of wait; Register file, not in the state of operating at full capacity, namely in one cycle, has register file bank idle; Select the roaming register file bank that suitable time starts one by one.Be provided with counter and renewal.
Above the GPGPU register file system based on eDRAM provided by the present invention is described in detail; but these explanations can not be understood to limit scope of the present invention; protection scope of the present invention is limited by the claims of enclosing, and any change on the claims in the present invention basis is all protection scope of the present invention.
Claims (7)
1., based on a GPGPU register file system of eDRAM, it is characterized in that:
1) SRAM is replaced to build register file with eDRAM; Register file is for storing data;
2) use flushing policy, the data stored in regular refresh register file, guarantee data integrity.
2. based on the GPGPU register file system of eDRAM, it is characterized in that: replace SRAM to build GPGPU register file with 3T1D-eDRAM.
3. based on the GPGPU register file system of eDRAM, it is characterized in that: replace SRAM to build GPGPU register file with 1T1C-eDRAM.
4. according to the method for refreshing of the GPGPU register file system based on eDRAM one of claim 1-3 Suo Shu, it is characterized in that comprising: 1) refresh operation: in units of register entries, a refresh operation is perform a read operation to the data in a register entries, a write operation; A register entries is made up of 32 32 bit registers; 2) method for refreshing: according to certain mode, as step 1), implement repeatedly refresh operation, complete the refreshing of whole register file.
5. the method for refreshing of the GPGPU register file system based on eDRAM according to claim 4, is characterized in that comprising following three kinds:
1) register file refreshes completely: utilize a rolling counters forward, choose a suitable time freezing register file, during this period, successively refresh operation is implemented to the register entries of register file, until whole register file completes refreshing, register file of then thawing and counter reset; The choosing of refresh time ensure to complete Refresh Data within data life cycles;
2) use bank bubble to refresh: when two registers are at same bank, cannot read, warp0 needs to wait for one-period more simultaneously, in this process, other bank of register file are idle, and implement refresh operation, this is exactly bank bubble.Each register entries associates a counter, utilize the bank bubble of a bubble detecting device detected register file, when bank bubble being detected, utilize a refreshing generator to need the register entries refreshed to implement refresh operation to one, reset corresponding counter simultaneously; If do not have enough bank bubble to ensure to complete the refreshing of whole register file within data life cycles, choose suitable time, complete register file is implemented to remaining register and refreshes; Bank described in said process bubble: one instruction needs multiple Data distribution8 of access at identical register file bank, the access of these data needs serial to carry out, therefore instruction needs to wait for multiple data access cycle, has other register file bank idle in the process of wait; Register file, not in the state of operating at full capacity, namely in one cycle, has register file bank idle; Bank comprises some register entries;
3) use bank roaming to refresh: a rolling counters forward is set, selects the roaming register file bank that suitable time starts one by one, at every turn to a register entries enforcement refresh operation of current bank; Repeat step above until whole register file is refreshed; Counter reset.
6. the method for refreshing of the GPGPU register file system based on eDRAM according to claim 4, is characterized in that 2) in when using bank bubble to refresh, refresh because comprise a read operation, a write operation at every turn; A counter is set, often crosses one-period counter and add 1.Refresh from the beginning, each register entries only refreshing a bank, different bank interlace refreshs, repeats step above until all bank are refreshed, the arrival register sum of counter, counter reset; Repeat process above, enter next round and refresh.
7. the method for refreshing of the GPGPU register file system based on eDRAM according to claim 4, it is characterized in that register file organization mode and the GPGPU warp scheduling strategy for this organizational form, be applied to the GPGPU register file system based on 1T1C-eDRAM; Described register file organization mode is on the basis of traditional register file organization mode, bank is divided into two groups; Described warp dispatching method is that warp scheduler launches odd number warp and even number warp in turn in the continuous print cycle, and odd number warp accesses first group of bank, and even number warp accesses second group of bank.If odd number/even number the warp be not ready for current, allows sequential filming even number/odd number warp.
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