CN104932378A - Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping - Google Patents
Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping Download PDFInfo
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- CN104932378A CN104932378A CN201510322361.2A CN201510322361A CN104932378A CN 104932378 A CN104932378 A CN 104932378A CN 201510322361 A CN201510322361 A CN 201510322361A CN 104932378 A CN104932378 A CN 104932378A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
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- Automation & Control Theory (AREA)
- Emergency Protection Circuit Devices (AREA)
- Relay Circuits (AREA)
Abstract
The invention relates to a control method and circuit for a special transformer acquisition terminal to prevent remote control false tripping. According to the control method and circuit, when the terminal determines to emit tripping signals through a relay, the terminal can emit the tripping signals through the relay only by means of a complex logic sequence; high electric level signal output of a reset chip is adopted as a necessary condition of tripping signal emission; and the reset chip can output high electric level only when system voltage is normal and system program operates normally, and therefore, it can be ensured that no false tripping instructions are emitted.
Description
Technical field
The present invention relates to a kind of control method and the circuit that prevent remote control mistrip for specially becoming acquisition terminal.
Background technology
Special change acquisition terminal can realize the monitoring of load to Electricity customers and electric flux, and electric company realizes the ordered electric of power customer and the adjustment of network load by remote control tripping operation.According to existing remote control trip method, special change acquisition terminal is directly by MCU(micro-control unit) I/O port line drive and realize remote control tripping operation, its major defect is: main control MCU occurs that unexpected race flies, in system electrification and MCU initialization procedure, easily cause remote control misoperation, and then send error tripping order.
Summary of the invention
Technical matters to be solved by this invention is, a kind of control method and the circuit that prevent remote control mistrip for specially becoming acquisition terminal are provided, reset chip is only used in that system voltage is normal, system program normal operation time could export high level, in order to guarantee that inerrancy trip signal sends.
Technical scheme of the present invention is as follows:
Preventing a control method for remote control mistrip for specially becoming acquisition terminal, it is characterized in that:
1), adopt d type flip flop to do the input of prime remote signal, shake to prevent the I/O mouth of CPU and cause relay misoperation to do;
2), adopt multiple control signal to carry out the final output of pilot relay, only have when reset signal be high level, YK_EN1 connect high level and YK_EN2 connects low level time d type flip flop can effectively export;
3) multiple control signal, is only had could finally to export trip signal by pilot relay according to the change of correct sequencing, first YK_EN1 is connect high level when reset signal is stablized, YK_EN2 connects low level, then the D of d type flip flop is connect high level, the CLK finally by d type flip flop sends a rising edge just can send trip signal.
Realize a kind of control circuit of described control method, it is characterized in that: it comprises system CPU, reset chip and d type flip flop, also comprise the first Sheffer stroke gate D2C, the second Sheffer stroke gate D4B, the 3rd Sheffer stroke gate D2A, the 4th Sheffer stroke gate D2D and the 5th Sheffer stroke gate D2B, the 3rd Sheffer stroke gate D2A and the 4th Sheffer stroke gate D2D forms rest-set flip-flop circuit; Wherein, the RST pin reseting pin of welding system CPU and an input pin of the first Sheffer stroke gate D2C respectively of reset chip, first Sheffer stroke gate D2C output pin connects two input pins of the second Sheffer stroke gate D4B, the output pin of the second Sheffer stroke gate D4B connects the input pin of rest-set flip-flop circuit, the output pin of rest-set flip-flop circuit connects two input pins of the 5th Sheffer stroke gate D2B, and the output pin of the 5th Sheffer stroke gate D2B connects the CLR pin of d type flip flop; The I/O mouth First Line YK_EN1 of CPU connects another input pin of the first Sheffer stroke gate D2C and meets GND through pull down resistor R4; The I/O mouth second line YK_EN2 of CPU connects an input pin of the 4th Sheffer stroke gate D2D and meets VCC through pull-up resistor R3; The remote control that data in pin D1 to the D8 pin of d type flip flop and CLK pin meet CPU respectively exports control pin, and output pin Q1 to the Q8 of d type flip flop connects photoelectric isolating circuit respectively, and photoelectric isolating circuit connects relay through driving circuit.
Good effect of the present invention is: just must send trip signal by relay by a complicated logical order when terminal is determined to send trip signal by relay.And with reset chip export high level signal be the necessary condition sending trip signal.Reset chip is only used in that system voltage is normal, system program normal operation time could export high level, so can determine that inerrancy trip signal sends.
Accompanying drawing explanation
Fig. 1 is circuit theory diagrams of the present invention.
Embodiment
The present invention is further illustrated below in conjunction with drawings and Examples.
As shown in Figure 1, control circuit embodiment of the present invention comprises system CPU 1, reset chip 7 and the d type flip flop 2 that model is SAM9260, also comprise the first Sheffer stroke gate D2C, the second Sheffer stroke gate D4B, the 3rd Sheffer stroke gate D2A, the 4th Sheffer stroke gate D2D and the 5th Sheffer stroke gate D2B, the 3rd Sheffer stroke gate D2A and the 4th Sheffer stroke gate D2D forms rest-set flip-flop circuit 3.
Wherein, the RST pin reseting pin of welding system CPU1 and an input pin of the first Sheffer stroke gate D2C respectively of reset chip 7, first Sheffer stroke gate D2C output pin connects two input pins of the second Sheffer stroke gate D4B, the output pin of the second Sheffer stroke gate D4B connects an input pin R(i.e. input pin of the 3rd Sheffer stroke gate D2A of rest-set flip-flop circuit 3), the output pin of rest-set flip-flop circuit 3 connects two input pins of the 5th Sheffer stroke gate D2B, the output pin of the 5th Sheffer stroke gate D2B connects the CLR pin of d type flip flop 2, ensure only in the normal situation of system state, just can send trip signal.
The I/O mouth First Line YK_EN1 of CPU1 connects another input pin of the first Sheffer stroke gate D2C and meets GND through pull down resistor R4; The I/O mouth second line YK_EN2 of CPU1 connects an input pin of the 4th Sheffer stroke gate D2D and meets VCC through pull-up resistor R3.Thus ensure that, in system electrification process, when the I/O mouth of CPU is unstable, trip signal cannot send.
The present embodiment also comprises photoelectric isolating circuit 4, driving circuit 6 and relay.The remote control that data in pin D1 to the D8 pin of d type flip flop 2 and CLK pin meet CPU1 respectively exports control pin, it is omissive representation that output pin Q1 to the Q8 of d type flip flop 2 connects in photoelectric isolating circuit 4(Fig. 1 respectively, only illustrate Q1 to connect), photoelectric isolating circuit 4 connects relay 5 through driving circuit 6.
Control method of the present invention comprises following measures:
1), adopt d type flip flop to do the input of prime remote signal, prevent the I/O mouth of CPU from shaking and cause relay misoperation to do.
2), adopt multiple control signal to carry out the final output of pilot relay: to only have when reset signal completes, namely reset signal be high level and YK_EN1 connects high level, YK_EN2 connects low level time d type flip flop can effectively export.
3), adopt multiple control signal according to the final output trip signal of correct sequencing change ability pilot relay.First YK_EN1 is connect high level when reset signal is stablized, YK_EN2 connects low level, then the D of d type flip flop is connect high level, the CLK finally by d type flip flop sends a rising edge just can send trip signal.The wrong any step of above three orders all can not send out trip signal.
Basic logic is all realize by Sheffer stroke gate in the present invention, and wherein D2A and D2D realizes rest-set flip-flop function, and the S input end of rest-set flip-flop is expanded by D2C and D4B, and the output terminal that D2B realizes rest-set flip-flop is anti-phase.Above five Sheffer stroke gates combine the main logic realized in the present invention.The output terminal of above logic receives the clear terminal of d type flip flop, and only have when RST signal and YK_EN1 signal are high level by truth table is known, when YK_EN2 is low level, the clear terminal side of d type flip flop is invalid, and trip signal can export.D input and the CLK input of YK_EN1, YK_EN2 and d type flip flop are controlled by system CPU, first YK_EN1 should be connect high level, YK_EN2 connects low level, then the D of d type flip flop is connect high level, the CLK finally by d type flip flop sends a rising edge finally could send trip signal.YK_EN1 meets GND, YK_EN2 through pull down resistor R4 and meets VCC through pull-up resistor R3 and ensure that the clear terminal (CLR) of the d type flip flop when system one powers on is low level, and trip signal cannot send.When reset chip action, reset signal is low level, and be low level by the clear terminal (CLR) of the known now d type flip flop of truth table, trip signal cannot send.System electrification, if I/O port sets high in CPU initialization procedure, when YK_EN1, YK_EN2 set high simultaneously, data keep, and the clear terminal (CLR) of d type flip flop is low level, and trip signal cannot send; If I/O port sets low in CPU initialization procedure, zeros data when YK_EN1, YK_EN set low simultaneously, the clear terminal (CLR) of d type flip flop is low level, and trip signal cannot send.
When in operational process, system power supply suffers accidental destruction abnormal, reset chip action exports reset signal, and be low level by the clear terminal (CLR) of the known now d type flip flop of truth table, trip signal cannot send.
In a case where, circuit of the present invention all forbids tripping operation:
1, when powering on, YK_EN1 meets GND, YK_EN2 through pull down resistor R4 and meets VCC through pull-up resistor R3, and be low level by the clear terminal (CLR) of the known d type flip flop of truth table, trip signal is forbidden sending.
2, when reset chip action, reset signal is low level, and be low level by the clear terminal (CLR) of the known now d type flip flop of truth table, trip signal cannot send.Can avoid so electrification reset and system power supply abnormal time, send error tripping signal.
3, system initialization IO may be floating input (high-impedance state), may be set high, also may be set low.If floating input is then as [15], trip signal is forbidden sending; If set high, when YK_EN1, YK_EN2 all set high, data keep, and the clear terminal (CLR) of d type flip flop is still low level, and trip signal is forbidden sending; If set low, zeros data when YK_EN1, YK_EN2 all set low, the clear terminal (CLR) of d type flip flop is low level, and trip signal also cannot send.
When cancelling trip signal, first being set low by YK_EN1, then set high by YK_EN2, is low level by the clear terminal (CLR) of the known d type flip flop of truth table, and relay normally open contact disconnects, and trip signal is cancelled.Meanwhile the output register of d type flip flop is cleared, and when again sending out trip signal, again must operate according to original order completely, prevent trip signal cumulative error.
Claims (2)
1. preventing a control method for remote control mistrip for specially becoming acquisition terminal, it is characterized in that:
1), adopt d type flip flop to do the input of prime remote signal, shake to prevent the I/O mouth of CPU and cause relay misoperation to do;
2), adopt multiple control signal to carry out the final output of pilot relay, only have when reset signal be high level, YK_EN1 connect high level and YK_EN2 connects low level time d type flip flop can effectively export;
3) multiple control signal, is only had could finally to export trip signal by pilot relay according to the change of correct sequencing, first YK_EN1 is connect high level when reset signal is stablized, YK_EN2 connects low level, then the D of d type flip flop is connect high level, the CLK finally by d type flip flop sends a rising edge just can send trip signal.
2. realize a kind of control circuit of control method described in claim 1, it is characterized in that: it comprises system CPU (1), reset chip (7) and d type flip flop (2), also comprise the first Sheffer stroke gate D2C, the second Sheffer stroke gate D4B, the 3rd Sheffer stroke gate D2A, the 4th Sheffer stroke gate D2D and the 5th Sheffer stroke gate D2B, the 3rd Sheffer stroke gate D2A and the 4th Sheffer stroke gate D2D forms rest-set flip-flop circuit (3); Wherein, the RST pin of reset chip (7) is welding system CPU(1 respectively) reseting pin and the input pin of the first Sheffer stroke gate D2C, first Sheffer stroke gate D2C output pin connects two input pins of the second Sheffer stroke gate D4B, the output pin of the second Sheffer stroke gate D4B connects the input pin (R) of rest-set flip-flop circuit (3), the output pin of rest-set flip-flop circuit (3) connects two input pins of the 5th Sheffer stroke gate D2B, and the output pin of the 5th Sheffer stroke gate D2B connects the CLR pin of d type flip flop (2); CPU(1) I/O mouth First Line YK_EN1 connects another input pin of the first Sheffer stroke gate D2C and meets GND through pull down resistor R4; CPU(1) I/O mouth second line YK_EN2 connects an input pin of the 4th Sheffer stroke gate D2D and meets VCC through pull-up resistor R3; Data in pin D1 to D8 pin and the CLK pin of d type flip flop (2) meet CPU(1 respectively) remote control export control pin, output pin Q1 to the Q8 of d type flip flop (2) connects photoelectric isolating circuit (4) respectively, and photoelectric isolating circuit (4) connects relay (5) through driving circuit (6).
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| CN201510322361.2A CN104932378B (en) | 2015-06-13 | 2015-06-13 | Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping |
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| CN201510322361.2A CN104932378B (en) | 2015-06-13 | 2015-06-13 | Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping |
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| CN104932378B CN104932378B (en) | 2017-05-17 |
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Cited By (3)
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| CN109258113A (en) * | 2018-11-16 | 2019-01-25 | 常州格力博有限公司 | Grass trimmer |
| CN110323712A (en) * | 2019-07-31 | 2019-10-11 | 西安天和防务技术股份有限公司 | Current potential keeps control method and overcurrent protection control method |
| CN111147046A (en) * | 2019-12-23 | 2020-05-12 | 陕西电器研究所 | Relay array control device and method |
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| CN104932378B (en) | 2017-05-17 |
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Address after: 264003 Laishan City, Yantai province Venture Center, Shandong Applicant after: Yantai Dongfang Wisdom Electric Co., Ltd. Address before: 264003 Laishan City, Yantai province Venture Center, Shandong Applicant before: Yantai Dongfang Wisdom Electronic Co., Ltd. |
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