CN104916624B - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
CN104916624B
CN104916624B CN201410448445.6A CN201410448445A CN104916624B CN 104916624 B CN104916624 B CN 104916624B CN 201410448445 A CN201410448445 A CN 201410448445A CN 104916624 B CN104916624 B CN 104916624B
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China
Prior art keywords
mentioned
layer
chip
resin layer
wiring layer
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CN201410448445.6A
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CN104916624A (en
Inventor
栗田洋郎
栗田洋一郎
江泽弘和
河崎茂
河崎一茂
筑山慧至
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Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Memory Corp
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Priority to CN201811248184.8A priority Critical patent/CN109390326B/en
Publication of CN104916624A publication Critical patent/CN104916624A/en
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract

A kind of inexpensive and semiconductor device of high reliablity and its manufacturing method are provided.The 1st face of upper layer chip is arranged in 1st resin layer.1st wiring layer is arranged in the 1st resin layer, is electrically connected with upper layer chip.The surface side of the 1st resin layer is arranged in 2nd resin layer, and expands to the side chip exterior domain in the outer part than upper layer chip.2nd wiring layer is arranged in the 2nd resin layer, connect with the 1st wiring layer, extends to chip exterior domain.Lower layer chip is mounted on the surface side of the 1st resin layer, connect with the 1st wiring layer.

Description

Semiconductor device and its manufacturing method
This application claims applied based on Japanese patent application 2014-51235 (applying date: on March 14th, 2014) Priority.The application applies by referring to the basis and the full content comprising basic application.
Technical field
The present invention relates to semiconductor device and its manufacturing methods.
Background technique
The laminated body of the known multiple chips that will be connected by TSV (Through-Silicon Via, through silicon via) is to wiring Substrate carries out the packaging structure of salient point (bump) connection.In addition, in such configuration, it is also proposed that will for multiple memory chips Interface chip (interface chip) passes through the construction of TSV connection.
Summary of the invention
Embodiments of the present invention provide a kind of inexpensive and high reliablity semiconductor device and its manufacturing method.
According to embodiment, semiconductor device has upper layer chip, the 1st resin layer, the 1st wiring layer, the 2nd resin layer, the 2nd Wiring layer, lower layer chip and sealing resin.Above-mentioned upper layer chip has the 2nd face of the opposite side in the 1st face and above-mentioned 1st face.On State above-mentioned 1st face that above-mentioned upper layer chip is arranged in the 1st resin layer.Above-mentioned 1st wiring layer is arranged in above-mentioned 1st resin layer, It is electrically connected with above-mentioned upper layer chip.The surface side of above-mentioned 1st resin layer is arranged in above-mentioned 2nd resin layer, and expands to than upper State the chip exterior domain of the side of upper layer chip in the outer part.Above-mentioned 2nd wiring layer is arranged in above-mentioned 2nd resin layer, and above-mentioned The connection of 1st wiring layer, extends to said chip exterior domain.Above-mentioned lower layer chip is mounted on the above-mentioned surface of above-mentioned 1st resin layer Side is connect with above-mentioned 1st wiring layer.Above-mentioned sealing resin covers above-mentioned upper layer chip.
Detailed description of the invention
Fig. 1 is the constructed profile of the semiconductor device of embodiment.
Fig. 2 is the constructed profile of the semiconductor device of embodiment.
(a) of Fig. 3 and (b) be embodiment semiconductor device constructed profile.
Fig. 4 is the constructed profile of the semiconductor device of embodiment.
(a) of Fig. 5 and (b) be embodiment semiconductor device constructed profile.
(a) of Fig. 6~(c) is the constructed profile for indicating the manufacturing method of semiconductor device of embodiment.
(a) of Fig. 7~(c) is the constructed profile for indicating the manufacturing method of semiconductor device of embodiment.
(a) of Fig. 8~(c) is the constructed profile for indicating the manufacturing method of semiconductor device of embodiment.
Fig. 9 is the constructed profile for indicating the manufacturing method of semiconductor device of embodiment.
Figure 10 is the constructed profile for indicating the manufacturing method of semiconductor device of embodiment.
Figure 11 is the constructed profile for indicating the manufacturing method of semiconductor device of embodiment.
Figure 12 is the constructed profile for indicating the manufacturing method of semiconductor device of embodiment.
Figure 13 is the constructed profile for indicating the manufacturing method of semiconductor device of embodiment.
Figure 14 is the constructed profile for indicating the manufacturing method of semiconductor device of embodiment.
(a) of Figure 15 and (b) be multiple chips in the semiconductor device for indicate embodiment connection relationship signal Figure.
Figure 16 is the constructed profile of the semiconductor device of embodiment.
(a) of Figure 17 and (b) be embodiment semiconductor device constructed profile.
Specific embodiment
Hereinafter, being explained with reference to embodiment.In addition, assigning identical label to identical element in each attached drawing.
Fig. 1 is the constructed profile of the semiconductor device of embodiment.
The semiconductor device of embodiment has upper layer chip and the wiring for connecting upper layer chip with external circuit Formations.Upper layer chip includes such as memory chip.
In the example depicted in figure 1, upper layer chip has 1 memory chip 11.Memory chip 11 has semiconductor Layer 12.
Semiconductor layer 12 is such as silicon substrate.Alternatively, semiconductor layer 12 is SOI (Silicon On Insulator: insulation Silicon on body) construction in silicon layer.In addition, semiconductor layer 12 is also possible to the layer such as SiC, GaN (substrate) other than silicon.With Under explanation in, semiconductor layer 12 is set as silicon substrate and is illustrated.
Silicon substrate 12 has the 2nd face 12b of the 1st face (circuit face) 12a and its opposite side.It is formed in the 1st face 12a and includes The semiconductor integrated circuit of transistor (not shown) etc..Charge accumulation layer, coordination electrode etc. are formed on the 1st face 12a.This Outside, on the 1st face 12a, equipped on piece (on chip) wiring layer 13 being connect with semiconductor integrated circuit, coordination electrode.
For example, Fig. 3 as be described hereinafter (b) shown in, between on piece wiring layer 13 and the 1st face 12a, on piece wiring layer 13 that Between this and on the on piece wiring layer 13 of top layer, it is equipped with interlayer insulating film 14.
Interlayer insulating film 14 is using silicon as the insulating film constituted substantially, for example, including silica (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon-carbon nitrogen (SiCN), at least a certain in silicon oxide carbide (SiOC).
The 1st resin layer 30 is equipped in the 1st face side 12a of memory chip 11.1st resin layer 30 is with by memory chip 11 On piece wiring layer 13 surface covering mode be arranged.
In the 1st resin layer 30 and the surface side of the 1st resin layer 30, it is equipped with the 1st wiring layer 32.1st wiring layer 32 will The perforation of 1st resin layer 30, and connect with the on piece wiring layer 13 of memory chip 11.Thus, the 1st wiring layer 32 and storage core Piece 11 is electrically connected.1st resin layer 30 will insulate between the 1st wiring layer 32.1st wiring portion includes the 1st resin layer 30 and the 1st wiring layer 32。
1st resin layer 30 and the 1st wiring layer 32 are located at the region opposed with the 1st face 12a of memory chip 11, and not It is formed in chip exterior domain (than the side region in the outer part of memory chip 11).1st wiring layer 32 is be overlapped with chip Region in by winding so-called fan-in (fan-in；Japanese: Off ァ Application イ Application) wiring layer (RDL:Redistribution again Layer)。
The 2nd resin layer 41 is equipped in the surface side of the 1st resin layer 30.2nd resin layer 41 is from the 1st with memory chip 11 Face 12a opposed region rises, expands to the side chip exterior domain in the outer part than memory chip 11 and formed.
In the 2nd resin layer 41 and the surface side of the 2nd resin layer 41 is equipped with the 2nd wiring layer 42.2nd wiring layer 42 and 1 wiring layer 32 connects and expands to chip exterior domain and formed.2nd wiring layer 42 is so-called to be fanned out to (fan-out；Japanese: Off ァ Application ア ウ ト) wiring layer (RDL:Redistribution Layer) again.2nd resin layer 41 will be exhausted between the 2nd wiring layer 42 Edge.2nd wiring portion includes the 2nd resin layer 41 and the 2nd wiring layer 42.
1st wiring layer 32 and the 2nd wiring layer 42 are for example constituted by containing copper as the metal material of principal component.
1st resin layer 30 and the 2nd resin layer 41 are mainly by being that the high-molecular organic material constituted substantially is constituted with carbon, example It such as include polyimide resin, PBO (polybenzoxazoles: polybenzoxazole) resin, epoxy resin, silicone resin, BCB (benzene And cyclobutane: benzocyclobutene) resin is as principal component.
Multiple external terminals 52 are configured in the surface side of the 2nd resin layer 41.External terminal 52 is, for example, solder ball, metal The electric conductivity salient point such as salient point.External terminal 52 is connect with the 2nd wiring layer 42.
The semiconductor integrated circuit that is formed in memory chip 11, memory component are via on piece wiring layer 13 and the 1st Wiring layer 32 and be electrically connected with the 2nd wiring layer 42.Also, via the external terminal 52 being connect with the 2nd wiring layer 42, storage core Piece 11 can be connect with external circuit.
The side of memory chip 11 and the 2nd face (upper surface) 12b are covered by sealing resin 80.Sealing resin 80 is extending To on the 2nd resin layer 41 of chip exterior domain, the side of memory chip 11 and the side of the 1st resin layer 30 are covered.
In addition, other than memory chip 11, having logic chip 70 as lower layer chip according to embodiment.It patrols Collect the surface (opposite side in the face connecting on piece wiring layer 13 that chip (logic chip) 70 is installed in the 1st resin layer 30 Face) side, connect with the 1st wiring layer 32.That is, a face in the 1st resin layer 30 is equipped with the memory as upper layer chip Chip 11 is equipped with the logic chip 70 as lower layer chip in another face of the 1st resin layer 30.Here, " upper layer " " under Layer " indicates the opposite positional relationship for clamping the 1st resin layer 30, rather than indicates the upper and lower meaning for being directed to gravity direction.
Logic chip 70 is IF (interface, the interface)/controller chip for controlling memory chip 11.
It is equipped on piece wiring layer 71 in a face of logic chip 70, the on piece wiring layer 71 is via electric conductivity salient point (example Such as solder ball, metal salient point) 72 and engaged with the welding section 32a of the 1st wiring layer 32.
2nd resin layer 41 is not formed in the entire surface of the 1st resin layer 30.In the 1st resin layer 30 and memory chip , there is the region (opening portion) for not forming the 2nd resin layer 41 and the 2nd wiring layer 42 in the surface side of the opposite side in the face of 11 connections, The region (opening portion) is configured with logic chip 70.In the opening portion, by the welding section 32a of salient point 72 and the 1st wiring layer 32 Between joint portion covering mode be filled with sealing resin 73.
Multiple welding section 32a of 1st wiring layer 32, with the joint portion between on piece wiring layer 13 and the 1st wiring layer 32 The roughly the same spacing of spacing, be configured in the mounting surface of the logic chip 70 in the 1st resin layer 30.
The minimum spacing of interconnecting piece between logic chip 70 and the welding section 32a of the 1st wiring layer 32 is (between salient point 72 Away from) less than the minimum spacing of the interconnecting piece between the outside weldings area 42a and external terminal 52 of the 2nd wiring layer 42.In addition, logic The minimum spacing of interconnecting piece between chip 70 and the 1st wiring layer 32 is less than the company between the 1st wiring layer 32 and the 2nd wiring layer 42 The minimum spacing of socket part.
1st wiring layer 32 includes the fine wiring of the on piece wiring layer 13,71 with memory chip 11 and logic chip 70 Design corresponding thin space welding section；And it (is routed with the 2nd with the welding section that the spacing of external terminal 52 is correspondingly arranged Joint portion between layer 42).
That is, the fine pitch electrode pad of the chip-scale of memory chip 11 and logic chip 70 is via the 1st wiring layer 32 and the 2nd wiring layer 42, is expanded to the spacing for being suitable for being installed to printed wiring board etc..
Logic chip 70 is configured in the region of the underface of memory chip 11, via the 1st wiring layer 32 to memory The connection of 11 salient point of chip.In addition, logic chip 70 is electric with external terminal 52 via the 1st wiring layer 32 and the 2nd wiring layer 42 Connection.The 2nd wiring layer 42 in the same face of the 1st resin layer 30, equipped with logic chip 70 and for being connect with outside.
It is not to clamp logic core between printed circuit board (plug-in type (interposer) substrate) and memory chip The construction of piece.Thus, when logic chip 70 is connected to memory chip 11 and this both sides of external circuit, can not use TSV (through electrode).Thus, according to embodiment, it is capable of providing the semiconductor device of low cost and high reliablity.
Fig. 2 is the constructed profile for indicating other of semiconductor device of embodiment.
In the example shown in Fig. 2, memory chip portion has the laminated body of multiple memory chips 11.It is illustrated in Fig. 2 Will such as 4 11 layered configurations of memory chip, but the stacking number of memory chip 11 is arbitrary.Multiple storage cores Piece 11 is the identical chips such as thickness, planar dimension, the layer construction of thickness direction and material.
In the 1st face 12a of each memory chip 11, on piece wiring layer 13 is provided likewise with above embodiment.
Each memory chip 11 is electrically connected via through electrode 18 and salient point (such as solder ball, metal salient point) 31 each other It connects.
Through electrode 18 penetrates through silicon substrate 12, by the on piece wiring layer 13 for being formed in the 1st face 12a and is formed in the 2nd face The rear electrode of 12b connects.
Memory chip 11 other than (undermost) memory chip 11 near 30 side of resin layer, makes its on piece Wiring layer 13 is opposed with the 2nd face 12b of the memory chip 11 of lower section and is laminated on the memory chip 11 of lower section.
Memory chip of the salient point 31 between rear electrode (through electrode 18) and top of the memory chip 11 of lower section Between 11 on piece wiring layer 13, and the piece with the rear electrode of the memory chip of lower section 11 and the memory chip 11 of top Upper wiring layer 13 engages.
It is filled with sealing resin 85 between memory chip 11 and memory chip 11, sealing resin 85 is by the week of salient point 31 Side covering.
Metal plate 82 is equipped on memory chip 11 farthest, top layer away from resin layer 30.As described later, golden Belong to plate 82 to use as supporter when multiple 11 and the 1st resin layers 30 of memory chip are laminated.Finally, metal plate 82 can To remove.In addition, metal plate 82 is functioned as heat sink in the case where retaining metal plate 82.
In 13 side of on piece wiring layer of undermost memory chip 11, the 1st is provided likewise with above-mentioned embodiment Resin layer 30, the 1st wiring layer 32, the 2nd resin layer 41, the 2nd wiring layer 42, logic chip 70 and external terminal 52.
The semiconductor integrated circuit that is formed in each memory chip 11, memory component are via on piece wiring layer 13, the 1st cloth Line layer 32 and be electrically connected with the 2nd wiring layer 42.Also, via the external terminal 52 being connect with the 2nd wiring layer 42, each storage core Piece 11 can be connect with external circuit.
The side and upper surface of the laminated body of multiple memory chips 11 are covered by sealing resin 80.In addition, metal plate 82 Also it is covered by sealing resin 80.
In the configuration in figure 2, memory chip 11 and the fine pitch electrode pad of the chip-scale in logic chip 70 Also via the 1st wiring layer 32 and the 2nd wiring layer 42, it is expanded to the spacing for being suitable for being installed to printed wiring board etc..
In addition, logic chip 70 is configured in the region of the underface of the laminated body of memory chip 11, relative to storage The laminated body of device chip 11 is connected via the 1st wiring layer 32 by salient point.In addition, logic chip 70 via the 1st wiring layer 32 and 2nd wiring layer 42 and be electrically connected with external terminal 52.In the same face of the 1st resin layer 30, be equipped with logic chip 70 and for 2nd wiring layer 42 of external connection.
Thus, in the configuration in figure 2, it connect logic chip 70 and memory chip 11 and external circuit this both sides When, TSV (through electrode) can also not used.Therefore, it is capable of providing the semiconductor device of low cost and high reliablity.
(a) of Fig. 3 is other the another constructed profile for indicating the semiconductor device of embodiment.
In the example shown in (a) of Fig. 3, memory chip portion also has the laminated body of multiple memory chips 11.This Outside, multiple 2 die-stacks 10 are laminated with, 2 die-stacks 10 by by the circuit face 12a of 2 memory chips 11 that This is opposed Face to face and is bonded and constitutes.
1 pair of memory chip 11 in 2 die-stacks 10 is bonded (wafer to by wafer to wafer as described later Wafer bonding) it engages.Multiple 2 die-stacks 10 carry out salient point connection each other.
(b) of Fig. 3 is the amplification constructed profile in the portion A in Fig. 3 (a), indicates that the mian part of 2 die-stacks 10 is cutd open Face.
Each memory chip 11 has silicon substrate (semiconductor layer) 12, on piece wiring layer 13, through electrode 18 and engagement Metal (target) 21.
Circuit face 12a is equipped with the on piece wiring layer 13 connecting with semiconductor integrated circuit, coordination electrode.In (b) of Fig. 3 Multilayer wiring is instantiated, but on piece wiring layer 13 is also possible to single layer.Between on piece wiring layer 13 and circuit face 12a, on piece Interlayer insulating film 14 is equipped between wiring layer 13 and on the on piece wiring layer 13 of top layer.
The surface of interlayer insulating film 14 is equipped with resin layer 15.Resin layer 15 is such as benzocyclobutene (BCB) resin.Or Person, resin layer 15 are polyimide resin or epoxy resin.
Silicon substrate 12 is equipped with through electrode 18.Also, rear electrode 19 is equipped in the back side 12b of silicon substrate 12.Perforation electricity Pole 18 penetrates through silicon substrate 12 in the position for foring rear electrode 19, and rear electrode 19 and on piece wiring layer 13 are connected.It passes through Energization pole 18 is for example made of the metal for comprising copper as principal component.
Between through electrode 18 and silicon substrate 12, equipped with the insulation for preventing through electrode 18 and silicon substrate 12 to be directly connected Film 17.Insulating film 17 is, for example, silicon oxide layer, silicon nitride film or silicon nitrogen oxidation film.
Embedment has jointing metal (or target) 21 in resin layer 15.Jointing metal 21 is exhausted by resin layer 15 and interlayer A part perforation of edge layer 14, connect on piece wiring layer 13.Metal of the jointing metal 21 for example by comprising copper as principal component It constitutes.
Such memory chip 11 makes circuit face 12a (on piece wiring layer 13) opposed each other and engages, and forms 2 chips Laminated body 10.The jointing metal 21 of mutual memory chip 11 is engaged each other, and resin layer 15 is engaged (glue each other It connects).
In (a) of Fig. 3, in the stacking direction in 2 group of 2 adjacent die-stacks 10,2 die-stacks 10 of lower section Upside memory chip 11 rear electrode 19 and 2 die-stacks 10 above it downside memory chip 11 Salient point 31 is equipped between rear electrode 19.Salient point 31 is, for example, solder ball or metal salient point, by upper and lower memory chip 11 Rear electrode 19 is connected to each other.
In the back side side 12b of the memory chip 11 of the downside of undermost 2 die-stacks 10, with above-mentioned embodiment party Formula is provided likewise with the 1st resin layer 30, the 1st wiring layer 32, the 2nd resin layer 41, the 2nd wiring layer 42, logic chip 70 and outer Portion's terminal 52.
The semiconductor integrated circuit that is formed in each memory chip 11, memory component are via on piece wiring layer 13, the 1st cloth Line layer 32 and be electrically connected with the 2nd wiring layer 42.Also, via the external terminal 52 being connect with the 2nd wiring layer 42, each storage core Piece 11 can be connect with external circuit.
The side and upper surface of the laminated body of multiple memory chips 11 are covered by sealing resin 80.In addition, metal plate 82 are also covered by sealing resin 80.
In the construction of (a) of Fig. 3, the fine pitch electrode of memory chip 11 and the chip-scale in logic chip 70 Pad is also expanded to the spacing for being suitable for being installed to printed wiring board etc. via the 1st wiring layer 32 and the 2nd wiring layer 42.
In addition, logic chip 70 is configured in the region of the underface of the laminated body of memory chip 11, relative to storage The laminated body of device chip 11 is connected via the 1st wiring layer 32 by salient point.In addition, logic chip 70 via the 1st wiring layer 32 with And the 2nd wiring layer 42 and be electrically connected with external terminal 52.In the same face of the 1st resin layer 30, equipped with logic chip 70 and it is used for The 2nd wiring layer 42 being connect with outside.
Thus, in the construction of (a) of Fig. 3, making logic chip 70 and memory chip 11 and external circuit, this is double When side's connection, TSV (through electrode) can also not used.Therefore, it is capable of providing the semiconductor device of low cost and high reliablity.
Then, referring to Fig. 9~Figure 14, illustrate the manufacturing method of 2 die-stacks 10.Process shown in Fig. 9~Figure 14 exists It is carried out under chip (wafer) state, a part of section of wafer W 1, W2 is shown in Fig. 9~Figure 14.
Firstly, in wafer technique, formed on silicon substrate 12 above-mentioned element (semiconductor integrated circuit, memory component, On piece wiring layer 13, interlayer insulating film 14, resin layer 15, jointing metal 21).Then, make the circuit face 12a of 2 pieces of wafer Ws 1, W2 Side is opposed and is bonded.
The 1st wafer W 1 and the 2nd wafer W 2 in Fig. 9, before showing fitting.1st wafer W 1 and the 2nd wafer W 2 construct it is identical, And by binding face clamping and each element become mirror symmetry.
Mutual corresponding jointing metal 21 is aligned and is bonded as shown in Figure 10 by the 1st wafer W 1 and the 2nd wafer W 2. Under pressurization and heating, 2 pieces of wafer Ws 1, W2 are bonded, and jointing metal 21 is engaged each other and resin layer 15 is glued each other It connects.
After bonding chip, as shown in figure 11, the silicon substrate 12 of the 1st wafer W 1 is ground from the back side side 12b and keeps its thinning. Even if the silicon substrate 12 of the 1st wafer W 1 is thinning, the silicon substrate 12 of the 2nd wafer W 2 is also used as supporter.Alternatively, the 1st can also be made The silicon substrate 12 of wafer W 1 first grinds the silicon substrate 12 of the 2nd wafer W 2 so that its is thinning as supporter.
Silicon substrate 12 before grinding is such as 700 μm or more, by grinding, the silicon substrate in the case where forming through electrode It is such as 30~50 μm or so that 12, which are thinned, is thinned in the case where not forming through electrode as such as 100~500 μm of left sides It is right.
After the silicon substrate 12 to the 1st wafer W 1 has carried out thinning, as shown in figure 11, silicon substrate 12 is penetrated through and is arrived by formation Up to the through-hole 16 of the wiring layer 13 of the 1st wafer W 1.For example, passing through RIE (Reactive Ion Etching, reactive ion etching) Through-hole 16 is formed Deng etching.
As shown in figure 12, the back side 12b of the silicon substrate 12 around the inner wall of through-hole 16 and through-hole 16 forms insulating film 17.Also, through electrode 18 is embedded into through-hole 16 across insulating film 17.In addition, being formed and being passed through in the back side 12b of silicon substrate 12 The rear electrode 19 that energization pole 18 connects.Overleaf insulating film 17 is also clipped between electrode 19 and the back side 12b of silicon substrate 12.
Then, as shown in figure 13, viscous to the back side side 12b of the silicon substrate 12 for the 1st wafer W 1 for being formed with through electrode 18 Paste supporter 100.In Figure 13, will be inverted upside down compared with Figure 12 to indicate the 1st wafer W 1 and the 2nd wafer W 2.
Supporter 100 is the rigid body such as glass substrate.Supporter 100 is adhered to the 1st chip via adhesive layer 101 The silicon substrate 12 of W1.
In the state of supporting the 1st wafer W 1 and the 2nd wafer W 2 by supporter 100, by the silicon substrate of the 2nd wafer W 2 12 grind from the back side side 12b and keep its thinning.
After the silicon substrate 12 to the 2nd wafer W 2 has carried out thinning, in the same manner as the technique to the 1st wafer W 1, being formed will Silicon substrate 12 penetrates through and reaches the through-hole of the wiring layer 13 of the 2nd wafer W 2.
Also, as shown in figure 14, the back of the silicon substrate 12 around the inner wall and through-hole 16 of the through-hole 16 of the 2nd wafer W 2 Face 12b forms insulating film 17.In addition, being embedded to through electrode 18 into through-hole 16 across insulating film 17.In addition, in silicon substrate 12 Back side 12b forms the rear electrode 19 connecting with through electrode 18.Overleaf between electrode 19 and the back side 12b of silicon substrate 12 Clip insulating film 17.In addition, as needed, overleaf forming salient point 31 on electrode 19.
Later, the conjugant of the 1st wafer W 1 and the 2nd wafer W 2 is cut, supporter 100 is removed into (removing), thus Obtain 2 die-stacks 10 of singualtion.
For example, being secured at the state in cutting belt with supporter 100, the 2nd wafer W 2 and the 1st wafer W 1 are cut. Alternatively, the 1st wafer W 1 and the 2nd wafer W 2 can also be cut after removing supporter 100.
2 die-stacks 10 of embodiment are not the chips of 2 chips of singualtion to chip bonding (chip to chip Bonding), but as chip to obtained from the cutting after bonding chip.Thus, 2 die-stacks 10 are formed to have The rectangular shape of continuous side.
Multiple 2 die-stacks 10 of singualtion are laminated in as described above on metal plate 82, in multiple 2 chip laminates Sealing resin 80 is filled between body 10.
Alternatively, multiple 2 die-stacks 10 can also be bonded via the resin bonding layer being pre-formed on the surface And it is laminated.
In TSV structure, the surface area of through electrode becomes smaller if keeping substrate thin, can reduce by insulating film clamping and it is right The parasitic capacitance between through electrode and substrate set.But if substrate thinner, generate in the mutual bonding of chip, chip The problem of processing becomes difficult in packaging technologies such as it is bonded with installation base plate.
Therefore, embodiment from the description above is carried out keeping the side circuit face 12a of 2 pieces of wafer Ws 1, W2 opposed After chip is to bonding chip, the silicon substrate 12 of the wafer W 2 of a side is regard as supporter, by the silicon substrate of the wafer W 1 of another party 12 thinnings and form through electrode 18.Later, supporter (rigid body) 100 has been pasted in 12 side of silicon substrate of the wafer W 1 of a side Afterwards, by 12 thinning of silicon substrate of the wafer W of another party 2, and through electrode 18 is also formed to wafer W 2.
Therefore, the difficulty of processing can not be brought by the basis of respective 12 thinning of substrate of 2 die-stacks 10 Upper formation TSV structure.As reference example, compared with it will be constructed made of 2 chip laminates in such a way that chip is to chip, according to reality 2 die-stacks 10 for applying mode, can make substrate 12 with a thickness of about 1/2.
Thus, compared with reference example, the table for clamping insulating film 17 and the through electrode 18 opposed with silicon substrate 12 can be made Area is about 1/2, the parasitic capacitance between through electrode 18 and substrate 12 can be reduced to about 1/2.
In particular, if the stacking number of memory chip 11 increases with the high capacity of storage capacitance, the quantity of TSV Also increase, there are the tendencies that the influence of its parasitic capacitance also becomes larger, but according to embodiment, by the thinning of substrate 12 by TSV Parasitic capacitance reduce, so as to realize the reduction of power consumption.
In addition, 2 die-stacks 10 are will to clamp joint surface and profile construction is in mirror symmetry, identical memory Construction obtained from chip 11 bonds together, therefore the warpage that each memory chip 11 occurs is cancelled, as 2 chip laminates Body 10 can obtain small warpage.
Fig. 4 is other the another constructed profile for indicating the semiconductor device of embodiment.
It is different from the construction of Fig. 1 on this point of 41 covering logic chip 70 of the 2nd resin layer in the construction of Fig. 4.
The upper surface (face of the opposite side of on piece wiring layer 71) of logic chip 70 is covered by the 2nd resin layer 41.It will patrol Collect the outside weldings area 42a that the 2nd wiring layer 42 also is provided in the 2nd resin layer 41 of the upper surface covering of chip 70.To outside this Welding section 42a is bonded to external terminal 52.That is, being mounted with that the region of logic chip 70 is also configured with external terminal 52.
By extending the region of configurable external terminal 52, the spacing that can be realized between external terminal 52 expands, reliably Ground prevents short circuit between terminal, and installation improves.
It (a) of Fig. 5 and is (b) other the another constructed profile for indicating the semiconductor device of embodiment.Fig. 5's (b) be the portion B in Fig. 5 (a) amplification constructed profile.1st resin layer 30, the 1st wiring layer 32, the 2nd resin layer the 41, the 2nd The composition of wiring layer 42 etc. is identical as above-mentioned embodiment.
Semiconductor device shown according to (a) of Fig. 5 and (b), logic chip 70 is such as SoC (System on a Chip: system on chip) construction large-scale multi-pipe pin chip, a part of logic chip 70 when looking down with the 2nd resin layer 41 and The overlapping of 2nd wiring layer 42.That is, compared with the area of the installation region (opening portion of the 2nd resin layer 41) of logic chip 70, logic The planar dimension of chip 70 is bigger.Sealing resin 73 is clipped between logic chip 70 and the 2nd resin layer 41.
(a) of Fig. 2, Fig. 3, (a) of Fig. 5 and (b) shown in embodiment, multiple memory chips 11 are such as Figure 15 (a) shown in, (bus connection) is connected in parallel to common data input and output terminal 90.That is, by through electrode and salient point etc., To the common data/address bus 91 being formed on chip laminate direction, multiple chips 11 are connected in parallel.
In addition, as shown in (b) of Figure 15, the bus 93 to the terminal 92 for being connected to logic chip 70, by multiple memories Chip 11 is connected in parallel.
Then, the manufacturing method of the semiconductor device of embodiment is illustrated referring to (c) of (a) of Fig. 6~Fig. 8.Fig. 6's (a) in~Fig. 8 (c), the laminated body of multiple memory chips 11 is illustrated as memory chip portion, but can also there was only 1 A memory chip 11.
Multiple memory chips 11 are laminated on metal plate 82.In multiple memory chips 11 on metal plate 82 On the memory chip 11 of top layer, the 1st resin layer 30 and the 1st wiring layer 32 are formed.
Laminated body comprising these metal plates 82, multiple memory chips 11, the 1st resin layer 30 and the 1st wiring layer 32 100 is such as (a) of Fig. 6 and (b) shown, is mounted on supporter 95.Multiple laminated bodies 100 are mounted in supporter separated from each other On 95.It is mounted in the 1st resin layer 30 laminated body 100 on supporter 95 (towards 95 side of supporter) downward.
Then, it as shown in (c) of Fig. 6, after the laminated body 100 on supporter 95 is molded with resin 80, will support Body 95 removes.
Then, as shown in (a) of Fig. 7, on the 1st resin layer 30 and chip exterior domain is (between adjacent laminated body 100 Region) resin 80 on form the 2nd resin layer 41 and the 2nd wiring layer 42.In addition, in the 2nd resin of chip area just above Layer 41 forms opening portion 41a, makes the welding section 32a (as shown in Figure 1) of the 1st resin layer 30 and the 1st wiring layer 32 from the opening Portion 41a exposes.
Also, on the 1st resin layer 30 of opening portion 41a, as shown in (b) of Fig. 7, logic chip 70 is installed.Logic core Piece 70 is engaged via salient point 72 shown in FIG. 1 with the welding section 32a of the 1st wiring layer 32.
After being mounted with logic chip 70, multiple external terminals 52 are formed on the 2nd resin layer 41.Multiple external terminals 52 Grid (grid) shape is for example configured on the 2nd resin layer 41.The outside weldings area 42a of external terminal 52 and the 2nd wiring layer 42 Engagement (as shown in Figure 1).
Later, the 2nd resin layer 41 in adjacent 100 regions of laminated body and sealing resin 80 are cut off, monolithic turns to Multiple semiconductor devices.
In addition, after the process of (c) of Fig. 6 and before forming the 2nd resin layer 41, it, can be in the 1st tree as shown in (a) of Fig. 8 Logic chip 70 is carried on rouge layer 30.
Later, as shown in (b) of Fig. 8, in a manner of covering logic chip 70, on the 1st resin layer 30 and outside chip The 2nd resin layer 41 is formed on the resin 80 in region (region between adjacent laminated body 100).
For the 2nd resin layer 41, through-hole is formed using such as laser, the 2nd wiring layer 42 is embedded to.
Later, as shown in (c) of Fig. 8, multiple external terminals 52 are formed on the 2nd resin layer 41.External terminal 52 also can Enough configurations are in the region Chong Die with logic chip 70.Thus, compared with being constructed shown in (c) of Fig. 7, multiple external terminals 52 Configurable region extension, the configuration freedom of external terminal 52 are got higher.
Later, the 2nd resin layer 41 in adjacent 100 regions of laminated body and sealing resin 80 are cut off, monolithic turns to Multiple semiconductor devices.
According to the semiconductor device of embodiment, multiple memory chips connect common data input and output terminal parallel connection It connects.In addition, multiple memory chips connect the bus parallel connection for being connected to logic chip.
In addition, foring the 2nd resin layer on the 1st resin layer according to the manufacturing method of the semiconductor device of embodiment Afterwards, the opening portion for exposing the 1st resin layer is formed in the 2nd resin layer, configures the 2nd chip portion in opening portion.In addition, according to reality The manufacturing method for applying the semiconductor device of mode, after being mounted with the 2nd chip portion on the 1st resin layer, to cover the 2nd chip portion Mode forms the 2nd resin layer on the 1st resin layer.
Figure 16 is other the another constructed profile for indicating the semiconductor device of embodiment.
The upper layer chip of embodiment shown in Figure 16 has multiple deposit in the same manner as embodiment for example shown in Fig. 2 The lit-par-lit structure of memory chip 11.In the section shown in Figure 16, upper layer chip warpage as the bow to raise upward.
For the face direction of upper layer chip, the 1st resin layer 30 has peripheral part 30b and central portion 30a.1st resin layer 30 Peripheral part 30b and the 2nd resin layer 41 the distance between bottom surface (shortest distance) less than the 1st resin layer 30 central portion 30a The distance between the bottom surface of 2nd resin layer 41 (shortest distance).
The 1st wiring layer 32 of outer region (the peripheral part 30b of the 1st resin layer 30) setting in the face direction of chip on upper layer Lower end, with the distance between the bottom surface of the 2nd resin layer 41 (shortest distance), less than the central area in the face direction of upper layer chip Domain (the central portion 30a of the 1st resin layer 30) setting the lower end of the 1st wiring layer 32 and the bottom surface of the 2nd resin layer 41 between away from From (shortest distance).
Peripheral part 30b including side comprising the 1st resin layer 30 is embedded in the 2nd resin layer 41, is covered by the 2nd resin layer 41 Lid.Therefore, the connection reliability (adhesion) between the 1st resin layer 30 and the 2nd resin layer 41 improves.
It is not limited to all being covered by the 2nd resin layer 41 for the side of the 1st resin layer 30.Even if the side of the 1st resin layer 30 The a part in face is covered by the 2nd resin layer 41, and connection reliability also improves.
Semiconductor device shown according to (a) of Figure 17 and (b), one of the side of the peripheral part 30b of the 1st resin layer 30 Divide and be embedded in the 2nd resin layer 41, is covered by the 2nd resin layer 41.
In the process of (b) of above-mentioned Fig. 6, upper layer chip is mounted to branch through not shown temporary adhesive layer On support body 95.At this point, the 1st resin layer 30 is pressed against temporary bond oxidant layer, and it is slightly recessed in temporary bond oxidant layer.If in resin Supporter 95 is removed after 80 be molded, then the 1st resin layer 30 is slightly prominent from resin 80.If the 2nd tree formed here Rouge layer 41, then at least part of the 1st resin layer 30 is embedded in the 2nd resin layer 41.
Embodiment as shown in figure 16 is such, can be reliable buried by the 1st resin layer 30 if making upper layer chip warpage Enter the 2nd resin layer 41.
Several embodiments of the invention are illustrated, but these embodiments are suggested as examples, and It is not intended to limit the range of invention.These new embodiments can be implemented in various other forms, and not depart from inventive concept In the range of, various omissions, replacements and changes can be made.These embodiments and modifications thereof are included in range and the master of invention In purport, and it is included in the range of the invention described in the claims and its equivalence.
Description of symbols
11 ... memory chips, 12 ... silicon substrates (semiconductor layer), 13 ... on piece wiring layers, 30 ... the 1st resin layers, 32 ... 1st wiring layer, 41 ... the 2nd resin layers, 42 ... the 2nd wiring layers, 52 ... external terminals, 70 ... logic chips.

Claims (13)

1. a kind of semiconductor device, has:
Upper layer chip, the 2nd face of the opposite side with the 1st face and above-mentioned 1st face；
Above-mentioned 1st face of above-mentioned upper layer chip is arranged in 1st resin layer；
1st wiring layer is arranged in above-mentioned 1st resin layer, is electrically connected with above-mentioned upper layer chip；
2nd resin layer, is arranged in the surface side of above-mentioned 1st resin layer, and expand to than above-mentioned upper layer chip side in the outer part Chip exterior domain；
2nd wiring layer is arranged in above-mentioned 2nd resin layer, connect with above-mentioned 1st wiring layer, and extend to said chip outskirt Domain；
Lower layer chip is mounted on the above-mentioned surface side of above-mentioned 1st resin layer, connect with above-mentioned 1st wiring layer；And
Sealing resin covers above-mentioned upper layer chip,
Above-mentioned 1st wiring layer that the outer region of above-mentioned upper layer chip is arranged lower end, with the bottom surface of above-mentioned 2nd resin layer it Between distance, less than above-mentioned upper layer chip middle section setting above-mentioned 1st wiring layer lower end, with above-mentioned 2nd resin The distance between the bottom surface of layer, the side of above-mentioned 1st resin layer is embedded in above-mentioned 2nd resin layer.
2. semiconductor device as described in claim 1,
Above-mentioned lower layer chip configuration is in the opening portion for being formed in above-mentioned 2nd resin layer.
3. semiconductor device as described in claim 1,
Above-mentioned 2nd resin layer covers above-mentioned lower layer chip.
4. semiconductor device as described in claim 1,
It is also equipped with the external terminal that the surface side of above-mentioned 2nd resin layer is set and is connect with above-mentioned 2nd wiring layer,
The minimum spacing of interconnecting piece between above-mentioned lower layer chip and above-mentioned 1st wiring layer is less than between the minimum of said external terminal Away from.
5. semiconductor device as claimed in claim 4,
The minimum spacing of interconnecting piece between above-mentioned lower layer chip and above-mentioned 1st wiring layer be less than above-mentioned 1st wiring layer with it is above-mentioned The minimum spacing of interconnecting piece between 2nd wiring layer.
6. semiconductor device as claimed in claim 4,
Above-mentioned 2nd resin layer covers above-mentioned lower layer chip,
Said external terminal is additionally arranged at the region that above-mentioned 2nd resin layer covers above-mentioned lower layer chip.
7. semiconductor device as described in claim 1,
Above-mentioned lower layer chip is Chong Die with above-mentioned 2nd wiring layer in vertical view.
8. semiconductor device as described in claim 1,
Above-mentioned upper layer chip includes memory chip, and above-mentioned lower layer chip includes logic chip.
9. semiconductor device as claimed in claim 8,
Above-mentioned upper layer chip has the laminated body of multiple above-mentioned memory chips.
10. semiconductor device as claimed in claim 9,
Above-mentioned multiple memory chips have the 1st chip and the 2nd chip,
Above-mentioned 1st chip includes
1st semiconductor layer, the 1st back side of the opposite side with the 1st circuit face and above-mentioned 1st circuit face；
1st on piece wiring layer is arranged in above-mentioned 1st circuit face；And
1st through electrode penetrates through above-mentioned 1st semiconductor layer and is arranged, and connect with above-mentioned 1st on piece wiring layer,
Above-mentioned 2nd chip laminate is in the above-mentioned 1st on piece wiring layer side of above-mentioned 1st chip, comprising:
2nd semiconductor layer has opposite with above-mentioned 1st on piece wiring layer opposed the 2nd circuit face and above-mentioned 2nd circuit face 2nd back side of side；
2nd on piece wiring layer is arranged in above-mentioned 2nd circuit face, connect with the above-mentioned 1st on piece wiring layer of above-mentioned 1st chip；With And
2nd through electrode penetrates through above-mentioned 2nd semiconductor layer and is arranged, connect with above-mentioned 2nd on piece wiring layer.
11. semiconductor device as claimed in claim 10,
Above-mentioned multiple memory chips also have the 3rd chip of above-mentioned 2nd back side for being layered in above-mentioned 2nd chip,
Above-mentioned 3rd chip includes
3rd semiconductor layer, with the 3rd circuit face and positioned at the opposite side of above-mentioned 3rd circuit face and opposed with above-mentioned 2nd chip 3rd back side；
3rd wiring layer is arranged in above-mentioned 3rd circuit face；And
3rd through electrode penetrates through above-mentioned 3rd semiconductor layer and is arranged, connect with above-mentioned 3rd wiring layer, and via salient point and It is connect with above-mentioned 2nd through electrode of above-mentioned 2nd chip.
12. the semiconductor device as described in any one of claim 1~11,
A part of at least peripheral part of above-mentioned 1st resin layer is covered by above-mentioned 2nd resin layer.
13. a kind of manufacturing method of semiconductor device, has following process:
In above-mentioned 1st face of the upper layer chip in the 2nd face with the 1st face and the opposite side in above-mentioned 1st face, the 1st resin layer of formation, With the process for the 1st wiring layer being electrically connected with above-mentioned upper layer chip being arranged in above-mentioned 1st resin layer；
The process that above-mentioned 2nd surface side of above-mentioned upper layer chip and side are covered with resin；
The above-mentioned resin of the chip exterior domain of side in the outer part on above-mentioned 1st resin layer and than above-mentioned upper layer chip On, it forms the 2nd resin layer and connecting with above-mentioned 1st wiring layer and extending to said chip in above-mentioned 2nd resin layer is set The process of 2nd wiring layer of exterior domain；And
The process that the lower layer chip connecting with above-mentioned 1st wiring layer is installed on above-mentioned 1st resin layer is forming the 2nd resin layer Process in, be formed as follows the 2nd resin layer: above-mentioned upper layer chip outer region be arranged above-mentioned 1st wiring layer Lower end, the distance between with the bottom surface of above-mentioned 2nd resin layer, it is above-mentioned less than the middle section setting in above-mentioned upper layer chip The distance between the lower end of 1st wiring layer and the bottom surface of above-mentioned 2nd resin layer, the side of above-mentioned 1st resin layer is embedded in State the 2nd resin layer.
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