CN104915180A - Data operation method and device - Google Patents
Data operation method and device Download PDFInfo
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- CN104915180A CN104915180A CN201410085731.0A CN201410085731A CN104915180A CN 104915180 A CN104915180 A CN 104915180A CN 201410085731 A CN201410085731 A CN 201410085731A CN 104915180 A CN104915180 A CN 104915180A
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Abstract
The embodiment of the invention provides a data operation method and device and relates to the field of communication. Whether a data reading instrument is a key instrument or not can be accurately judged, the data reading speed of a processer in an internal storage is increased, and the hardware cost is prevented from being excessively high. The method comprises the steps that it is determined that the first operation instruction is critical on a compiler, and after the first operation instruction is changed into a second operation instruction, an internal storage controller receives the second operation instruction; the internal storage controller determines that the second operation instruction is critical according to a critical instruction identifier carried by the second operation instruction, and operation is performed on data corresponding to the second operation instruction in the internal storage according to the preference strategy. The data operation method and device are used for performing operation on data of the internal storage.
Description
Technical field
The present invention relates to the communications field, particularly relate to a kind of method and apparatus of data manipulation.
Background technology
In the system of existing processor access internal memory, this processor correspondence at least level cache, then this processor is when sending data read command, first inquire about in the buffer, if when all can not find data corresponding to this data read command in every level cache, this data read command can be passed in Memory Controller Hub, carries out instruction scheduling by Memory Controller Hub, and the mode eventually through access memory reads data corresponding to this data read command.
Because the time delay of reading data in internal memory is longer, if this data read command is key instruction, that is, the execution of many follow-up instructions all depends on this data read command, then reduce the processing speed of this processor to whole process, therefore, in order to address this problem, judge whether this data read command is key instruction by increase detection module and prediction module in prior art, then this Memory Controller Hub preferentially processes the data read command being defined as key instruction, decrease the time delay that this processor reads data in internal memory.Wherein, this detection module is used for, instruction submit in queue delay longer data read command detected time, notify that this prediction module is inquired about this data read command and predicts; This prediction module is used for, and to inquire about and predict according to the historical information of preserving to this data read command.
But this detection module and this prediction module add the cost of hardware, and according to historical information, this prediction module predicts whether this data read command is that key instruction exists larger error.
Summary of the invention
The invention provides a kind of method and apparatus of data manipulation, can judge whether data read command is key instruction accurately, improve the speed that processor reads data in internal memory, and it is too high to avoid hardware cost.
For achieving the above object, the present invention adopts following technical scheme:
First aspect provides a kind of method of data manipulation, comprising:
Determine that the first operational order has at compiler key, and after described first operational order is changed to the second operational order, Memory Controller Hub receives described second operational order; Described second operational order carries key instruction mark;
According to described key instruction mark, described Memory Controller Hub determines that described second operational order is key instruction;
Operate according to the data of preference strategy to described second operational order corresponding in internal memory.
In the first possible implementation of first aspect, if described first operational order is data read command, then described second operational order of described Memory Controller Hub reception comprises:
When processor does not find the data of corresponding described first operational order in the buffer, receive described first operational order that described processor sends;
In conjunction with first aspect or the first possible implementation, in the implementation that the second is possible, if operational order to be called in described Memory Controller Hub is not key instruction, then describedly carries out operation according to the data of preference strategy to described second operational order corresponding in internal memory and comprise:
Preferentially call the data of described second operational order to described second operational order corresponding in internal memory to operate.
In conjunction with the implementation that the second is possible, in the implementation that the third is possible, described preferentially call described second operational order to internal memory in before the data of corresponding described second operational order operate, described method also comprises:
Operand according to operational order to be called in the operand of described second operational order and described Memory Controller Hub determines that operational order to be called in described Memory Controller Hub and described second operational order do not exist the relation of sequence.
Second aspect provides a kind of method of data manipulation, comprising:
Compiler carries out compiling to source code and obtains object code;
Determine whether the first operational order in described object code has key;
When determining that described first operational order has key, described first operational order is changed to the second operational order, wherein, described second operational order carries key instruction mark, so that Memory Controller Hub is when receiving described second operational order, determine that described second operational order is key instruction according to described key instruction mark, and operate according to the data of preference strategy to described second operational order corresponding in internal memory.
In the first possible implementation of second aspect, whether described the first operational order determined in described object code has key comprising:
When the operand of the operand of described first operational order and the follow-up operational order of described first operational order meets pre-conditioned, determine that described first operational order has key.
The third aspect provides a kind of Memory Controller Hub, comprising:
Receiving element, key for determining that at compiler the first operational order has, and after described first operational order is changed to the second operational order, receive described second operational order; Described second operational order carries key instruction mark;
According to described key instruction mark, determining unit, for determining that described second operational order is key instruction;
Processing unit, for operating according to the data of preference strategy to described second operational order corresponding in internal memory.
In the first possible implementation of the third aspect, described receiving element specifically for: if described first operational order is data read command, when processor does not find the data of corresponding described first operational order in the buffer, receive described first operational order that described processor sends;
In conjunction with the third aspect or the first possible implementation, in the implementation that the second is possible, described processing unit specifically for: if operational order to be called in described Memory Controller Hub is not key instruction, preferentially calls the data of described second operational order to described second operational order corresponding in internal memory and operate.
In conjunction with the implementation that the second is possible, in the implementation that the third is possible, described processing unit specifically for: preferentially call described second operational order to internal memory in before the data of corresponding described second operational order operate, the operand according to operational order to be called in the operand of described second operational order and described Memory Controller Hub determines that operational order to be called in described Memory Controller Hub and described second operational order do not exist the relation of sequence.
Fourth aspect provides a kind of compiler, comprising:
Processing unit, obtains object code for carrying out compiling to source code;
Determining unit, for determining whether the first operational order in described object code has key;
Described processing unit also for, when determining that described first operational order has key, described first operational order is changed to the second operational order, wherein, described second operational order carries key instruction mark, so that Memory Controller Hub is when receiving described second operational order, determine that described second operational order is key instruction according to described key instruction mark, and operate according to the data of preference strategy to described second operational order corresponding in internal memory.
In the first possible implementation of fourth aspect, described determining unit specifically for:
When the operand of the operand of described first operational order and the follow-up operational order of described first operational order meets pre-conditioned, determine that described first operational order has key.
Adopt such scheme, determine that the first operational order has at compiler key, and after this first operational order is changed to the second operational order, Memory Controller Hub receives this second operational order, the key instruction mark that this Memory Controller Hub carries according to this second operational order determines that this second operational order is key instruction, and according to preference strategy in internal memory to should the data of the second operational order operate.Like this, if this Memory Controller Hub receives data read command, whether can carry key instruction mark according to this data read command and determine whether this data read command is key instruction, and preferentially call the data that this data read command reads correspondence in internal memory, can judge whether data read command is key instruction accurately, improve processor in internal memory, read the speed of data, and avoid inquiry and predict the problem that the hardware cost that brings is too high.
Accompanying drawing explanation
The structural representation of the system of a kind of processor access internal memory that Fig. 1 provides for the embodiment of the present invention;
The schematic flow sheet of the method for a kind of data manipulation that Fig. 2 provides for the embodiment of the present invention;
The schematic diagram of a kind of Memory Controller Hub instruction queue that Fig. 3 provides for the embodiment of the present invention;
The schematic flow sheet of the method for the another kind of data manipulation that Fig. 4 provides for the embodiment of the present invention;
The structural representation of a kind of Memory Controller Hub that Fig. 5 provides for the embodiment of the present invention;
The structural representation of a kind of compiler that Fig. 6 provides for the embodiment of the present invention;
The structural representation of the another kind of Memory Controller Hub that Fig. 7 provides for the embodiment of the present invention;
The structural representation of the another kind of compiler that Fig. 8 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Following examples of the present invention can be applied to the system of processor access internal memory, this system as shown in Figure 1, comprise: compiler, processor, level cache, L2 cache, Memory Controller Hub and internal memory, its annexation as shown in Figure 1, described compiler, obtains executable program for source code is carried out compiling; Described processor, for performing the executable program that described compiler obtains; Described level cache, for fast cache data; Described L2 cache, for fast cache data; Described Memory Controller Hub is that inside computer system is controlled internal memory and made the important component part of the swapping data of internal memory and processor by Memory Controller Hub; Described internal memory, for storing data, its memory capacity is greater than buffer memory, but read and write access speed is less than the read or write speed of buffer memory.
The embodiment of the present invention provides a kind of method of data manipulation, as shown in Figure 2, comprising:
S201, to determine that the first operational order has at compiler key, and after this first operational order is changed to the second operational order, Memory Controller Hub receives this second operational order.
Wherein, this second operational order carries key instruction mark.
Particularly, compiler carries out compiling to source code and obtains object code, and the object code obtained is detected, detect to have critical first operational order, then this first operational order is changed to the second operational order carrying key instruction mark by this compiler.
Alternatively, this compiler, when the operand of the operand of this first operational order and the follow-up operational order of this first operational order meets pre-conditioned, determines that this first operational order has key.
Illustratively, source code is:
……
for（i=1；i<100;i++）
a[i]=a[0]+i;
……
The compiling of this compiler obtains object code:
……
LDR R2，[R1]；
ADD R3,R2,#1
STR R3,[R1,#1]
ADD R3,R2,#2
STR R3，[R1,#2]
……
ADD R3,R2,#99
STR R3，[R1,#99]
……
Further, this compiler is after obtaining above-mentioned object code, this object code is scanned, detect the relation of the operand of the operand of every bar operational order and the follow-up operational order of this operational order, when the operand of the operand of the first operational order and the follow-up operational order of this first operational order meets pre-conditioned, determine that this first operational order has key.Such as, this is pre-conditioned is greater than 5 for the operand occurrence number in the operand of subsequent operation instruction in this first operational order, then in above-mentioned object code, for the first operational order LDR R2, [R1], this first operational order represents and is saved in register R2 by the data reading at R1 address place, this compiler carries out scanning by the operational order follow-up to this first operational order can determine that the number of times that the operand R2 in this first operational order occurs in subsequent instructions is greater than 5, then this compiler determines that this first operational order has key.
From source code, perform the value that value that circulation obtains array a [1] to array a [99] all uses array a [0], the value in the register R2 in namely corresponding object code, therefore, if the unsuccessful execution of this first operational order, follow-up operational order all cannot perform.
Further, this first operational order, when determining that this first operational order has key, is changed to the second operational order by this compiler, as LDR_c R2, [R1], then the object code after change is:
……
LDR_c R2，[R1]
ADD R3,R2,#1
STR R3,[R1,#1]
ADD R3,R2,#2
STR R3，[R1,#2]
……
ADD R3,R2,#99
STR R3，[R1,#99]
……
It should be noted that, the above-mentioned pre-conditioned frequency that can also occur in the operand of subsequent operation instruction for the operand in this first operational order is greater than N, N be greater than zero positive integer, namely this compiler is after scanning object code, if determine, the frequency that the operand R2 of this first operational order occurs in subsequent operation instruction is greater than N, then this compiler determines that this first operational order has key.
Alternatively, if this first operational order is data read command, then processor do not find in the buffer to should the data of the first operational order time, this Memory Controller Hub receives this first operational order that this processor sends.
It should be noted that, the existence of this second operational order supported by this processor, and this processor is when processing this second operational order, the same with the processing mode of this first operational order.Even this first operational order is data read command, then this processor is when execution the second operational order, first inquire about in the buffer should the data of the second operational order, if exist should the data of the second operational order in buffer memory, then this processor reads this data; If when all can not find data corresponding to this second operational order in every level cache, then this second operational order is referred to be sent in Memory Controller Hub.
According to this key instruction mark, S202, this Memory Controller Hub determine that this second operational order is key instruction.
Particularly, this Memory Controller Hub is when receiving this second operational order, determine that this second operational order is key instruction according to the key instruction mark that this second operational order carries, wherein, this key instruction mark can be the title of the operational code of this second operational order, as above-mentioned LDR_c, also can be other identification informations that this instruction is carried, be used to indicate the key of this second operational order.
S203, this Memory Controller Hub according to preference strategy in internal memory to should the data of the second operational order operate.
Alternatively, if operational order to be called in this Memory Controller Hub is not key instruction, then this Memory Controller Hub preferentially call this second operational order in internal memory to should the data of the second operational order operate.
Alternatively, this preferentially call this second operational order to internal memory in should before the data of the second operational order operate, according to the operand of operational order to be called in the operand of this second operational order and this Memory Controller Hub, this Memory Controller Hub determines that operational order to be called in this Memory Controller Hub and this second operational order do not exist the relation of sequence.
It should be noted that, the relation of above-mentioned sequence refers to that first this Memory Controller Hub can only perform this operational order to be called, this second operational order of rear execution, such as:
STR R1，R2
LDR_c R3,R2
There is above-mentioned code known, can only after the data in register R1 write in register R2 by execution STR R1, R2, could perform LDR_c R3, R2 reads as register R3 from the data register R2, and therefore this STR and this LDR_c exists the relation of sequence.
Illustratively, this preference strategy is: if the instruction to be called in the instruction queue of this Memory Controller Hub is key instruction, then preferentially perform this instruction to be called; If the instruction to be called in the instruction queue of this Memory Controller Hub is not key instruction and instruction to be called and this second operational order exist the relation of sequence, then preferentially perform this instruction to be called; If the instruction to be called in the instruction queue of this Memory Controller Hub is not key instruction and instruction to be called and this second operational order do not exist the relation of sequence, then preferentially perform this second operational order.
As shown in Figure 3, in the instruction queue of this Memory Controller Hub, comprise operational order LDR_c, STR, LDR and the second operational order, then the order of this Memory Controller Hub executable operations instruction is followed successively by LDR_c, STR, the second operational order, LDR.Wherein, this LDR_c is key instruction and there is not the relation of sequence with this second operational order; There is the relation of sequence in this STR and this second operational order, such as, this second operational order is data read command, and the destination operand of this second operational order source operand corresponding with this STR is identical, that is, Memory Controller Hub is after execution STR instruction carries out write operation to a certain address, and perform the data that this second operational order reads same address, therefore this STR must perform before this second operational order; This LDR is not key instruction and there is not the relation of sequence with this second operational order.
Adopt said method, determine that the first operational order has at compiler key, and after this first operational order is changed to the second operational order, Memory Controller Hub receives this second operational order, the key instruction mark that this Memory Controller Hub carries according to this second operational order determines that this second operational order is key instruction, and according to preference strategy in internal memory to should the data of the second operational order operate.Like this, if this Memory Controller Hub receives data read command, whether can carry key instruction mark according to this data read command and determine whether this data read command is key instruction, and preferentially call the data that this data read command reads correspondence in internal memory, can judge whether data read command is key instruction accurately, improve processor in internal memory, read the speed of data, and avoid inquiry and predict the problem that the hardware cost that brings is too high.
The embodiment of the present invention provides a kind of method of data manipulation, as shown in Figure 4, comprising:
S401, compiler carry out compiling to source code and obtain object code.
S402, this compiler determine whether the first operational order in this object code has key.
Alternatively, this compiler, when the operand of the operand of this first operational order and the follow-up operational order of this first operational order meets pre-conditioned, determines that this first operational order has key.
Illustratively, source code is:
……
for（i=1；i<100;i++）
a[i]=a[0]+i;
……
The compiling of this compiler obtains object code:
……
LDR R2，[R1]；
ADD R3,R2,#1
STR R3,[R1,#1]
ADD R3,R2,#2
STR R3，[R1,#2]
……
ADD R3,R2,#99
STR R3，[R1,#99]
……
Further, this compiler is after obtaining above-mentioned object code, this object code is scanned, detect the relation of the operand of the operand of every bar operational order and the follow-up operational order of this operational order, when the operand of the operand of the first operational order and the follow-up operational order of this first operational order meets pre-conditioned, determine that this first operational order has key.Such as, this is pre-conditioned is greater than 5 for the operand occurrence number in the operand of subsequent operation instruction in this first operational order, then in above-mentioned object code, for the first operational order LDR R2, [R1], this first operational order represents and is saved in register R2 by the data reading at R1 address place, this compiler carries out scanning by the operational order follow-up to this first operational order can determine that the number of times that the operand R2 in this first operational order occurs in subsequent instructions is greater than 5, then this compiler determines that this first operational order has key.
From source code, perform the value that value that circulation obtains array a [1] to array a [99] all uses array a [0], the value in the register R2 in namely corresponding object code, therefore, if the unsuccessful execution of this first operational order, follow-up operational order all cannot perform.
It should be noted that, the above-mentioned pre-conditioned frequency that can also occur in the operand of subsequent operation instruction for the operand in this first operational order is greater than N, N be greater than zero positive integer, namely this compiler is after scanning object code, if determine, the frequency that the operand R2 of this first operational order occurs in subsequent operation instruction is greater than N, then this compiler determines that this first operational order has key.
This first operational order, when determining that this first operational order has key, is changed to the second operational order by S403, this compiler.
Wherein, this second operational order carries key instruction mark, so that Memory Controller Hub is when receiving this second operational order, determine that this second operational order is key instruction according to this key instruction mark, and according to preference strategy by this second operational order in internal memory to should the data of the second operational order operate.
Illustratively, this first operational order, when determining that this first operational order has key, is changed to the second operational order by this compiler, as by this first operational order LDR R2, [R1] changes to the second operational order LDR_c R2, [R1], then the object code after change is:
……
LDR_c R2，[R1]
ADD R3,R2,#1
STR R3,[R1,#1]
ADD R3,R2,#2
STR R3，[R1,#2]
……
ADD R3,R2,#99
STR R3，[R1,#99]
……
Alternatively, if this first operational order is data read command, then processor do not find in the buffer to should the data of the first operational order time, this Memory Controller Hub receives this first operational order that this processor sends.
It should be noted that, the existence of this second operational order supported by this processor, and this processor is when processing this second operational order, the same with the processing mode of this first operational order.Even this first operational order is data read command, then this processor is when execution the second operational order, first inquire about in the buffer should the data of the second operational order, if exist should the data of the second operational order in buffer memory, then this processor reads this data; If when all can not find data corresponding to this second operational order in every level cache, then this second operational order is referred to be sent in Memory Controller Hub.
This Memory Controller Hub is when receiving this second operational order, determine that this second operational order is key instruction according to the key instruction mark that this second operational order carries, wherein, this key instruction mark can be the title of the operational code of this second operational order, as above-mentioned LDR_c, also can be other identification informations that this instruction is carried, be used to indicate the key of this second operational order.
Adopt said method, compiler is after obtaining object code, determine that the first operational order has key, and this first operational order is changed to the second operational order, so that Memory Controller Hub is when receiving this second operational order, determine that this second operational order is key instruction, and according to preference strategy in internal memory to should the data of the second operational order operate.Like this, if this Memory Controller Hub receives data read command, whether can carry key instruction mark according to this data read command and determine whether this data read command is key instruction, and preferentially call the data that this data read command reads correspondence in internal memory, can judge whether data read command is key instruction accurately, improve processor in internal memory, read the speed of data, and avoid inquiry and predict the problem that the hardware cost that brings is too high.
The embodiment of the present invention provides a kind of Memory Controller Hub 50, as shown in Figure 5, comprising:
Receiving element 51, key for determining that at compiler the first operational order has, and after this first operational order is changed to the second operational order, receive this second operational order.
Wherein, this second operational order carries key instruction mark.
According to this key instruction mark, determining unit 52, for determining that this second operational order is key instruction.
Processing unit 53, for according to preference strategy in internal memory to should the data of the second operational order operate.
Particularly, compiler carries out compiling to source code and obtains object code, and the object code obtained is detected, detect to have critical first operational order, then this first operational order is changed to the second operational order carrying key instruction mark by this compiler.
Alternatively, this compiler, when the operand of the operand of this first operational order and the follow-up operational order of this first operational order meets pre-conditioned, determines that this first operational order has key.
Illustratively, source code is:
……
for（i=1；i<100;i++）
a[i]=a[0]+i;
……
The compiling of this compiler obtains object code:
……
LDR R2，[R1]；
ADD R3,R2,#1
STR R3,[R1,#1]
ADD R3,R2,#2
STR R3，[R1,#2]
……
ADD R3,R2,#99
STR R3，[R1,#99]
……
Further, this compiler is after obtaining above-mentioned object code, this object code is scanned, detect the relation of the operand of the operand of every bar operational order and the follow-up operational order of this operational order, when the operand of the operand of the first operational order and the follow-up operational order of this first operational order meets pre-conditioned, determine that this first operational order has key.Such as, this is pre-conditioned is greater than 5 for the operand occurrence number in the operand of subsequent operation instruction in this first operational order, then in above-mentioned object code, for the first operational order LDR R2, [R1], this first operational order represents and is saved in register R2 by the data reading at R1 address place, this compiler carries out scanning by the operational order follow-up to this first operational order can determine that the number of times that the operand R2 in this first operational order occurs in subsequent instructions is greater than 5, then this compiler determines that this first operational order has key.
From source code, perform the value that value that circulation obtains array a [1] to array a [99] all uses array a [0], the value in the register R2 in namely corresponding object code, therefore, if the unsuccessful execution of this first operational order, follow-up operational order all cannot perform.
Further, this first operational order, when determining that this first operational order has key, is changed to the second operational order by this compiler, as LDR_c R2, [R1], then the object code after change is:
……
LDR_c R2，[R1]
ADD R3,R2,#1
STR R3,[R1,#1]
ADD R3,R2,#2
STR R3，[R1,#2]
……
ADD R3,R2,#99
STR R3，[R1,#99]
……
It should be noted that, the above-mentioned pre-conditioned frequency that can also occur in the operand of subsequent operation instruction for the operand in this first operational order is greater than N, N be greater than zero positive integer, namely this compiler is after scanning object code, if determine, the frequency that the operand R2 of this first operational order occurs in subsequent operation instruction is greater than N, then this compiler determines that this first operational order has key.
Alternatively, this receiving element 51 specifically for, if this first operational order is data read command, processor do not find in the buffer to should the data of the first operational order time, receive this first operational order that this processor sends.
It should be noted that, the existence of this second operational order supported by this processor, and this processor is when processing this second operational order, the same with the processing mode of this first operational order.Even this first operational order is data read command, then this processor is when execution the second operational order, first inquire about in the buffer should the data of the second operational order, if exist should the data of the second operational order in buffer memory, then this processor reads this data; If when all can not find data corresponding to this second operational order in every level cache, then this second operational order is referred to be sent in Memory Controller Hub.
Further, this Memory Controller Hub is when receiving this second operational order, determine that this second operational order is key instruction according to the key instruction mark that this second operational order carries, wherein, this key instruction mark can be the title of the operational code of this second operational order, as above-mentioned LDR_c, also can be other identification informations that this instruction is carried, be used to indicate the key of this second operational order.
Alternatively, this processing unit 53 specifically for, if operational order to be called in this Memory Controller Hub is not key instruction, preferentially call this second operational order in internal memory to should the data of the second operational order operate.
Alternatively, this processing unit 53 also for, preferentially call this second operational order to internal memory in should before the data of the second operational order operate, the operand according to operational order to be called in the operand of this second operational order and this Memory Controller Hub determines that operational order to be called in this Memory Controller Hub and this second operational order do not exist the relation of sequence.
It should be noted that, the relation of above-mentioned sequence refers to that first this Memory Controller Hub can only perform this operational order to be called, this second operational order of rear execution, such as:
STR R1，R2
LDR_c R3,R2
There is above-mentioned code known, can only after the data in register R1 write in register R2 by execution STR R1, R2, could perform LDR_c R3, R2 reads as register R3 from the data register R2, and therefore this STR and this LDR_c exists the relation of sequence.
Illustratively, this preference strategy is: if the instruction to be called in the instruction queue of this Memory Controller Hub is key instruction, then preferentially perform this instruction to be called; If the instruction to be called in the instruction queue of this Memory Controller Hub is not key instruction and instruction to be called and this second operational order exist the relation of sequence, then preferentially perform this instruction to be called; If the instruction to be called in the instruction queue of this Memory Controller Hub is not key instruction and instruction to be called and this second operational order do not exist the relation of sequence, then preferentially perform this second operational order.
Those skilled in the art can be well understood to, for convenience and simplicity of description, only be illustrated with the division of above-mentioned each functional module, in practical application, can distribute as required and by above-mentioned functions and be completed by different functional modules, inner structure by device is divided into different functional modules, to complete all or part of function described above.The specific works process of the unit of foregoing description, with reference to the corresponding process in preceding method embodiment, can not repeat them here.
Adopt above-mentioned Memory Controller Hub, determine that the first operational order has at compiler key, and after this first operational order is changed to the second operational order, this Memory Controller Hub receives this second operational order, the key instruction mark that this Memory Controller Hub carries according to this second operational order determines that this second operational order is key instruction, and according to preference strategy in internal memory to should the data of the second operational order operate.Like this, if this Memory Controller Hub receives data read command, whether can carry key instruction mark according to this data read command and determine whether this data read command is key instruction, and preferentially call the data that this data read command reads correspondence in internal memory, can judge whether data read command is key instruction accurately, improve processor in internal memory, read the speed of data, and avoid inquiry and predict the problem that the hardware cost that brings is too high.
The embodiment of the present invention provides a kind of compiler 60, as shown in Figure 6, comprising:
Processing unit 61, obtains object code for carrying out compiling to source code.
Determining unit 62, for determining whether the first operational order in this object code has key.
This processing unit 61 also for, when determining that this first operational order has key, this first operational order is changed to the second operational order.
Wherein, this second operational order carries key instruction mark, so that Memory Controller Hub is when receiving this second operational order, determine that this second operational order is key instruction according to this key instruction mark, and according to preference strategy in internal memory to should the data of the second operational order operate.
Alternatively, this determining unit 62 specifically for, when the operand of the operand of this first operational order and the follow-up operational order of this first operational order meets pre-conditioned, determine that this first operational order has key.
Illustratively, source code is:
……
for（i=1；i<100;i++）
a[i]=a[0]+i;
……
The compiling of this compiler obtains object code:
……
LDR R2，[R1]；
ADD R3,R2,#1
STR R3,[R1,#1]
ADD R3,R2,#2
STR R3，[R1,#2]
……
ADD R3,R2,#99
STR R3，[R1,#99]
……
Further, this compiler is after obtaining above-mentioned object code, this object code is scanned, detect the relation of the operand of the operand of every bar operational order and the follow-up operational order of this operational order, when the operand of the operand of the first operational order and the follow-up operational order of this first operational order meets pre-conditioned, determine that this first operational order has key.Such as, this is pre-conditioned is greater than 5 for the operand occurrence number in the operand of subsequent operation instruction in this first operational order, then in above-mentioned object code, for the first operational order LDR R2, [R1], this first operational order represents and is saved in register R2 by the data reading at R1 address place, this compiler carries out scanning by the operational order follow-up to this first operational order can determine that the number of times that the operand R2 in this first operational order occurs in subsequent instructions is greater than 5, then this compiler determines that this first operational order has key.
From source code, perform the value that value that circulation obtains array a [1] to array a [99] all uses array a [0], the value in the register R2 in namely corresponding object code, therefore, if the unsuccessful execution of this first operational order, follow-up operational order all cannot perform.
Further, this first operational order, when determining that this first operational order has key, is changed to the second operational order by this compiler, as LDR_c R2, [R1], then the object code after change is:
……
LDR_c R2，[R1]
ADD R3,R2,#1
STR R3,[R1,#1]
ADD R3,R2,#2
STR R3，[R1,#2]
……
ADD R3,R2,#99
STR R3，[R1,#99]
……
It should be noted that, the above-mentioned pre-conditioned frequency that can also occur in the operand of subsequent operation instruction for the operand in this first operational order is greater than N, N be greater than zero positive integer, namely this compiler is after scanning object code, if determine, the frequency that the operand R2 of this first operational order occurs in subsequent operation instruction is greater than N, then this compiler determines that this first operational order has key.
Further, this first operational order, when determining that this first operational order has key, is changed to the second operational order by this compiler, as by this first operational order LDR R2, [R1] changes to the second operational order LDR_c R2, [R1], then the object code after change is:
……
LDR_c R2，[R1]
ADD R3,R2,#1
STR R3,[R1,#1]
ADD R3,R2,#2
STR R3，[R1,#2]
……
ADD R3,R2,#99
STR R3，[R1,#99]
……
Alternatively, if this first operational order is data read command, then processor do not find in the buffer to should the data of the first operational order time, this Memory Controller Hub receives this first operational order that this processor sends.
It should be noted that, the existence of this second operational order supported by this processor, and this processor is when processing this second operational order, the same with the processing mode of this first operational order.Even this first operational order is data read command, then this processor is when execution the second operational order, first inquire about in the buffer should the data of the second operational order, if exist should the data of the second operational order in buffer memory, then this processor reads this data; If when all can not find data corresponding to this second operational order in every level cache, then this second operational order is referred to be sent in Memory Controller Hub.
This Memory Controller Hub is when receiving this second operational order, determine that this second operational order is key instruction according to the key instruction mark that this second operational order carries, wherein, this key instruction mark can be the title of the operational code of this second operational order, as above-mentioned LDR_c, also can be other identification informations that this instruction is carried, be used to indicate the key of this second operational order.
Those skilled in the art can be well understood to, for convenience and simplicity of description, only be illustrated with the division of above-mentioned each functional module, in practical application, can distribute as required and by above-mentioned functions and be completed by different functional modules, inner structure by device is divided into different functional modules, to complete all or part of function described above.The specific works process of the unit of foregoing description, with reference to the corresponding process in preceding method embodiment, can not repeat them here.
Adopt above-mentioned compiler, this compiler is after obtaining object code, determine that the first operational order has key, and this first operational order is changed to the second operational order, so that Memory Controller Hub is when receiving this second operational order, determine that this second operational order is key instruction, and according to preference strategy in internal memory to should the data of the second operational order operate.Like this, if this Memory Controller Hub receives data read command, whether can carry key instruction mark according to this data read command and determine whether this data read command is key instruction, and preferentially call the data that this data read command reads correspondence in internal memory, can judge whether data read command is key instruction accurately, improve processor in internal memory, read the speed of data, and avoid inquiry and predict the problem that the hardware cost that brings is too high.
The embodiment of the present invention provides a kind of Memory Controller Hub 70, and as shown in Figure 7, this Memory Controller Hub 70 comprises:
Processor (processor) 71, communication interface (Communications Interface) 72, storer (memory) 73 and communication bus 74; Wherein, described processor 71, described communication interface 72 complete mutual communicating with described storer 73 by described communication bus 74.
Processor 71 may be a multi-core central processing unit CPU, or specific integrated circuit ASIC(Application Specific Integrated Circuit), or be configured to the one or more integrated circuit implementing the embodiment of the present invention.
Storer 73 is for depositing program code, and described program code comprises computer-managed instruction and network flow graph.Storer 73 may comprise high-speed RAM storer, still may comprise nonvolatile memory (non-volatile memory), such as at least one magnetic disk memory.
Described communication interface 72, for realizing the connection communication between these devices.
Described processor 71 for performing the program code in described storer 73, to realize following operation:
Determine that the first operational order has at compiler key, and after described first operational order is changed to the second operational order, receive described second operational order; Described second operational order carries key instruction mark;
Determine that described second operational order is key instruction according to described key instruction mark;
Operate according to the data of preference strategy to described second operational order corresponding in internal memory.
Alternatively, if described first operational order is data read command, then described second operational order of described Memory Controller Hub reception specifically comprises:
When processor does not find the data of corresponding described first operational order in the buffer, receive described first operational order that described processor sends.
Alternatively, if operational order to be called in described Memory Controller Hub is not key instruction, then described operation according to the data of preference strategy to described second operational order corresponding in internal memory specifically comprises:
Preferentially call the data of described second operational order to described second operational order corresponding in internal memory to operate.
Alternatively, described preferentially call described second operational order to internal memory in before the data of corresponding described second operational order operate, described operation also comprises:
Operand according to operational order to be called in the operand of described second operational order and described Memory Controller Hub determines that operational order to be called in described Memory Controller Hub and described second operational order do not exist the relation of sequence.
Affiliated those skilled in the art can be well understood to, and for convenience and simplicity of description, the specific works process of the Memory Controller Hub of foregoing description and description, with reference to the corresponding process in preceding method embodiment, can not repeat them here.
The embodiment of the present invention provides a kind of compiler 80, and as shown in Figure 8, this compiler 80 comprises:
Processor (processor) 81, communication interface (Communications Interface) 82, storer (memory) 83 and communication bus 84; Wherein, described processor 81, described communication interface 82 complete mutual communicating with described storer 83 by described communication bus 84.
Processor 81 may be a multi-core central processing unit CPU, or specific integrated circuit ASIC(Application Specific Integrated Circuit), or be configured to the one or more integrated circuit implementing the embodiment of the present invention.
Storer 83 is for depositing program code, and described program code comprises computer-managed instruction and network flow graph.Storer 83 may comprise high-speed RAM storer, still may comprise nonvolatile memory (non-volatile memory), such as at least one magnetic disk memory.
Described communication interface 82, for realizing the connection communication between these devices.
Described processor 81 for performing the program code in described storer 83, to realize following operation:
Compiling is carried out to source code and obtains object code;
Determine whether the first operational order in described object code has key;
When determining that described first operational order has key, described first operational order is changed to the second operational order, wherein, described second operational order carries key instruction mark, so that Memory Controller Hub is when receiving described second operational order, determine that described second operational order is key instruction according to described key instruction mark, and operate according to the data of preference strategy to described second operational order corresponding in internal memory.
Alternatively, whether described the first operational order determined in described object code has and keyly specifically to comprise:
When the operand of the operand of described first operational order and the follow-up operational order of described first operational order meets pre-conditioned, fixed described first operational order has key.
Affiliated those skilled in the art can be well understood to, and for convenience and simplicity of description, the specific works process of the induction installation of foregoing description and description, with reference to the corresponding process in preceding method embodiment, can not repeat them here.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (12)
1. a method for data manipulation, is characterized in that, comprising:
Determine that the first operational order has at compiler key, and after described first operational order is changed to the second operational order, Memory Controller Hub receives described second operational order; Described second operational order carries key instruction mark;
According to described key instruction mark, described Memory Controller Hub determines that described second operational order is key instruction;
Operate according to the data of preference strategy to described second operational order corresponding in internal memory.
2. method according to claim 1, is characterized in that, if described first operational order is data read command, then described second operational order of described Memory Controller Hub reception comprises:
When processor does not find the data of corresponding described first operational order in the buffer, receive described first operational order that described processor sends.
3. method according to claim 1 and 2, is characterized in that, if operational order to be called in described Memory Controller Hub is not key instruction, then describedly carries out operation according to the data of preference strategy to described second operational order corresponding in internal memory and comprises:
Preferentially call the data of described second operational order to described second operational order corresponding in internal memory to operate.
4. method according to claim 3, is characterized in that, described preferentially call described second operational order to internal memory in before the data of corresponding described second operational order operate, described method also comprises:
Operand according to operational order to be called in the operand of described second operational order and described Memory Controller Hub determines that operational order to be called in described Memory Controller Hub and described second operational order do not exist the relation of sequence.
5. a method for data manipulation, is characterized in that, comprising:
Compiler carries out compiling to source code and obtains object code;
Determine whether the first operational order in described object code has key;
When determining that described first operational order has key, described first operational order is changed to the second operational order, wherein, described second operational order carries key instruction mark, so that Memory Controller Hub is when receiving described second operational order, determine that described second operational order is key instruction according to described key instruction mark, and operate according to the data of preference strategy to described second operational order corresponding in internal memory.
6. method according to claim 5, is characterized in that, whether described the first operational order determined in described object code has key comprising:
When the operand of the operand of described first operational order and the follow-up operational order of described first operational order meets pre-conditioned, determine that described first operational order has key.
7. a Memory Controller Hub, is characterized in that, comprising:
Receiving element, key for determining that at compiler the first operational order has, and after described first operational order is changed to the second operational order, receive described second operational order; Described second operational order carries key instruction mark;
According to described key instruction mark, determining unit, for determining that described second operational order is key instruction;
Processing unit, for operating according to the data of preference strategy to described second operational order corresponding in internal memory.
8. Memory Controller Hub according to claim 7, it is characterized in that, described receiving element specifically for: if described first operational order is data read command, when processor does not find the data of corresponding described first operational order in the buffer, receive described first operational order that described processor sends.
9. the Memory Controller Hub according to claim 7 or 8, it is characterized in that, described processing unit specifically for: if operational order to be called in described Memory Controller Hub is not key instruction, preferentially calls the data of described second operational order to described second operational order corresponding in internal memory and operate.
10. Memory Controller Hub according to claim 9, it is characterized in that, described processing unit specifically for: preferentially call described second operational order to internal memory in before the data of corresponding described second operational order operate, the operand according to operational order to be called in the operand of described second operational order and described Memory Controller Hub determines that operational order to be called in described Memory Controller Hub and described second operational order do not exist the relation of sequence.
11. 1 kinds of compilers, is characterized in that, comprising:
Processing unit, obtains object code for carrying out compiling to source code;
Determining unit, for determining whether the first operational order in described object code has key;
Described processing unit also for, when determining that described first operational order has key, described first operational order is changed to the second operational order, wherein, described second operational order carries key instruction mark, so that Memory Controller Hub is when receiving described second operational order, determine that described second operational order is key instruction according to described key instruction mark, and operate according to the data of preference strategy to described second operational order corresponding in internal memory.
12. compilers according to claim 11, is characterized in that, described determining unit specifically for:
When the operand of the operand of described first operational order and the follow-up operational order of described first operational order meets pre-conditioned, determine that described first operational order has key.
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