CN104901707A - Anti-signal-interference device in electronic device detection - Google Patents
Anti-signal-interference device in electronic device detection Download PDFInfo
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- CN104901707A CN104901707A CN201510183799.7A CN201510183799A CN104901707A CN 104901707 A CN104901707 A CN 104901707A CN 201510183799 A CN201510183799 A CN 201510183799A CN 104901707 A CN104901707 A CN 104901707A
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Abstract
The invention discloses an anti-signal-interference device in electronic device detection. Signals generated by an electronic device successively pass a filtering and blocking circuit, an envelope demodulation and comparison circuit and an FPGA decoding determining device which are connected in series to determine whether the electronic device is effective; a bypass resistor Ra is connected with a bypass capacitor Ca in parallel and then with a main path resistor Rb in series to form the filtering and blocking circuit; the envelope demodulation and comparison circuit is composed of a bypass capacitor Cb and a main path capacitor Cd; and the bypass resistor Rb, the bypass capacitor Ca and the bypass capacitor Cb include a common end. The device is good in anti-interference effect, and whether the electronic device is effective can be determined in a highly reliable manner.
Description
Technical field
The present invention relates to detection and the signal processing apparatus of electronic device signal.
Background technology
The performance parameter of the electronic device such as electronic diode, microelectronic chip needs the instrument of specialty or circuit to test, and compares with the data of standard, judges the quality of electronic device with this.
Number of patent application be the disclosure of the invention of 2013101898949 a kind of multichannel interference signal generation device and interference signal production method, it comprises the interference parameter carrying out interference signal parameters setting and arranges equipment, signal output apparatus for generation of the interference signal generator of all kinds of array analog signal and the output for multichannel interference signal, and interference parameter arranges equipment and connects interference signal generator and signal output apparatus successively; Described interference parameter arranges equipment for arranging interference signal parameters, and interference signal parameters comprises interference strength, array format, array element distance and array amplitude phase error; Interference signal generator comprises the parameter setting circuit, multichannel baseband signal generation circuit and the power adjusting circuit that connect successively; Signal output apparatus comprises digital to analog converter and up-convert channel.The equipment of this invention is too complicated, and cost is more expensive.
Number of patent application be 2013100181407 brightly disclose the anti-interference digital sample device of multichannel, comprise: the analog to digital converter group of the ADC formation of several multidiameter delays, and the FPGA to be communicated with analog to digital converter group, the analog signal of the multi-channel parallel that multi-channel parallel radio-frequency front-end receives by described analog to digital converter group, being converted to can for the digital signal of FPGA process, described analog to digital converter group is also communicated with one to provide the sampled clock signal of adjustable delay clock chip for ADC, the sampled clock signal of described clock chip is divided into multidiameter delay to export to ADC chip.The circuit element of this device is fully open, is difficult to consult and use in reality test.
Summary of the invention
Goal of the invention:
There is provided a kind of antinoise signal interference performance strong, differentiate electronic device that fine or not accuracy is high detect in signal anti-interference device.
Technical scheme:
The invention provides a kind of electronic device detect in signal anti-interference device, the signal of communication occurred by electronic device to be decoded determining device by the filtering block isolating circuit of serial connection, envelope demodulation comparison circuit, FPGA successively, finally judges the quality of electronic device.
Described filtering block isolating circuit is made up of with the main road resistance Rb that connects after a shunt capacitance Ca parallel connection a bypass resistance Ra, envelope demodulation comparison circuit is made up of a shunt capacitance Cb and main road electric capacity Cd, and bypass resistance Rb, shunt capacitance Ca, shunt capacitance Cb have common common port (or earth terminal).
The value of Ca, Ra, Rb be respectively 100pf, 1000 ohm, 1000 ohm;
The value of Cb, Cd is respectively 10pf and 0.1 μ f.
Jamproof system of the present invention is mainly used in correct process chip return data, and because the communication of conventional radio-frequency (RF) identification chip is communication, communication protocol is ISO/IEC14443 agreement.
In the present invention, the communication data format of signal of communication is preferably Manchester's code mode.For chip inverse signal, first we can through simple filtering block isolating circuit, then through envelope demodulation comparison circuit, the envelope of inverse signal, have the envelope of data to show as the waveform of height height, the envelope of countless certificate then shows as the waveform of high level.
In native system, focus on FPGA process interference sections.It is high level during 50% bit period that the data 1 of Manchester's code are expressed as before data wire, is low level during rear 50% bit period.Being low level during data 0 are expressed as front 50% bit period, is low level during rear 50% bit period.
Accompanying drawing explanation
Fig. 1 is a circuit connection diagram of the present invention;
In figure, 1-diode (electronic device); 2-input signal; 3-shunt capacitance Ca; 4-bypass resistance Ra; 5-shunt capacitance Cb; 6-main road electric capacity Cd; 7-FPGA decodes determining device; 8-outputs signal; 9-envelope demodulation comparison circuit; 10-main road resistance Rb; 11-filtering block isolating circuit; 12-common port.
Embodiment
In native system as shown in Figure 1, the input signal 2 occurred by Schottky diode 1 decode determining device 7 by the filtering block isolating circuit 11 of serial connection, envelope demodulation comparison circuit 9, FPGA successively, judges that it is fine or not with this; Described filtering block isolating circuit 11 is made up of with the main road resistance Rb10 that connects after a shunt capacitance Ca3 parallel connection a bypass resistance Ra4, envelope demodulation comparison circuit 9 is made up of a shunt capacitance Cb5 and main road electric capacity Cd6, and bypass resistance Rb10, shunt capacitance Ca3, shunt capacitance Cb5 have common common port 12.
The value of Ca3, Ra4, Rb10 be respectively 100pf, 1000 ohm and 1000 ohm, the value of Cb5, Cd6 is respectively 10pf and 0.1 μ f.
We can according to communication protocol, and during a bit position, FPGA samples 8 data points, and these 8 points are evenly distributed, if front 4 points are high level, rear four points are that low spot is put down, then we judge that these data are 1, if front 4 points are low level, rear four points are that high point is flat, be then judged as data 0.Because we are according to communication protocol, then all data that should correctly return are aware of.If within the cycle that should be data 1, if front 4 points are high, be then judged as 1.Within the cycle that should be data 0, if rear four points are high, be then judged as 0.So just can correctly identify whole return data, compare with real data afterwards, judge whether returning of chip be correct.FPGA receives signal, carries out sampling analysis, compares with correct data, obtain comparative result according to communication protocol to signal, and judges chip quality with this.
Claims (5)
1. the signal anti-interference device in an electronic device detection, it is characterized in that: the input signal (2) occurred by electronic device (1) by filtering block isolating circuit (11), envelope demodulation comparison circuit (9), FPGA decoding determining device (7) of serial connection, judges the quality of electronic device (1) successively with this; Described filtering block isolating circuit (11) is by a bypass resistance Ra(4) with a shunt capacitance Ca(3) in parallel after to connect a main road resistance Rb(10) form, envelope demodulation comparison circuit (9) is by a shunt capacitance Cb(5) and main road electric capacity Cd(6) form.
2. electronic device as claimed in claim 1 detect in signal anti-interference device, it is characterized in that: bypass resistance Rb(10), shunt capacitance Ca(3), shunt capacitance Cb(5) there is common common port.
3. electronic device as claimed in claim 1 detect in signal anti-interference device, it is characterized in that: described Ca, the value of Ra, Rb be respectively 100pf, 1000 ohm and 1000 ohm.
4. the signal anti-interference device in electronic device detection as claimed in claim 1, is characterized in that: the value of described Cb, Cd is respectively 10pf and 0.1 μ f.
5. the signal anti-interference device in electronic device detection as claimed in claim 1, is characterized in that: the communication data format of signal of communication is Manchester's code mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510183799.7A CN104901707B (en) | 2015-04-18 | 2015-04-18 | Signal anti-interference device in electronic device detection |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510183799.7A CN104901707B (en) | 2015-04-18 | 2015-04-18 | Signal anti-interference device in electronic device detection |
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| CN104901707A true CN104901707A (en) | 2015-09-09 |
| CN104901707B CN104901707B (en) | 2017-03-15 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4996691A (en) * | 1988-09-21 | 1991-02-26 | Northern Telecom Limited | Integrated circuit testing method and apparatus and integrated circuit devices for use therewith |
| CN202210154U (en) * | 2011-06-22 | 2012-05-02 | 成都信息工程学院 | Weather radar test and fault detection device |
| CN102539970A (en) * | 2012-01-04 | 2012-07-04 | 华北电网有限公司计量中心 | RFID (radio frequency identification) equipment testing method and system |
| CN203025317U (en) * | 2012-09-10 | 2013-06-26 | 大唐微电子技术有限公司 | Contactless smart card chip test device |
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2015
- 2015-04-18 CN CN201510183799.7A patent/CN104901707B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4996691A (en) * | 1988-09-21 | 1991-02-26 | Northern Telecom Limited | Integrated circuit testing method and apparatus and integrated circuit devices for use therewith |
| CN202210154U (en) * | 2011-06-22 | 2012-05-02 | 成都信息工程学院 | Weather radar test and fault detection device |
| CN102539970A (en) * | 2012-01-04 | 2012-07-04 | 华北电网有限公司计量中心 | RFID (radio frequency identification) equipment testing method and system |
| CN203025317U (en) * | 2012-09-10 | 2013-06-26 | 大唐微电子技术有限公司 | Contactless smart card chip test device |
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| CN104901707B (en) | 2017-03-15 |
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