CN104885362B - Two-phase switching type capacitor device flash type ADC - Google Patents
Two-phase switching type capacitor device flash type ADC Download PDFInfo
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- CN104885362B CN104885362B CN201480003826.1A CN201480003826A CN104885362B CN 104885362 B CN104885362 B CN 104885362B CN 201480003826 A CN201480003826 A CN 201480003826A CN 104885362 B CN104885362 B CN 104885362B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
- H03M3/338—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching
- H03M3/34—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching by chopping
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
- H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
- H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/352—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M3/354—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M3/356—Offset or drift compensation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
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- Physics & Mathematics (AREA)
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- Power Engineering (AREA)
- Analogue/Digital Conversion (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The present invention discloses a kind of input stage for switching type capacitor device A/D converter, has the differential voltage input for receiving input voltage, the differential reference voltage input for receiving copped wave reference voltage, shares voltage connection and difference output.A pair of of input capacitor is coupling between the differential voltage input and the difference output, and a pair of of reference capacitor is coupling between the differential reference voltage input.By the first phase and the second phase control switch unit, the switch unit it is operable with：During the first phase, the first terminal of the input capacitor is connect with the shared voltage and is connected and the first terminal of the reference capacitor is coupled with inverting difference Voltage Reference；And during the second phase, the first terminal of the input capacitor is connected with the differential input voltage and the first terminal of the reference capacitor and the noninverting Differential voltage reference are coupled.
Description
The cross reference of related application
Present application advocates the equity of the 61/769th, No. 928 United States provisional application filed in 27 days 2 months in 2013, institute
The full text for stating Provisional Application is incorporated herein by reference.
Technical field
The present invention relates to two-phase switching type capacitor device flash type A/D converters (ADC), in particular, are related to use and cut
The flash type ADC of wave device Voltage Reference.
Background technology
The block diagram of conventional switching type capacitor device A/D converter 100 (ADC) is shown in Fig. 1.It will wait the input converted
Signal is fed through loop filter 110 and arrives quantizer 120, wherein usually converting the signals to have one or more points
The output bit stream of resolution.The output signal is fed back through into D/A converter 130 (DAC) and arrives the loop filter 110,
At the place output signal is subtracted from the input signal.
The A/D converter of this type introduces quantizing noise and offset error.In particular, it is used in the quantizer
Reference voltage introduces offset voltage and to make the distorted signals through measurement.
Invention content
In the presence of the demand of the Curve guide impeller to switching type capacitor device DAC.According to embodiment, switching type capacitor device analog/digital turns
The input stage of parallel operation may include that the differential voltage input of reception input voltage, the differential reference voltage of reception copped wave reference voltage are defeated
Enter, share voltage connection, difference output, a pair of of the input electricity being coupling between the differential voltage input and the difference output
Container, a pair of of the reference capacitor being coupling between the differential reference voltage input, and pass through the first phase and the second phase control
Switch unit, the switch unit it is operable with during the first phase by the first terminal of the input capacitor with it is described total
It is connected with voltage connection and the first terminal of the reference capacitor is coupled with inverting difference Voltage Reference；And
The first terminal of the input capacitor is connected with the differential input voltage during second phase and by the reference
The first terminal of capacitor is coupled with noninverting Differential voltage reference.
According to another embodiment, first phase and the second phase are defined by Non-overlapping clock signal.According to another implementation
Example, the reference voltage carry out copped wave using the Non-overlapping clock signal.According to another embodiment, the reference voltage includes one
Positive offset voltage during a phase and the negative offset voltage during another phase.According to another embodiment, in the first phase phase
Between, the Second terminal of the input capacitor is coupled with voltage connection together.According to another embodiment, described first
During phase, the Second terminal of the input capacitor is coupled with negative input voltage.According to another embodiment, positive input capacitance
The first terminal of device and the first terminal of positive reference capacitor are coupled with positive output terminal, and negative input capacitor
The first terminal and the first terminal of negative reference capacitor be coupled with negative output terminal.According to another embodiment,
The shared voltage is connected as being grounded.According to another embodiment, the shared voltage is connected as virtual ground.
According to yet another embodiment, the method that input signal is provided to the quantizer of the sigma-delta modulator with input stage
(input stage has a pair of of input capacitor and a pair of of reference capacitor, wherein the input capacitor and reference capacitor
Each of first terminal be connected respectively with positive output terminal and negative output terminal) may include：It, will during the first phase
The positive output terminal and negative output terminal are connected with voltage and are charged to the reference capacitor with reverse phase reference voltage together；
And during follow-up second phase, the positive output terminal and negative output terminal are disconnected from the shared voltage, and by the input
The first terminal of capacitor and the first terminal of the reference capacitor respectively with noninverting differential input voltage and
The noninverting reference voltage is connected.
According to another embodiment of the method, first phase and described second are defined by Non-overlapping clock signal
Phase.According to another embodiment of the method, the Non-overlapping clock signal can be used to carry out copped wave to the reference voltage.Root
According to another embodiment of the method, the reference voltage include during a phase positive offset voltage and during another phase
Negative offset voltage.According to another embodiment of the method, during first phase, described the of the input capacitor
Two-terminal connect with the shared voltage and is coupled.It is described during first phase according to another embodiment of the method
The Second terminal of input capacitor is coupled with reverse inter-input-ing voltage.It is described to share according to another embodiment of the method
Voltage is connected as being grounded.According to another embodiment of the method, the shared voltage is connected as virtual ground.
Description of the drawings
Fig. 1 shows the block diagram of sigma-delta modulator.
Fig. 2 shows ADC grades of ventional flash formula.
Fig. 3 shows copped wave reference voltage.
Fig. 4 shows the input stage of sigma-delta modulator according to first embodiment.
Fig. 5 shows the input stage of sigma-delta modulator according to second embodiment.
Specific implementation mode
According to various embodiments, it is possible to provide the two-phase switching type capacitor device flash type ADC of chopper voltage reference is used,
In in the flash type ADC the average Voltage Reference.Disclosure address how can be based on two-phase switching type capacitor device
Flash type ADC in using chopper voltage reference without being put down by the bias effect of the Voltage Reference and without additional circuit
The described chopper voltage reference.
In the sigma-delta-converter such as (e.g.) shown in Fig. 1, multi-layer usually is made using flash type ADC and modulates
The quantizer of device.These flash types ADC is usually based on capacitive, and cutting for the signal and the reference is sampled wherein existing
Switching network, whether the sampled signal followed by the generation is higher than the threshold value provided by the reference voltage
Comparator.
The flash type ADC usually uses two phases (one reset mutually and a comparison phase) with can be in two independent ratios
The condenser charge is resetted compared between.The Voltage Reference often from chopper voltage reference source, to avoid l/f noise and
Offset error in the reference signal.
According to various embodiments, it is possible to provide the two-phase switching type capacitor device flash type ADC of chopper voltage reference is used,
In in the flash type ADC the average Voltage Reference so that do not need low-pass filter with the averagely described chopper signal.
This also allows in flash type ADC with small twice of reference capacitor.This will eliminate the institute having as the flash type ADC
The demand that is not buffered and not being chopped into voltage reference signal of reference source is stated, and to also simplify setting for multi-layer modulator
Meter.
To be made of multiple comparator stages, (n comparator corresponds to n+1 layer of the ADC resolution ratio to ventional flash formula ADC
Grade).Such as displaying (such as showing in fig. 2), at each level, each of described comparator stage is usually by switching type capacitor
Device circuit drives.
This circuit be with the input signal Vin+/- and reference signal Vref+/- and be used for common mode virtual ground
Or the differential input stage of the VCM of ground signalling.Vin+ is connected by switch 210a with the first terminal of capacitor 230a, capacitor
The Second terminal of 230a is coupled with the leading-out terminal OP.Switch 215a is by the first terminal phase of Vref+ and capacitor 240a
Connection, the Second terminal of capacitor 240a are coupled with the leading-out terminal OP.Switch 215b is by Vref-'s and capacitor 240b
First terminal is connected, and the Second terminal of capacitor 240b is coupled with the leading-out terminal OM.Switch 210b by Vin- with electricity
The first terminal of container 230b is connected, and the Second terminal of capacitor 230b is coupled with the leading-out terminal OM.
Switch 220a to 220d is provided with by the first terminal of capacitor 230a, 240a, 240b and 230b and VCM phases
Coupling.The leading-out terminal OP and OM is connected by switch 250a and 250b with VCM, and OP is connected by switch 260 with OM.It is logical
Oversampling clock signal P1 control switch 220a to 220d, 250a, 250b and 260, and by clock signal P2 control switches 210a,
210b and 215a, 215b.
Output OP/OM is connected to comparator (respectively in positive side and negative side).In general, here, the circuit is in two phases
Work is with by the electric charge transfer to the comparator in P1 and P2 (non-overlapping phase/clock signal).In P1 phases, it is connected to
It is that the switch of OP/OM is to turn on and the top plate of all capacitors and bottom plate are reset into VCM.There is no charge to be transferred to institute
State comparator.Be connected to Vin+/- and Vref+/- the input switch disconnect.In this phase, OP=OM=VCM.This is multiple
Position phase.
It in phase P2, shifts, therefore this is transfer phase.Because input switch 210a, 210b and 215a, 215b are to turn on
, so sampling each input on its corresponding capacitor 230a, 230b and 240a, 240b.Because being connected to the switch of OP/OM
250a, 250b and 260 disconnections, so OP/OM signals are no longer reset to VCM.The value of OP/OM signals depend on Vin+/- and
Vref+/- and the capacitor value.Cin if (Vin+-Vin-)-Cref (Vref+-Vref-)>0 (this expression Vin+-Vin->
Cref/Cin* (Vref+-Vref-)), then OP-OM differential voltages become just.So the institute of differential voltage input Vin+-Vin-
It is Cref/Cin (Vref+-Vin-) to state effective comparator threshold.Each of described comparator stage usually has by described
Cref capacitor values setting different comparator thresholds and its be uniformly distributed with consistent quantization error.Only when described
Negative threshold value is realized when exchanging Vref+ and Vref- in input.
This conventional grade shown in Fig. 2 has problem when/- includes chopping modulation as Vref+, though it is described be modulated at P1 with
It is also such that (this is natural way) occurs between P2.If shown in figure 3, if Vref+-Vref-=is written in phase P1
Vref+Voff and in phase P2 be written Vref+-Vref-=Vref-Voff, then can be directed to be chopped between P1 and P2 and
The average Voltage Reference of offset and Vref with Voff and obtain model.
In the conventional grade, the Vref transfers only occur in P2 (in Vref+/- input).So in chopper
In the case of modulated Voltage Reference, Vref-Voff is shifted always.So in the case, having never been realized appropriate flat
Always the Vref offsets are integrated and in the output charge, this is not the purpose of the chopper modulation.
The improved input stage of the switching type capacitor device ADC of Fig. 4 displayings according to various embodiments.Switch 410a by Vin+ with
The first terminal of capacitor 450a is connected, and Second terminal and the output OP of capacitor 450a are coupled.Switch 420a is by Vref+
It is connected with the first terminal of capacitor 460a, Second terminal and the output OP of capacitor 460a are coupled.Switch 420b will
Vref- is connected with the first terminal of capacitor 460b, and Second terminal and the output OM of capacitor 460b are coupled.Switch
Vin- is connected by 410b with the first terminal of capacitor 450b, Second terminal and the output OM phase couplings of capacitor 450b
It closes.Switch 440a and 440b is provided so that the first terminal of capacitor 450a and 450b to be coupled with VCM.There is provided switch 470a and
470b is coupled with that will export OP and OM with VCM, and switch 480 keeps output OP and OM short-circuit.Switch 430a is provided with by Vref-
It is connected to the first terminal of capacitor 460a and provides switch 430b so that Vref+ is connected to described the of capacitor 460b
One terminal.Switch 440a, 440b, 430a, 430b, 470a, 470b and 480 are controlled by clock signal P1.Pass through clock signal
P2 controls switch 410a, 410b and 420a, 420b.
In proposed structure according to various embodiments, if Fig. 4 is shown, no longer exist on the Vref input switches
Switch to VCM connects.Switch 420a, 420b and 430a, 430b be now in cross-over configuration and be connected to Vref+ or
Any one of Vref-.In phase P1, one group of switch 430a, 430b by capacitor 460a, 460b be connected to Vref+/-, and
In phase P2, one group of supplement switch 420a, 420b be connected to opposite Vref- /+.So shifted on reference capacitor Cref
Total charge dosage is just：
- Cref (Vref+-Vref-) in phase P1, and
Cref (Vref--Vref+) in phase P2.
In the case of being the copped wave reference input switched between P1 and P2, it can be written as：Vref+-Vref- in phase P1
=the Vref+Voff and Vref+-Vref-=Vref-Voff in phase P2, the total electrical charge of transfer are：Charge (P2)-charge
(P1)=Cref Vref+Voff)-(- Cref (Vref-Voff))=2*Cref*Vref.In this summation, it is attributed in Vref
Switch 420a, the 420b connected in the demodulation of the chopper of +/- input completion and the cross-over configuration on P1 and P2
And 430a, 430b, eliminate the Voff components.This is indicated by the condenser charge integrates between described two phases
The average reference and therefore comparison result is deviated independently of the Voltage Reference, this solves the problems, such as routine ADC.Input letter
Number capacitor Cin is not changed but may also set up in cross-over configuration to be obtained in the sampled signal in this configuration
The factor of twice (2x) (as long as can obtain the input signal during described two phases, this simultaneously not always sets up
).By this new technology, twice of gain is realized in the paths Vref, thus Cref can divided by two with keep it is identical effectively
Threshold value, this is conducive to stabilization time problem and bare die size.Number of switches is still identical as in routinely configuring, so being not present
Practical apparent disadvantage.Chopper modulation only needs synchronouss with phase P1 and P2, and switching needs are between P1 and P2
Occur to realize that offset appropriate is eliminated.
Fig. 5 shows the exemplary embodiment of circuit, wherein realizing twice of increasing in the paths Vin by the cross-over configuration
Benefit.Vin+ is connected by switch 510a with the first terminal of capacitor 550a, Second terminal and the output OP phases of capacitor 550a
Coupling.Vref+ is connected by switch 520a with the first terminal of capacitor 560a, the Second terminal of capacitor 560a with it is defeated
Go out OP to be coupled.Vref- is connected by switch 520b with the first terminal of capacitor 560b, the second end of capacitor 560b
Son is coupled with output OM.Vin- is connected by switch 510b with the first terminal of capacitor 550b, capacitor 550b's
Second terminal is coupled with output OM.Vin- is connected by switch 540a with the first terminal of capacitor 550a, and switchs
Vin+ is connected by 540b with the first terminal of capacitor 550b.There is provided switch 570a and 570b with will export OP and OM and
VCM is coupled and switch 580 keeps output OP and OM short-circuit.Switch 530a is provided so that Vref- to be connected to the institute of capacitor 560a
It states first terminal and provides switch 530b so that Vref+ to be connected with the first terminal of capacitor 560b.Switch 540a,
It 540b, 530a, 530b, 570a, 570b and 580 is controlled by clock signal P1.Switch 510a, 510b and 520a, 520b pass through
Clock signal P2 controls.
Claims (15)
1. a kind of input stage for switching type capacitor device A/D converter comprising：
Include the switch unit of multiple switching devices；
Receive the differential voltage input of differential input voltage；
The differential reference voltage input of copped wave differential reference voltage is received, the copped wave differential reference voltage includes reference voltage
And negative reference voltage；
Share voltage connection；
Difference output；
A pair of of input capacitor, wherein the first terminal of the first input capacitor is via the first switching device and the differential voltage
The first voltage input coupling of input, and the first output of the Second terminal of first input capacitor and the difference output
Coupling, and the first terminal of wherein the second input capacitor inputted via first switching device and the differential voltage the
Two control sources couple, and the second output coupling of the Second terminal of second input capacitor and the difference output；
A pair of of reference capacitor, wherein the first terminal of the first reference capacitor is via the second switching device and the differential reference
First reference input of control source or the second reference input coupling, and the Second terminal of first reference capacitor with it is described
First output coupling of difference output, and the first terminal of wherein the second reference capacitor is via second switching device and institute
State the second reference input or the coupling of the first reference input of differential reference voltage input, and the second of second reference capacitor
Second output coupling of terminal and the difference output；
The wherein described switch unit by the first phase and the second phase control, and the switch unit it is operable with
During the first phase, via third switching device by the institute of first input capacitor and second input capacitor
It states first terminal and is connect with the shared voltage and is connected and via second switching device by the institute of the reference capacitor
First terminal is stated to be coupled with reverse phase copped wave differential reference voltage；And
During the second phase, via first switching device by first input capacitor and second input capacitor
The first terminal be connected with the differential input voltage and via second switching device by it is described first with reference to electricity
Container and the first terminal of second reference capacitor are coupled with noninverting copped wave differential reference voltage.
2. input stage according to claim 1, wherein first phase and the second phase are defined by Non-overlapping clock signal.
3. input stage according to claim 2, wherein the differential reference voltage is come using the Non-overlapping clock signal
Copped wave.
4. input stage according to claim 3, wherein the differential reference voltage includes the positive offset during a phase
Voltage and the negative offset voltage during another phase.
5. input stage according to claim 1, wherein during first phase, the Second terminal of the input capacitor
It is coupled together with voltage connection via the 4th switching device.
6. input stage according to claim 1, wherein the shared voltage is connected as being grounded.
7. input stage according to claim 1, wherein the shared voltage is connected as virtual ground.
8. a kind of input stage for switching type capacitor device A/D converter comprising：
Include the switch unit of multiple switching devices；
Receive the differential voltage input of differential input voltage；
The differential reference voltage input of copped wave differential reference voltage is received, the copped wave differential reference voltage includes reference voltage
And negative reference voltage；
Share voltage connection；
Difference output；
A pair of of input capacitor, wherein the first terminal of the first input capacitor is via the first switching device and the differential voltage
The first voltage of input inputs or second voltage input coupling, and the Second terminal of first input capacitor and the difference
First output coupling of output, and the first terminal of wherein the second input capacitor is via first switching device and the difference
The first voltage input of component voltage input or second voltage input coupling, and the Second terminal of second input capacitor and institute
State the second output coupling of difference output；
A pair of of reference capacitor, wherein the first terminal of the first reference capacitor is via the second switching device and the differential reference
First reference input of control source or the second reference input coupling, and the Second terminal of first reference capacitor with it is described
First output coupling of difference output, and the first terminal of wherein the second reference capacitor is via second switching device and institute
State the second reference input or the coupling of the first reference input of differential reference voltage input, and the second of second reference capacitor
Second output coupling of terminal and the difference output；
The wherein described switch unit by the first phase and the second phase control, and the switch unit it is operable with
During the first phase, via first switching device by first input capacitor and second input capacitor
The first terminal be connected with backward difference input voltage and via second switching device by it is described first with reference to electricity
Container and the first terminal of second reference capacitor are coupled with reverse phase copped wave differential reference voltage；And
During the second phase, via first switching device by first input capacitor and second input capacitor
The first terminal be connected with non-return differential input voltage and referred to described first via second switching device
Capacitor and the first terminal of second reference capacitor are coupled with noninverting copped wave differential reference voltage,
Wherein described copped wave differential reference voltage copped wave between first phase and second phase so that during a phase
Positive offset occurs, and negative offset occurs during another phase.
9. a kind of method for the quantizer that input signal is provided to the sigma-delta modulator with input stage, the input stage tool
There are a pair of of input capacitor and a pair of of reference capacitor, wherein the of each of the input capacitor and reference capacitor
One terminal is connected with positive output terminal and negative output terminal respectively, and it includes positive reference that the wherein described sigma-delta modulator, which receives,
The copped wave differential reference voltage of voltage and negative reference voltage, the method includes：
During the first phase, the positive output terminal and negative output terminal are connected with voltage together, and by described with reference to electricity
The Second terminal of container is connected with backward difference reference voltage, while the Second terminal of the input capacitor and ground phase coupling
It closes；And
During follow-up second phase, the positive output terminal and negative output terminal are disconnected from the shared voltage, and will be described defeated
The Second terminal for entering capacitor is connected with noninverting differential input voltage and by described the second of the reference capacitor
Terminal is connected with the differential reference voltage,
Wherein described copped wave differential reference voltage copped wave between first phase and second phase so that during a phase
Positive offset occurs, and negative offset occurs during another phase.
10. being connected as being grounded according to the method described in claim 9, wherein sharing voltage.
11. according to the method described in claim 9, wherein sharing voltage is connected as virtual ground.
12. a kind of method for the quantizer that input signal is provided to the sigma-delta modulator with input stage, the input stage tool
There are a pair of of input capacitor and a pair of of reference capacitor, wherein the of each of the input capacitor and reference capacitor
One terminal is connected with positive output terminal and negative output terminal respectively, and the wherein described sigma-delta modulator is received to have and just be referred to
The copped wave differential reference voltage of voltage and negative reference voltage, the method includes：
During the first phase, the positive output terminal and negative output terminal are connected with voltage together, and by described with reference to electricity
The Second terminal of container is connected with backward difference reference voltage, while the Second terminal and backward difference of the input capacitor
Input voltage is coupled；And
During follow-up second phase, the positive output terminal and negative output terminal are disconnected from the shared voltage, and will be described defeated
The Second terminal for entering capacitor is connected with noninverting differential input voltage and by described the second of the reference capacitor
Terminal is connected with the differential reference voltage,
Wherein described copped wave differential reference voltage copped wave between first phase and second phase so that during a phase
Positive offset occurs, and negative offset occurs during another phase.
13. according to the method for claim 12, wherein first phase and the second phase are defined by Non-overlapping clock signal.
14. according to the method for claim 13, wherein the differential reference voltage is come using the Non-overlapping clock signal
Copped wave.
15. according to the method for claim 14, wherein the differential reference voltage includes the positive offset during a phase
Voltage and the negative offset voltage during another phase.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361769928P | 2013-02-27 | 2013-02-27 | |
| US61/769,928 | 2013-02-27 | ||
| US14/181,904 US9154155B2 (en) | 2013-02-27 | 2014-02-17 | 2-phase switched capacitor flash ADC |
| US14/181,904 | 2014-02-17 | ||
| PCT/US2014/017262 WO2014133852A1 (en) | 2013-02-27 | 2014-02-20 | 2-phase switched capacitor flash adc |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104885362A CN104885362A (en) | 2015-09-02 |
| CN104885362B true CN104885362B (en) | 2018-09-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480003826.1A Active CN104885362B (en) | 2013-02-27 | 2014-02-20 | Two-phase switching type capacitor device flash type ADC |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US9154155B2 (en) |
| EP (1) | EP2962392B1 (en) |
| KR (1) | KR20150122628A (en) |
| CN (1) | CN104885362B (en) |
| TW (1) | TWI640164B (en) |
| WO (1) | WO2014133852A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9525426B2 (en) * | 2015-02-05 | 2016-12-20 | Infineon Technologies Ag | Cross-coupled input voltage sampling and driver amplifier flicker noise cancellation in a switched capacitor analog-to-digital converter |
| CN106230433A (en) * | 2016-09-20 | 2016-12-14 | 天津大学 | High-speed-differential Voltage Reference Buffer |
| US10014879B1 (en) * | 2017-11-30 | 2018-07-03 | Cirrus Logic, Inc. | Capacitance-to-digital converter |
| DE102021100438B3 (en) | 2021-01-12 | 2022-05-12 | Elmos Semiconductor Se | Device for simultaneous delta-sigma analog-to-digital conversion of multiple input signals |
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| CN101589549A (en) * | 2007-01-31 | 2009-11-25 | 麦德托尼克公司 | Chopper-stabilized instrumentation amplifier |
| CN102187582A (en) * | 2008-10-23 | 2011-09-14 | 密克罗奇普技术公司 | Multi-level feed-back digital-to-analog converter using a chopper voltage reference for a switched capacitor sigma-delta analog-to-digital converter |
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| JP3103657B2 (en) | 1992-03-23 | 2000-10-30 | 松下電器産業株式会社 | A / D converter having voltage holding circuit and capacitive coupling network |
| US6972705B1 (en) | 2004-12-14 | 2005-12-06 | Cirrus Logic, Inc. | Signal processing system having an ADC delta-sigma modulator with single-ended input and feedback signal inputs |
| US7136006B2 (en) | 2004-12-16 | 2006-11-14 | Texas Instruments Incorporated | Systems and methods for mismatch cancellation in switched capacitor circuits |
| EP2338229B1 (en) * | 2008-10-13 | 2013-03-13 | Integrated Device Technology, Inc. | Switched-capacitor pipeline stage |
| US7999710B2 (en) | 2009-09-15 | 2011-08-16 | Texas Instruments Incorporated | Multistage chopper stabilized delta-sigma ADC with reduced offset |
| WO2012005777A1 (en) | 2010-07-08 | 2012-01-12 | Microchip Technology Incorporated | 2-phase gain calibration and scaling scheme for switched capacitor sigma-delta modulator using a chopper voltage reference |
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2014
- 2014-02-17 US US14/181,904 patent/US9154155B2/en active Active
- 2014-02-20 CN CN201480003826.1A patent/CN104885362B/en active Active
- 2014-02-20 WO PCT/US2014/017262 patent/WO2014133852A1/en active Application Filing
- 2014-02-20 EP EP14708423.0A patent/EP2962392B1/en active Active
- 2014-02-20 KR KR1020157017519A patent/KR20150122628A/en not_active Application Discontinuation
- 2014-02-27 TW TW103106891A patent/TWI640164B/en active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101589549A (en) * | 2007-01-31 | 2009-11-25 | 麦德托尼克公司 | Chopper-stabilized instrumentation amplifier |
| CN102187582A (en) * | 2008-10-23 | 2011-09-14 | 密克罗奇普技术公司 | Multi-level feed-back digital-to-analog converter using a chopper voltage reference for a switched capacitor sigma-delta analog-to-digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2962392A1 (en) | 2016-01-06 |
| CN104885362A (en) | 2015-09-02 |
| TW201448472A (en) | 2014-12-16 |
| US20160028413A1 (en) | 2016-01-28 |
| US9154155B2 (en) | 2015-10-06 |
| TWI640164B (en) | 2018-11-01 |
| WO2014133852A1 (en) | 2014-09-04 |
| US9300319B2 (en) | 2016-03-29 |
| EP2962392B1 (en) | 2018-12-26 |
| KR20150122628A (en) | 2015-11-02 |
| US20140240155A1 (en) | 2014-08-28 |
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