CN104882091B - Gray level expanded circuit and implementation method on a kind of microdisplay on silicon piece - Google Patents
Gray level expanded circuit and implementation method on a kind of microdisplay on silicon piece Download PDFInfo
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Abstract
Gray level expanded circuit and implementation method on a kind of microdisplay on silicon piece.Gray level expanded circuit on the microdisplay on silicon piece, available for fields such as silicon based LCD micro-display (LCoS), silicon substrate OLED micro-displays (OLEDoS) and other microdisplay on silicon parts, the integrated data drive circuit on the piece of microdisplay on silicon.It is made up of scanning sequence control circuit, shift-register circuit, expansible DATA REG circuitry, digital analog converter and analog signal output buffer circuit.Gray level expanded circuit on the microdisplay on silicon piece that the present invention is provided, can be by most one times of the extension of the gray level of the microdisplay on silicon of N Data In-Lines, interconnection resource on high grade grey level microdisplay on silicon piece can be saved, cost is reduced, available for requiring the wearable display that high grade grey level is shown.
Description
Technical field
The present invention relates to fields such as miniature Display Technique, Helmet-mounted Display Technique and video eyeglasses, silicon substrate liquid is related specifically to
Structure and its implementation on brilliant micro-display device, the integration slice of silicon-based organic light-emitting micro-display device.
Background technology
Technology of Microdisplay on Silicon includes liquid crystal on silicon LCoS and silicon-based organic light-emitting device OLEDoS etc., is using extensive
The micro-dimension high resolution display that integrated circuit technology is prepared on silicon chip, in wearable electronic, virtual reality, video
The portable mobile field of information display such as glasses, micro- projection display have application widely.
A kind of important application of microdisplay on silicon is near-to-eye, and be exactly that image-tape glasses are the same is placed on eye display
The side of eyeball, this requires the volume very little of display device, generally less than 0.3 inch.In order to improve display resolution, save micro-
Data-bus width inside interconnection resource on the piece of display chip, micro-display is at 6 and following, so may result in figure
The brightness of picture and the stereovision of color decline, gray level reduction, image of poor quality.Particularly it is used for the medical 3D displays of wear-type
When, brightness and gray level can not meet the requirement of display.Prior art is in the external circuit of display, to utilize image enhaucament
Technology carries out cut position and smoothing processing to 8 digital video signals, improves the stereovision of image, and in the inside of micro-display, image
Gray level be still 6, it is impossible to the details of real display original image.
Gray level expanded circuit on microdisplay on silicon piece proposed by the present invention, can be in display chip internal extended video
The bit wide of data, enables the micro-display chip of low-bit width data-interface to show the image of high grade grey level, both saved on piece
Interconnection resource, can improve the imaging quality of display again, applied to 3D video eyeglasses, medical 3D laparoscopes and portable wearable
Video display, it is significant.
The content of the invention
Present invention aim to address low-bit width (less than 6) micro display chip display gray scale is not high, brightness of image and
Color hierarchy sense declines problem.Gray level expanded circuit and implementation method on a kind of piece of micro display chip are provided.On this
Gray level expanded circuit, can be micro- aobvious by the silicon substrate with M digital video Data In-Lines using video data latch mechanism on piece
Show that the gray level of device expands to 2M, this saves microdisplay on silicon to greatest extent for the micro-display of design smaller volume
Piece on interconnection resource, realize the micro-display of high grade grey level, the particularly high grade grey level for medical 3D video-endoscopes etc.
Wearable display, will be with a wide range of applications.
Gray level expanded circuit on the microdisplay on silicon piece that the present invention is provided, controls circuit, displacement to post by scanning sequence
Latch circuit, expansible DATA REG circuitry, digital analog converter and analog signal output buffer circuit composition.
Described scanning sequence control circuit has two inputs, believes respectively with outside line synchronising signal and pixel clock
Number be connected, its output end has four, respectively with two inputs of shift-register circuit and expansible DATA REG circuitry
Two inputs be connected；Two inputs of described shift-register circuit control two outputs of circuit with scanning sequence
End is connected, and its N road control line output terminal is connected with the N roads control line input of expansible DATA REG circuitry, and (N is according to display
Device resolution ratio determines that, for the display of 1920x1080 resolution ratio, 1920) N takes；Described expansible DATA REG circuitry
Input have five, one of input is the N roads control line output terminal phase of N roads control line and shift-register circuit
Even, an input is that M digital video data input pins are connected to outside, and its excess-three input controls circuit with sequence scanning respectively
Two output ends be connected with outside gray level control signal input, the output end of expansible DATA REG circuitry is N roads 2M
Position datawire, is connected with 2M, the N roads data input pin of digital analog converter；The input of described digital analog converter has two groups,
2M, the N roads data output end with outside 8 tunnels simulation step power supply and expansible DATA REG circuitry is connected respectively, digital-to-analogue
The output end of converter is connected with the N roads input end of analog signal of analog signal output buffer circuit；Described analog signal is defeated
Go out the input of buffer circuit with the N roads analog signal output of digital analog converter to be connected, its output end is communicated with the outside.
Described scanning sequence control circuit includes monopulse generator, linage-counter, height word bit decision circuitry and arteries and veins
Rush synchronous circuit；The input of monopulse generator is connected with outside line synchronising signal, and the one of output end and pulse synchronization circuit
Individual input is connected；The input of linage-counter is connected with external pixels clock signal, and the output end of linage-counter has three, point
Not with the input, the input of height word bit decision circuitry and expansible DATA REG circuitry of pulse synchronization circuit
One input is connected；Two output ends of pulse synchronization circuit are connected with two inputs of shift-register circuit；Just
The output end of word bit decision circuitry is connected with an input of expansible DATA REG circuitry.
Described expansible DATA REG circuitry includes N number of element circuit and N number of unit second level latch；Described
One input C1 of N number of element circuit connects together and controls an output end of circuit to be connected with scanning sequence, and second
Individual input C3 connects together and is connected with the input of outside gray level control signal, the M digital video data wires of N number of element circuit
Input is connected to outside, the 2M digital video data line output terminals of N number of element circuit and N number of unit second level latch each unit electricity
The 2M digital video data wires input on road is connected；One input C2 of described N number of unit second level latch is connected in one
Rise and control an output end of circuit to be connected with scanning sequence, the 2M of 2M digital video data wire inputs and N number of element circuit
Digital video data line output terminal is connected, 2M digital video data line output terminals and the number shown in Fig. 1 of N number of unit second level latch
The N roads 2M position datawires input of weighted-voltage D/A converter is connected.
The element circuit of described expansible DATA REG circuitry, including M single-pole double-throw switch (SPDT)s, M gate controlled switches
With 2M data latches；One group of common port that is, M-bit data input and outside M-bit data in M single-pole double-throw switch (SPDT)s
Line is connected, and the low M each inputs of the normally closed points of M single-pole double-throw switch (SPDT)s respectively with 2M data latches are connected, M hilted broadswords
M position each input of the opened point of commutator respectively with M gate controlled switches is connected；The control end of M single-pole double-throw switch (SPDT)s with
One output end C1 of scanning sequence control circuit is connected；The M positions output end of M gate controlled switches respectively with 2M data latches
High M each inputs be connected；Another input of M gate controlled switches is connected with outside gray level control signal input C3；
Wherein 2M position datawires are connected the 2M position output ends of 2M data latches all the way with the N roads input of digital analog converter.
The implementation method of gray level expanded circuit function, is sequentially passed through following on the microdisplay on silicon piece that the present invention is provided
Step：
The firstth, outside gray level control signal is set, and C3=0 is low grey-scale modes, and C3=1 is high grade grey level pattern；
As C3=0, between the high period of C1 signals, M gate controlled switches are closed, and high M of each 2M data latches can not
Data are write, are M low grey-scale modes；As C3=1, between the high period of C1 signals, M gate controlled switches are opened, 2M
High M and low M of position data latches can write data, be 2M high grade grey level patterns, 2M is realized using M-bit data line
Position high grade grey level；
Secondth, scanning sequence controls circuit under outer row synchronization and the control of pixel clock signal, produces shift LD
Displacement enabling signal HS, the shift clock CLK and expansible DATA REG circuitry write control signal C1 of device circuit, during displacement
Clock CLK and control signal C1 are the two divided-frequencies of external pixels clock signal；Shift-register circuit in the presence of shift clock,
N roads control signal is exported, and is sequentially output from 1 to N a high level；
3rd, expansible DATA REG circuitry is under the output signal control of shift-register circuit, each clk cycle
A 2M bit digital vision signal is latched in two times, by each 2M of M digital videos data write-in between the low period of C1 signals
Low M of data latches, are write next M digital videos data by M gate controlled switches between the high period of C1 signals
High M of each 2M data latches；
4th, under the output signal control of shift-register circuit, from 1 to N, the of expansible DATA REG circuitry
After the 2M positions data latches of Unit one to N units are completed to the latch of a line vision signal, scanning sequence control circuit
Output signal C2 produces a high pulse signal, the data of all units is sent to N number of 2M second level latch；
5th, the data being sent in N number of 2M second level latch are directly output to N roads 2M digit weighted-voltage D/A converters, utilize
The multi-channel analog step power supply of outside input is to carrying out digital-to-analogue conversion, output N roads simulation electricity per 2M digital videos data all the way simultaneously
Pressure；Back-end circuit is output to after the processing of analog signal output buffer circuit, complete the scanning of a line vision signal and defeated again
Go out；
6th, wait next line synchronising signal to arrive, repeat.
Advantages and positive effects of the present invention
Gray level expanded circuit can solve the problem that low-bit width (less than 6) silicon substrate on the microdisplay on silicon piece that the present invention is provided
Micro display chip display gray scale is not high, the problem of brightness of image and color hierarchy sense decline.Wearable display device is requirement
The micro-display device of volume very little, in order to improve integrated level, saves interconnection resource on piece, and low-bit width is used microdisplay on silicon more
Video data so that imaging Quality Down.The present invention passes through piece by designing gray level expanded circuit on microdisplay on silicon piece
Upper video data latch cicuit, extends one times by the bit wide of video data, can significantly improve the gray level of image, make image
The stereovision of brightness and color is significantly improved, particularly in the case where needing high grade grey level wearable display, such as
Medical wearable display field, has great application prospect.It can be applied to silicon-base liquid crystal display device, silicon-based organic light-emitting
Display device etc..
Brief description of the drawings
Fig. 1 is gray level expanded circuit structure chart on microdisplay on silicon piece；
Fig. 2 is scanning sequence control circuit structure diagram；
Fig. 3 is expansible DATA REG circuitry structure chart；
Fig. 4 is expansible data register element circuit structured flowchart.
Embodiment
Gray level expanded circuit in embodiment 1, a kind of microdisplay on silicon piece
As shown in figure 1, gray level expanded circuit is by scanning sequence control on a kind of microdisplay on silicon piece that the present invention is provided
Circuit 1 processed, shift-register circuit 2, expansible DATA REG circuitry 3, digital analog converter 4 and analog signal output buffering electricity
Road 5 is constituted；Described scanning sequence control circuit 1 has two inputs, respectively with outside line synchronising signal and pixel clock
Signal is connected, and its output end has four, respectively with two inputs of shift-register circuit 2 and expansible data register electricity
Two inputs on road 3 are connected；Two inputs of described shift-register circuit 2 control the two of circuit 1 with scanning sequence
Individual output end is connected, and its N road control line output terminal is connected with the N roads control line input of expansible DATA REG circuitry 3；Institute
The input for the expansible DATA REG circuitry 3 stated has five, and one of input is N roads control line and shift register
The N roads control line output terminal of circuit 2 is connected, and another input is that M digital video data input pins are connected to outside, and its excess-three is defeated
Enter end controls two output ends of circuit 1 and outside gray level control signal input to be connected with sequence scanning respectively, expansible number
It is N roads 2M position datawires according to the output end of register circuit, is connected with 2M, the N roads data input pin of digital analog converter 4；It is described
The input of digital analog converter 4 have two, respectively with outside 8 tunnels simulation step power supply and expansible DATA REG circuitry
3 2M, N roads data output end is connected, and the output end of digital analog converter is believed with the N roads simulation of analog signal output buffer circuit 5
Number input is connected；The N roads analog signal of the input of described analog signal output buffer circuit 5 and digital analog converter 4 is defeated
Go out end to be connected, its output end is communicated with the outside.
As shown in Fig. 2 described scanning sequence control circuit 1 is sentenced by monopulse generator 6, linage-counter 7, height word bit
Deenergizing 8 and pulse synchronization circuit 9 are constituted；The input of monopulse generator 6 is connected with outside line synchronising signal, its output end
It is connected with an input of pulse synchronization circuit 9；The input of linage-counter 7 is connected with external pixels clock signal, and its is defeated
Going out end has three, respectively with can in the input, the input of height word bit decision circuitry 8 and Fig. 1 of pulse synchronization circuit 9
One input of growth data register circuit 3 is connected；Two output ends of pulse synchronization circuit 9 and shift LD in Fig. 1
Two inputs of device circuit 2 are connected；Expansible DATA REG circuitry 3 in the output end and Fig. 1 of height word bit decision circuitry 8
An input be connected.
As shown in figure 3, described expansible DATA REG circuitry 3 is locked by N number of element circuit 11 and N number of unit second level
Storage 10 is constituted；One input C1 of all element circuits all connect together and with Fig. 1 scanning sequence control circuit 1 one
Individual output end is connected；Second input C3 connects together and is connected with the input of outside gray level control signal；N number of unit electricity
The M digital video data wire inputs on road 11 are connected to outside, 2M digital video data line output terminals and the N number of list of N number of element circuit 11
The 2M digital video data wires input of first each unit circuit of second level latch 10 is connected；Latch described N number of unit second level
One input C2 of device 10 connects together and is connected with an output end of scanning sequence control circuit 1 in Fig. 1, and 2M regard
Frequency data wire input is connected with the 2M digital video data line output terminals of N number of element circuit 11, N number of unit second level latch 10
N roads 2M digital video data line output terminals be connected with the N roads 2M position datawire inputs of the digital analog converter 4 shown in Fig. 1.
The implementation of embodiment 2, expansible data register element circuit
As shown in figure 4, the element circuit 11 of described expansible DATA REG circuitry 3 by M single-pole double-throw switch (SPDT)s 13,
M gate controlled switches 12 and 2M data latches 14 are constituted；The one group of common port that is, M-bit data of M single-pole double-throw switch (SPDT)s 13
Input is connected with outside M-bit data line, low M inputs of the normally closed point of M single-pole double-throw switch (SPDT)s and 2M data latches
End is connected, and the opened point of M single-pole double-throw switch (SPDT)s is connected with the M positions input of M gate controlled switches；M single-pole double-throw switch (SPDT)s
Control end controls an output end C1 of circuit to be connected with scanning sequence；The M position output ends of M gate controlled switches are locked with 2M data
High M inputs of storage are connected；Another input of M gate controlled switches and outside gray level control signal input C3 phases
Even；Wherein 2M position datawires are connected the 2M position output ends of 2M data latches all the way with digital analog converter N roads input.
The implementation method of gray level expanded circuit in embodiment 3, a kind of microdisplay on silicon piece
The implementation method of gray level expanded circuit function, is sequentially passed through on a kind of microdisplay on silicon piece that the present invention is provided
Following steps：
The firstth, outside gray level control signal is set, and C3=0 is low grey-scale modes, and C3=1 is high grade grey level pattern；
As C3=0, between the high period of C1 signals, M gate controlled switches 12 are closed, each 2M data latches 14
High M can not write data, be M low grey-scale modes；As C3=1, between the high period of C1 signals, M gates
Switch 12 is opened, and 2M data latches 14 high M and low M can write data, be 2M high grade grey level patterns, utilize
M-bit data line realizes 2M high grade grey levels；
Secondth, scanning sequence controls circuit 1 under outer row synchronization and the control of pixel clock signal, produces shift LD
Displacement enabling signal HS, the shift clock CLK and the write control signal C1 of expansible DATA REG circuitry 3 of device circuit 2, displacement
Clock CLK and control signal C1 are the two divided-frequencies of external pixels clock signal；Effect of the shift-register circuit 2 in shift clock
Under, output N roads control signal, and it is sequentially output from 1 to N a high level；
3rd, expansible DATA REG circuitry 3 is under the output signal control of shift-register circuit 2, each CLK weeks
Phase latches a 2M bit digital vision signal in two times, and M digital videos data are write into each 2M between the low period of C1 signals
Next M digital videos data are passed through M gate controlled switches by low M of position data latches 14 between the high period of C1 signals
High M of the 12 each 2M data latches 14 of write-in；
4th, under the output signal control of shift-register circuit 2, from 1 to N, expansible DATA REG circuitry 3
First module is completed to the 2M positions data latches 14 of N units after the latch to a line vision signal, scanning sequence control
The output signal C2 of circuit 1 produces a high pulse signal, the data of all units is sent to N number of 2M second level latch 10；
5th, the data being sent in N number of 2M second level latch 10 are directly output to N roads 2M digits weighted-voltage D/A converter 4, profit
With the multi-channel analog step power supply of outside input to carrying out digital-to-analogue conversion, the simulation of output N roads simultaneously per 2M digital videos data all the way
Voltage；Be output to back-end circuit after the processing of analog signal output buffer circuit 5 again, complete a line vision signal scanning and
Output；
6th, wait next line synchronising signal to arrive, repeat.
Embodiment 4,6 digital video data/address bus are extended to implementing for 12 grayscale images in piece
For the microdisplay on silicon of 1920x1080 resolution ratio, N=1920, external video data bus is 6, M=6.
Line synchronising signal is waited to arrive, scanning sequence control circuit 1 output HS and CLK signal, driving shift register electricity
The first via of 1920 road control lines is exported high level by road 2, other 1919 road control line output low levels, now expansible data
The first module circuit of register circuit 3 is selected and enabled, and other element circuits are unselected；Outside gray level extension control is set
Signal C3=1 processed, makes at the M positions gate controlled switch 12 of the first module circuit of N element circuits 11 of expansible DATA REG circuitry 3
In open mode；Scanning sequence controls circuit 1 to drive C1 signals to be low level, under the controller of outside pixel clock, by one
The video data of individual 6 writes the low 6 of 2M data latches 14；Then scanning sequence control circuit 1 drive C1 signals be
High level, under the controller of outside pixel clock, the video data of second 6 is write the height of 2M data latches 14
6；When C1 signals are changed into low level again, 12 digital video data are latched into Unit the 1st of N units second level latch 10
In, and start simultaneously at the write-in to Unit the 2nd；
Operate successively, 1920 units of N units second level latch 10 are write, that is, complete writing for data line
Enter；It is high level that scanning sequence, which controls circuit 1 to export C2 signals, afterwards, makes 12 in 1920 N units second level latch 10
Position data are output to mode converter 4, are turned the digital video data-signal of 1920 tunnel 12 using the multichannel step power supply of outside input
Change 1920 road analog video signals into, then be output to through analog signal output buffer circuit 5 display pixel matrix of outside.
Circulate operation, completes the processing of whole image picture data.
Embodiment 5,4 digital video data/address bus are extended to implementing for 8 grayscale images in piece
For the microdisplay on silicon of 800x600 resolution ratio, N=800, external video data bus is 4, M=4.
Line synchronising signal is waited to arrive, scanning sequence control circuit 1 output HS and CLK signal, driving shift register electricity
The first via of 800 road control lines is exported high level by road 2, other 799 road control line output low levels, and now expansible data are posted
The first module circuit of latch circuit 3 is selected and enabled, and other element circuits are unselected；Outside gray level extension control is set
Signal C3=1, is in the M positions gate controlled switch 12 of the first module circuit of N element circuits 11 of expansible DATA REG circuitry 3
Open mode；Scanning sequence controls circuit 1 to drive C1 signals to be low level, under the controller of outside pixel clock, by one 4
The video data of position writes the low 4 of 2M data latches 14；Then scanning sequence controls circuit 1 to drive C1 signals to be high electricity
It is flat, under the controller of outside pixel clock, by the high 4 of second 4 video data 2M data latches 14 of write-in；
When C1 signals are changed into low level again, 8 digital video data are latched into Unit the 1st of N units second level latch 10, and together
When start the write-in to Unit the 2nd；
Operate successively, 800 units of N units second level latch 10 are write, that is, complete the write-in of data line；
It is high level that scanning sequence, which controls circuit 1 to export C2 signals, afterwards, makes 8 data in 800 N units second level latch 10
Mode converter 4 is output to, the digital video data-signal of 800 tunnel 8 is converted into 800 tunnels using the multichannel step power supply of outside input
Analog video signal, then through analog signal output buffer circuit 5 be output to outside display pixel matrix.
Circulate operation, completes the processing of whole image picture data.
Claims (5)
1. gray level expanded circuit on a kind of microdisplay on silicon piece, it is characterised in that the circuit includes：Scanning sequence control electricity
Road, shift-register circuit, expansible DATA REG circuitry, digital analog converter and analog signal output buffer circuit；
Described scanning sequence control circuit has two inputs, respectively with outside line synchronising signal and pixel clock signal phase
Even, its output end has four, wherein, two of write control signal output end C1 and C2 and expansible DATA REG circuitry are defeated
Enter end to be connected, two inputs of displacement enabling signal output end HS and shift clock output end CLK and shift-register circuit
It is connected；Two inputs of described shift-register circuit control two output ends of circuit to be connected with scanning sequence, its N road
Control line output terminal is connected with the N roads control line input of expansible DATA REG circuitry, and wherein N is according to monitor resolution
It is determined that；The input of described expansible DATA REG circuitry has five, and one of input is N roads control line and displacement
The N roads control line output terminal of register circuit is connected, and another input is that M digital video data input pins are connected to outside, the 3rd
Individual input C3 is connected with outside gray level control signal, and other two input controls two of circuit with sequence scanning respectively
Output end C1 is connected with C2, and the output end of expansible DATA REG circuitry is N roads 2M position datawires, the N with digital analog converter
Road 2M data input pin is connected；The input of described digital analog converter has two groups, respectively with outside 8 tunnels simulation step electricity
Source is connected with 2M, the N roads data output end of expansible DATA REG circuitry, the output end and analog signal of digital analog converter
The N roads input end of analog signal of output buffer is connected；The input and digital-to-analogue of described analog signal output buffer circuit
The N roads analog signal output of converter is connected, and output end is communicated with the outside.
2. gray level expanded circuit on microdisplay on silicon piece according to claim 1, it is characterised in that described scanning
Sequential control circuit includes monopulse generator, linage-counter, height word bit decision circuitry and pulse synchronization circuit；Pulse is sent out
The input of raw device is connected with outside line synchronising signal, and output end is connected with an input of pulse synchronization circuit；Row is counted
The input of device is connected with external pixels clock signal, and the output end of linage-counter has three, respectively with pulse synchronization circuit
One input phase of one input, the input of height word bit decision circuitry and described expansible DATA REG circuitry
Even；Two output ends of pulse synchronization circuit are connected with two inputs of described shift-register circuit；Height word bit is sentenced
The output end of deenergizing is connected with an input of described expansible DATA REG circuitry.
3. gray level expanded circuit on microdisplay on silicon piece according to claim 1, it is characterised in that described expands
Opening up DATA REG circuitry includes N number of element circuit and N number of unit second level latch；One of described N number of element circuit
Input C1 connects together and is connected with an output end of described scanning sequence control circuit, and second input C3 is
Connect together and be connected with the input of outside gray level control signal, the M digital video data wire inputs of N number of element circuit are connected to outside
Portion, the 2M digital videos of the 2M digital video data line output terminals of N number of element circuit and N number of unit second level latch each unit circuit
Data wire input is connected；One input C2 of described N number of unit second level latch all connect together and with it is described
One output end of scanning sequence control circuit is connected, the 2M digital videos of 2M digital video data wire inputs and N number of element circuit
Data line output terminal is connected, 2M digital video data line output terminals and the described digital analog converter of N number of unit second level latch
N roads 2M position datawires input be connected.
4. gray level expanded circuit on microdisplay on silicon piece according to claim 3, it is characterised in that described expands
In the element circuit for opening up DATA REG circuitry, each element circuit includes M single-pole double-throw switch (SPDT)s, M gate controlled switches
With 2M data latches；One group of common port that is, M-bit data input and outside M-bit data in M single-pole double-throw switch (SPDT)s
Line is connected, and the low M each inputs of the normally closed points of M single-pole double-throw switch (SPDT)s respectively with 2M data latches are connected, M hilted broadswords
M position each input of the opened point of commutator respectively with M gate controlled switches is connected；The control end of M single-pole double-throw switch (SPDT)s with
One output end C1 of described scanning sequence control circuit is connected；The M positions output end of M gate controlled switches respectively with 2M data
High M each inputs of latch are connected；Another input of M gate controlled switches and outside gray level control signal input
C3 is connected；The 2M position output ends of 2M data latches and the N roads input of described digital analog converter wherein 2M digits all the way
It is connected according to line.
5. the implementation method of gray level expanded circuit, is sequentially passed through down on the microdisplay on silicon piece described in a kind of claim 1
State step：
The firstth, outside gray level control signal is set, and C3=0 is low grey-scale modes, and C3=1 is high grade grey level pattern；
As C3=0, between the high period of C1 signals, M gate controlled switches are closed, high M of each 2M data latches
Data can not be write, are M low grey-scale modes；As C3=1, between the high period of C1 signals, M gate controlled switches are beaten
Open, high M and low M of 2M data latches can write data, be 2M high grade grey level patterns, utilize M-bit data line
Realize 2M high grade grey levels；
Secondth, scanning sequence controls circuit under outer row synchronization and the control of pixel clock signal, produces shift register electricity
Displacement enabling signal HS, the shift clock CLK and expansible DATA REG circuitry write control signal C1 on road, shift clock
CLK and control signal C1 are the two divided-frequencies of external pixels clock signal；Shift-register circuit is defeated in the presence of shift clock
Go out N roads control signal, and be sequentially output from 1 to N a high level；
3rd, expansible DATA REG circuitry is under the output signal control of shift-register circuit, and each clk cycle is divided to two
M digital videos data are write each 2M data by one 2M bit digital vision signal of secondary latch between the low period of C1 signals
Low M of latch, are write next M digital videos data each by M gate controlled switches between the high period of C1 signals
High M of 2M data latches；
4th, under the output signal control of shift-register circuit, from 1 to N, the first of expansible DATA REG circuitry is single
After member is completed to the latch of a line vision signal to the 2M positions data latches of N units, scanning sequence control circuit output
Signal C2 produces a high pulse signal, the data of all units is sent to N number of 2M second level latch；
5th, the data being sent in N number of 2M second level latch are directly output to N roads 2M digit weighted-voltage D/A converters, utilize outside
The multi-channel analog step power supply of input is to carrying out digital-to-analogue conversion, output N roads analog voltage per 2M digital videos data all the way simultaneously；Again
Back-end circuit is output to after the processing of analog signal output buffer circuit, the scanning and output of a line vision signal is completed；
6th, wait next line synchronising signal to arrive, repeat.
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| CN111968567B (en) * | 2020-08-31 | 2022-02-25 | 上海天马微电子有限公司 | Display panel and electronic equipment |
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