CN104867977A - Semiconductor Device And Method Of Fabricating The Same - Google Patents

Semiconductor Device And Method Of Fabricating The Same Download PDF

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Publication number
CN104867977A
CN104867977A CN201510035301.2A CN201510035301A CN104867977A CN 104867977 A CN104867977 A CN 104867977A CN 201510035301 A CN201510035301 A CN 201510035301A CN 104867977 A CN104867977 A CN 104867977A
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China
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district
concentration
semiconductor device
semiconductor substrate
fin
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CN201510035301.2A
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CN104867977B (en
Inventor
林夏珍
金亨俊
李来寅
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Samsung Electronics Co Ltd
Seoul National University Industry Foundation
SNU R&DB Foundation
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Samsung Electronics Co Ltd
Seoul National University Industry Foundation
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/783—Field effect transistors with field effect produced by an insulated gate comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention provides a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.

Description

Semiconductor device and manufacture method thereof
Technical field
The present invention's design relates to semiconductor device and manufacture method thereof.
Background technology
In order to improve the mobility of charge carrier, for the technology that III-V can be utilized to form the raceway groove of transistor, be studied.
But, if the gate insulator with high-k (height-K) is formed directly in III-V, then may form unstable interface.Therefore, when operating, transistor can have highdensity interface trapped charge (DIT), and this makes the performance degradation of transistor.
Summary of the invention
Some execution modes of the present invention's design provide a kind of semiconductor device with the product reliability of raising.
Some execution modes of the present invention's design also provide a kind of manufacture to have the method for the semiconductor device of the product reliability of raising.
According to the one side of the present invention's design, provide a kind of semiconductor device.This semiconductor device comprises: Semiconductor substrate, comprises III element and V group element; And grid structure, on a semiconductor substrate.Semiconductor substrate comprises: the firstth district, the basal surface of contact grid structure; And secondth district, be arranged under the firstth district.The concentration of III element in the firstth district is lower than the concentration of V group element in the firstth district, and III element concentration is in the second region substantially equal to V group element concentration in the second region.
In some embodiments, III element is at least one in Ga, In and Al, and V group element is at least one in P, As and Sb.
In some embodiments, the concentration of III element in the firstth district increases from the top surface in the firstth district towards the basal surface in the firstth district.
In some embodiments, III element is 10% or less in the concentration at the top surface place in the firstth district.
In some embodiments, the top surface in the firstth district comprises 5% or less oxygen atom.
In some embodiments, the firstth district has the thickness of 1 to 20nm.
In some embodiments, grid structure comprises the gate insulator in contact first district and the gate electrode be arranged on gate insulator.
In some embodiments, gate insulator is recessed shape, and gate electrode is arranged on gate insulator.
In some embodiments, this semiconductor device also comprises the source/drain regions of the one side or the multi-lateral of setting in the semiconductor substrate in the first and secondth district.
In some embodiments, the firstth district and source/drain regions spaced apart.
In some embodiments, this semiconductor device also comprises the substrate be arranged under Semiconductor substrate.
In some embodiments, substrate does not comprise III element and V group element.
According to the another aspect of the present invention's design, provide a kind of semiconductor device.This semiconductor device comprises: substrate; Fin, projects upwards from substrate in a first direction, and comprises the first material and the second material; And on fin the grid structure crossing with fin.Fin comprises setting channel region under the gate structure, and the concentration of the first material in channel region increases from the surface of channel region towards the inside of channel region.
In some embodiments, the first material comprises III element, and the second material comprises V group element.
In some embodiments, the concentration of the second material in channel region reduces from the surface of channel region towards the inside of channel region.
In some embodiments, the difference between the concentration of the first material and the concentration of the second material reduces from the surface of channel region towards the inside of channel region.
In some embodiments, in the surface of channel region, the concentration of the second material is higher than the concentration of the first material.
In some embodiments, the concentration of the first material in the surface of channel region is 10% or less.
In some embodiments, grid structure comprises the gate insulator of contact channel region and the gate electrode be arranged on gate insulator.
In some embodiments, this semiconductor device also comprises the cover layer of cover gate electrode.
In some embodiments, this semiconductor device also comprises the source/drain regions be formed in the one side or the multi-lateral of grid structure in fin, and wherein in the surface of the contact source/drain regions of fin, the concentration of the first material is substantially equal to the concentration of the second material.
According to the another aspect of the present invention's design, provide a kind of method manufacturing semiconductor device.The method comprises: provide the Semiconductor substrate comprising III element and V group element; Oxide skin(coating) is formed by the top surface of oxide-semiconductor substrate; Remove oxide skin(coating); And form grid structure on a semiconductor substrate.
In some embodiments, III element is at least one in Ga, In and Al, and V group element is at least one in P, As and Sb.
In some embodiments, before the method is also included in and forms oxide skin(coating), remove native oxide layer by cleaning the top surface of Semiconductor substrate.
In some embodiments, oxide skin(coating) comprises the oxide of the III element more than the oxide of V group element.
In some embodiments, the top surface of oxide-semiconductor substrate is included in 5atm or higher and at the top surface 30 minutes to 2 hours of 300 DEG C or more high oxidation Semiconductor substrate.
In some embodiments, the top surface of oxide-semiconductor substrate is included in the top surface 30 minutes to 2 hours of oxide-semiconductor substrate under 600 DEG C or higher high temperature.
In some embodiments, after removal oxide skin(coating), at the top surface place of Semiconductor substrate, the concentration of V group element is higher than the concentration of III element.
In some embodiments, form grid structure also comprise the gate insulator of formation contact semiconductor substrate and form gate electrode on gate insulator.
In some embodiments, remove oxide skin(coating) comprise utilize wet etching remove oxide skin(coating).
In some embodiments, the method also comprises: before formation oxide skin(coating), form source/drain regions in the semiconductor substrate, wherein form oxide skin(coating) and comprise and form oxide skin(coating) by the top surface between source/drain regions of oxide-semiconductor substrate.
According to the another aspect of the present invention's design, provide a kind of method manufacturing semiconductor device.The method comprises: form fin, fin projects upwards from substrate and comprises the first material and the second material with substantially equal concentration; The channel region of cleaning fin; Oxide skin(coating) is formed by the channel region being oxidized fin; Channel region is exposed by removing oxide skin(coating); And form grid structure to cover channel region.Form the first material that oxide skin(coating) comprises the oxidation fin more than the second material of fin, in the surface of channel region, the concentration of the second material is higher than the concentration of the first material.
In some embodiments, the first material comprises III element, and the second material comprises V group element.
In some embodiments, channel region is oxidized at 5atm or higher and 300 DEG C or higher execution 30 minutes to 2 hours.
In some embodiments, the method also comprises: after the fins are formed, is formed crossing with fin and covers the dummy gate electrode structure of channel region; Source/drain regions is formed in the one side or the multi-lateral of dummy gate electrode structure; And the channel region of fin is exposed by removing dummy gate electrode structure.
In some embodiments, form grid structure to comprise: form the gate insulator on the surface of contact channel region and form gate electrode on gate insulator.
According to the another aspect of the present invention's design, provide a kind of semiconductor device.This semiconductor device comprises: Semiconductor substrate, comprises III element and V group element; And grid structure, on a semiconductor substrate.Semiconductor substrate comprises: the firstth district, the basal surface of contact grid structure; And secondth district, be arranged under the firstth district.In the surface of Semiconductor substrate, the concentration of V group element is higher than the concentration of III element.
In some embodiments, the concentration of III element in the firstth district increases from the top surface in the firstth district towards the basal surface in the firstth district.
In some embodiments, III element concentration is in the second region substantially equal to V group element concentration in the second region.
In some embodiments, the concentration of III element in the firstth district is lower than the concentration of V group element in the firstth district.
In some embodiments, III element is at least one in Ga, In and Al, and V group element is at least one in P, As and Sb.
Accompanying drawing explanation
By the more specifically description of the preferred implementation from the present invention's design such as shown in accompanying drawing, obviously, Reference numeral identical in the accompanying drawings refers to identical parts throughout different views to the above and other feature and advantage of the present invention's design.Accompanying drawing need not be drawn in proportion, but focuses on the principle illustrating that the present invention conceives.
Fig. 1 is the sectional view of semiconductor device of the example embodiment according to the present invention's design.
Fig. 2 is the sectional view of semiconductor device of the example embodiment according to the present invention's design.
Fig. 3 is the sectional view of semiconductor device of the example embodiment according to the present invention's design.
Fig. 4 is the sectional view of semiconductor device of the example embodiment according to the present invention's design.
Fig. 5 is the sectional view of semiconductor device of the example embodiment according to the present invention's design.
Fig. 6 is the perspective view of semiconductor device of the example embodiment according to the present invention's design.
Fig. 7 and Fig. 8 is the sectional view of semiconductor device of Fig. 6 of example embodiment according to the present invention's design.
Fig. 9 is the perspective view of semiconductor device of the example embodiment according to the present invention's design.
Figure 10 is the perspective view of semiconductor device of the example embodiment according to the present invention's design.
Figure 11 and Figure 12 is the sectional view of the semiconductor device of Figure 10.
Figure 13 and Figure 14 is respectively circuit diagram and the layout of semiconductor device, and this semiconductor device comprises any one in the semiconductor device of the Fig. 1 to Figure 12 manufactured according to the example embodiment of the present invention's design.
Figure 15 is the block diagram of electronic system, and this electronic system comprises any one in the semiconductor device of the Fig. 1 to Figure 12 manufactured according to the example embodiment of the present invention's design.
Figure 16 and Figure 17 is the diagram of the example that semiconductor system is shown, the semiconductor device according to Fig. 1 to Figure 12 of the example embodiment manufacture of the present invention's design can be applied to this semiconductor system.
Figure 18, Figure 20, Figure 21, Figure 22, Figure 24, Figure 26 and Figure 27 are the sectional view of the step of the method for the semiconductor device of the shop drawings 1 of the execution mode illustrated according to the present invention's design.
Figure 19 is the curve chart of the concentration of the Semiconductor substrate of the Figure 18 of the execution mode illustrated according to the present invention's design.
Figure 23 is the curve chart of the concentration of the Semiconductor substrate of the Figure 22 of the execution mode illustrated according to the present invention's design.
Figure 25 is the curve chart of the concentration illustrated according to the first material in firstth district of Semiconductor substrate of the example embodiment of the present invention's design and the secondth district and the second material.
Figure 28 is the curve chart that the effect that the present invention conceives is shown.
Figure 29 to Figure 35 is the sectional view of the step of the method for the semiconductor device of the shop drawings 3 of the example embodiment illustrated according to the present invention's design.
Figure 36 to Figure 39 and Figure 55 is the perspective view of the step of the method for the semiconductor device of the shop drawings 6 of the example embodiment illustrated according to the present invention's design.
Figure 40, Figure 42, Figure 43, Figure 45, Figure 47, Figure 49, Figure 51 and Figure 53 are the sectional view intercepted along the line A-A of Figure 39.
Figure 41, Figure 44, Figure 46, Figure 48, Figure 50, Figure 52 and Figure 54 are the sectional view intercepted along the line B-B of Figure 39.
Figure 56 is the sectional view intercepted along the line A-A of Figure 55.
Figure 57 is the sectional view intercepted along the line B-B of Figure 55.
Embodiment
Hereafter with reference to the accompanying drawings different example embodiment is more fully being described, example embodiment more shown in the drawings.But the present invention's design can be implemented in many different forms, and should not be understood to be limited to execution mode set forth herein.
Term is only for describing concrete example embodiment as used herein, and is not intended to limit the present invention's design.When using at this, singulative " " and " being somebody's turn to do " are intended to also comprise plural form, unless context clearly represents separately.Will be further understood that, when term " comprises " and/or " comprising " is used in this manual, it represents the existence of described feature, integer, step, operation, element and/or parts, but does not get rid of one or more further feature, integer, step, operation, element, the existence of parts and/or its group or interpolation.
To understand, when an element or layer be called as " " another element or layer " on ", " being connected to " or " being connected to " another element or layer time, it can directly on another element or layer, be directly connected to or be directly connected to another element or layer, or intervening elements or layer can be there is.On the contrary, when an element or layer be called as " directly existing " another element or layer " on ", " being directly connected to " or " being directly connected to " another element or layer time, then there is no intervening elements or layer.Identical Reference numeral refers to identical element all the time.When using at this, term "and/or" comprises one or more any and all combinations of associated listed items.
To understand, although term first, second etc. can be used to this to describe different elements, assembly, region, layer and/or part, these elements, assembly, region, layer and/or part should not limit by these terms.These terms are only used to differentiation element, assembly, region, layer or part and another element, assembly, region, layer or part.Thus, the first element discussed below, assembly, region, layer or part can be called as the second element, assembly, region, layer or part, and do not depart from the instruction of the present invention's design.
For convenience of description, can in this usage space relational terms, such as " ... below ", " ... under ", D score, " ... on ", " on " etc. an element or feature and another element (or multiple element) or feature (or multiple feature) relation are as illustrated in the drawing described.To understand, spatial relationship term is intended to comprise except the orientation described in figure, device different orientation in use or operation.Such as, if device is in the drawings reversed, be then described as be in other element or feature " under " or the element of " below " can be oriented to other element described or feature " on ".Thus, exemplary term " ... under " upper and lower two kinds of orientations can be contained.Device can by additionally orientation (90-degree rotation or other orientation), and spatial relation description language can be interpreted accordingly as used herein.
Describe example embodiment at this with reference to cross section diagram, wherein cross section diagram is the indicative icon of Utopian example embodiment (and intermediate structure).Therefore, the departing from of diagram shape caused due to such as manufacturing technology and/or tolerance it is expected to.Thus, example embodiment should not be understood to the given shape in the region be limited to shown in this, but will comprise such as by manufacturing the departing from of shape caused.Such as, the injection region being illustrated as rectangle generally will have the gradient of sphering or bending feature and/or implantation concentration at its edge, instead of the binary change from injection region to non-injection regions.Similarly, by inject formed imbed district and can cause imbedding district and some inject by region between the surface injected occurs for it.Thus, the region illustrated in the drawings is schematic in essence, and their shape is not intended to the true form in the region that device is shown, and is not intended to the scope limiting the present invention's design.
Although the respective planes figure of some sectional views and/or perspective view may not be illustrated, but the sectional view of the device architecture shown in this provides the support for multiple device architecture, the plurality of device architecture as by extend along two different directions illustrating in plan view and/or as by illustrating in the perspective along three different direction extensions.Described two different directions can be orthogonal or can not be orthogonal.Described three different directions can comprise third direction that can be orthogonal from described two different directions.Multiple device architecture can be integrated in same electronic device.Such as, when device architecture (such as, memory cell structure or transistor arrangement) is illustrated in the sectional views, electronic device can comprise multiple device architecture (such as, memory cell structure or transistor arrangement), as shown in by the plane graph by electronic device.Multiple device architecture can be arranged to array and/or two-dimensional pattern.
The semiconductor device of the example embodiment according to the present invention's design is described now with reference to Fig. 1 and Figure 25.
Fig. 1 is the sectional view of semiconductor device 1 of the example embodiment according to the present invention's design.Figure 25 is the curve chart of the concentration of the first and second materials illustrated in the first area 23 of Semiconductor substrate 21 and second area 25.
With reference to Fig. 1, Semiconductor substrate 1 can comprise Semiconductor substrate 21, grid structure 40 and source/drain regions 51.
Semiconductor substrate 21 can comprise the first material and the second material.First material can be such as III element, and the second material can be such as V group element.III element can be at least one in such as Ga, In and Al.V group element can be at least one in such as P, As and Sb.Therefore, Semiconductor substrate 21 can be made up of at least one in such as GaAs, InGaAs, AlGaAs, InAs, GaSb, InSb and InP.
The concentration of the first material that Semiconductor substrate 21 comprises and the second material can change according to the position in Semiconductor substrate 21.Second material is greater than the concentration of the first material at the top surface of Semiconductor substrate 21 in the concentration of the top surface of Semiconductor substrate 21.Along with the degree of depth the top surface from Semiconductor substrate 21 increases, the concentration of the first material can increase and the concentration of the second material can reduce.Certain depth place the top surface from Semiconductor substrate 21, the concentration of the first material can be substantially equal to the concentration of the second material.
Specifically, Semiconductor substrate 21 comprises the first district 23 and the second district 25.First district 23 can be positioned at the top surface place of Semiconductor substrate 21, and the second district 25 can be arranged under the first district 23.First district 23 contacts grid structure 40.First district 23 can have the thickness of such as 1-20nm.
With reference to Figure 25, in the first district 23, the concentration of the first material increases gradually from the top surface in the first district 23 towards the basal surface in the first district 23.Namely, the first material is less than the concentration of the first material in the bottom surface in the first district 23 in the concentration at the top surface place in the first district 23.First material is 10% or less in the concentration at the top surface place in the first district 23.In the first district 23, the concentration of the first material is lower than the concentration of the second material.
In the first district 23, the concentration of the second material is higher than the concentration of the first material.Namely, in the top surface place in the first district 23 and the bottom surface in the first district 23, the concentration of the second material is higher than the first material.But the concentration of the second material reduces towards the basal surface in the first district 23, and the difference between the concentration of the second material and the concentration of the first material reduces towards the basal surface in the first district 23.
First district 23 can comprise some oxygen atoms.Oxygen atom can reduce from the top surface in the first district 23 towards the basal surface in the first district 23, and no longer can be present in the certain depth place from the top surface in the first district 23.Namely, the oxygen atom at the top surface place in the first district 23 is more than the oxygen atom of the bottom surface in the first district 23.At the top surface place in the first district 23, the concentration of oxygen atom can be 5% or less.
In the second district 25, the concentration of the first material can be substantially equal to the concentration of the second material.Here, term " substantially " not only represents accurately identical, and allows the surplus of contingent error during technique.Therefore, as shown in figure 25, the concentration of the first material and the concentration of the second material can be unequal in the some parts in the second district 25.
In the second district 25, oxygen atom can exist hardly, as shown in figure 25.
Again with reference to Fig. 1, grid structure 40 can be arranged in Semiconductor substrate 21.Grid structure 40 can be arranged in the first district 23 of Semiconductor substrate 21.Grid structure 40 can comprise gate insulator 41, gate electrode 43 and hard mask layer 45.
Gate insulator 41 can be arranged in Semiconductor substrate 21.Gate insulator 41 can contact semiconductor substrate 21.Gate insulator 41 can the first district 23 of contact semiconductor substrate 21.Gate insulator 41 can comprise and being selected from by such as HfSiON, HfO 2, ZrO 2, Al 2o 3, Ta 2o 5, TiO 2, SrTiO 3(Ba, Sr) TiO 3the material of the group formed.Alternatively, gate insulator 41 can be silicon oxide layer.
Gate electrode 43 can be arranged on gate insulator 41.Gate electrode 43 can comprise electric conducting material such as polysilicon.
Hard mask layer 45 can be arranged on gate electrode 43.Hard mask layer 45 can comprise at least one in such as oxide skin(coating), nitride layer and oxynitride layer.
Source/drain regions 51 can be arranged on the one side or the multi-lateral of grid structure 40.Source/drain regions 51 can be formed in Semiconductor substrate 21.Source/drain regions 51 can be formed in contiguous first district 23 and the second district 25 in Semiconductor substrate 21.
If semiconductor device 1 is P-channel metal-oxide-semiconductor (PMOS) transistor, then source/drain regions 51 can comprise the material with the lattice constant larger than Semiconductor substrate 21.Alternatively, if semiconductor device 1 is N NMOS N-channel MOS N (NMOS) transistor, then source/drain regions 51 can comprise the material with the lattice constant less than Semiconductor substrate 21.
Sept 47 can be arranged on the one side or the multi-lateral of grid structure 40.Sept 47 can one or more sidewalls of overlies gate structure 40.Each sept 47 can be at least one in such as silicon oxide layer, silicon-nitride layer and silicon oxynitride layer.
Sept 47 can be formed in the first district 23.
The semiconductor device 2 of the example embodiment according to the present invention's design is described now with reference to Fig. 2.For simplicity, the description of substantially the same with the element of the aforementioned embodiments of Fig. 1 element will be omitted.Hereinafter by describing the current embodiment of Fig. 2, mainly concentrate on in the difference of the aforementioned embodiments of Fig. 1.
Fig. 2 is the sectional view of semiconductor device 2 of the example embodiment according to the present invention's design.
The semiconductor device 2 of Fig. 2 can be identical with the semiconductor device 1 of Fig. 1 in Semiconductor substrate 21, grid structure 40 and source/drain 51.Therefore, as semiconductor device 1, the Semiconductor substrate 21 of semiconductor device 2 comprises the first district 23 and the second district 25.In semiconductor device 2, Semiconductor substrate 21 comprises the first material such as III element and the second material such as V group element.The concentration of the first material increases from the top surface in the first district 23 towards the basal surface in the first district 23.Namely, the first material is less than the concentration of the first material in the bottom surface in the first district 23 in the concentration at the top surface place in the first district 23.In the first district 23 of semiconductor device 2, the concentration of the first material is lower than the concentration of the second material, and in the second district 25 of semiconductor device 2, the concentration of the first material is substantially equal to the concentration of the second material.
Except the element of the semiconductor device 1 of Fig. 1, the semiconductor device 2 of Fig. 2 can also comprise substrate 11.Substrate 11 can be arranged under Semiconductor substrate 21.Substrate 11 can be made up of one or more semi-conducting materials being such as selected from the group be made up of Si, Ge, SiGe, SiC and SiGeC.Substrate 11 also can be such as silicon-on-insulator (SOI) substrate.Namely, substrate 11 can not comprise III element and V group element.
The semiconductor device of the example embodiment according to the present invention's design is described now with reference to Fig. 3 and Figure 25.
Fig. 3 is the sectional view of semiconductor device 3 of the example embodiment according to the present invention's design.
With reference to Fig. 3, semiconductor device 3 can comprise Semiconductor substrate 22, grid structure 39, regions and source/drain 52 and contact 76.
Semiconductor substrate 22 can the first material and the second material.First material can be such as III element, and the second material can be such as V group element.III element can be at least one in such as Ga, In and Al.V group element can be at least one in such as P, As and Sb.Therefore, Semiconductor substrate 22 can be made up of at least one in such as GaAs, InGaAs, AlGaAs, InAs, GaSb, InSb and InP.
The concentration of the first material that Semiconductor substrate 22 comprises and the second material can change according to the position in Semiconductor substrate 22.The concentration of top surface place first material in Semiconductor substrate 22 is greater than in the concentration of top surface place second material of Semiconductor substrate 22.Along with the degree of depth the top surface from Semiconductor substrate 22 increases, the concentration of the first material can increase and the concentration of the second material can reduce.Certain depth place the top surface from Semiconductor substrate 22, the concentration of the first material can be substantially equal to the concentration of the second material.
Specifically, Semiconductor substrate 22 comprises the first district 24 and the second district 26.First district 24 can be positioned at the top surface place of Semiconductor substrate 22, and the second district 26 is arranged under the first district 24.First district 24 contacts grid structure 39.First district 24 can have the thickness of such as 1-20nm.
The concentration of the first material and the concentration of the second material is described in detail now with reference to Figure 25.First district 24 of Fig. 3 corresponding to the second district 26 of the Reference numeral 23, Fig. 3 of Figure 25 corresponding to the Reference numeral 25 of Figure 25.
In the first district 24, the concentration of the first material increases gradually from the top surface in the first district 24 towards the basal surface in the first district 24.Namely, the concentration of bottom surface first material in the first district 24 is less than in the concentration of top surface place first material in the first district 24.First material is 10% or less in the concentration at the top surface place in the first district 24.In the first district 24, the concentration of the first material is lower than the concentration of the second material.
In the first district 24, the concentration of the second material is higher than the concentration of the first material.Namely, in the top surface place in the first district 24 and the bottom surface in the first district 24, the concentration of the second material is higher than the first material.But the concentration of the second material reduces towards the basal surface in the first district 24, and the difference between the concentration of the second material and the concentration of the first material reduces towards the basal surface in the first district 24.
First district 24 can comprise some oxygen atoms.Oxygen atom can reduce from the top surface in the first district 24 towards the basal surface in the first district 24, and no longer can be present in the certain depth place from the top surface in the first district 24.Namely, the oxygen atom at the top surface place in the first district 24 is more than the oxygen atom of the bottom surface in the first district 24.At the top surface place in the first district 24, the concentration of oxygen atom can be 5% or less.
In the second district 26, the concentration of the first material can be substantially equal to the concentration of the second material.Here, term " substantially " not only represents accurately identical, and allows the surplus of contingent error during technique.Therefore, as shown in figure 25, the concentration of the first material and the concentration of the second material can be unequal in the some parts in the second district 26.
In the second district 26, oxygen atom can exist hardly, as shown in figure 25.
Again with reference to Fig. 3, device isolation layer 20, such as, shallow trench isolation, from (STI) layer, is formed in Semiconductor substrate 22 to be limited with source region.
Grid structure 39 can be arranged in Semiconductor substrate 22.Grid structure 39 can be arranged in the first district 24 of Semiconductor substrate 22.Grid structure 39 can comprise gate insulator 42, work function key-course 44 and gate metal 46.
Gate insulator 42 can be arranged in Semiconductor substrate 22.Gate insulator 42 can be formed as the first district 24 of contact semiconductor substrate 22.Gate insulator 42 can be conformally formed by the sidewall along the top surface in the first district 24 and along sept 48.Therefore, gate insulator 42 can have concave shape.
Gate insulator 42 can comprise high k dielectric.Gate insulator 42 can comprise and being selected from by such as HfSiON, HfO 2, ZrO 2, Al 2o 3, Ta 2o 5, TiO 2, SrTiO 3(Ba, Sr) TiO 3the material of the group formed.Gate insulator 42 can be formed to suitable thickness according to the type of the device that will be formed.
Gate electrode can comprise work function key-course 44 and gate metal 46.The gate electrode comprising work function key-course 44 and gate metal 46 can be arranged on gate insulator 42.The gate electrode comprising work function key-course 44 and gate metal 46 can fill the space of the recessed intra-zone formed by gate insulator 42.
Work function key-course 44 can be arranged on gate insulator 42.Work function key-course 44 can be formed directly on gate insulator 42.Specifically, work function key-course 44 can be conformally formed along the sidewall of the top surface in the first district 24 and sept 48 and gate insulator 42 betwixt, and can concave shape be had.
If semiconductor device 3 is nmos pass transistor, then work function key-course 44 can be N-type work function key-course, and can comprise at least one in such as TiAl, TiAlC, TiAlN, TaC, TiC and HfSi.
Alternatively, if semiconductor device 3 is PMOS transistor, then work function key-course 44 can be P type work function key-course and can comprise such as TiN.Alternatively, work function key-course 44 can have by P type work function key-course and be stacked on the structure that the N-type work function key-course on P type work function key-course forms.In such execution mode, work function key-course 44 can perform the function identical with P type work function key-course.
Gate metal 46 can fill the recessed region formed by gate insulator 42 and work function key-course 44.
Sept 48 can be arranged on the one side or the multi-lateral of grid structure 39.Sept 48 can one or more sidewalls of overlies gate structure 39.Sept 48 can be arranged in the second district 26, instead of in the first district 24.Namely, sept can be arranged in the second district 26 between the first district 24 and source/drain regions 52.
Each sept 48 can be at least one in such as nitride layer and oxynitride layer.In the alternate embodiment of Fig. 3, each sept 48 can be multilayer, instead of the individual layer shown in Fig. 3.
Source/drain regions 52 can be arranged on the one side or the multi-lateral of grid structure 39.Source/drain regions 52 can be formed in Semiconductor substrate 22 by epitaxy technique.
Source/drain regions 52 can be spaced apart with the first district 24 by the second district 26.Namely, source/drain regions 52 can be formed as making source/drain regions 52 not contact the first district 24.Therefore, source/drain regions 52 contacts the second district 26.In the surface of the contact source/drain regions 52 of Semiconductor substrate 22, the concentration of the first material and the concentration of the second material can be substantially equal.Namely, in the surface of the contact source/drain regions 52 in the second district 26, the concentration of the first material and the concentration of the second material can be substantially equal.
If semiconductor device 3 is PMOS transistor, then source/drain regions 52 can comprise the material with the lattice constant larger than Semiconductor substrate 22.Alternatively, if semiconductor device 3 is nmos pass transistor, then source/drain regions 52 can comprise the material with the lattice constant less than Semiconductor substrate 22.
Cover layer 53 can be arranged on grid structure 39.Cover layer 53 can overlies gate structure 39, and gate insulator 42, work function key-course 44 and gate metal 46 are not exposed.In addition, cover layer 53 can be arranged on the top surface of sept 48.
Cover layer 53 can be such as nitride layer, such as, can be at least one in SiN, SiON and SiCON, or can be such as oxide skin(coating).
First interlayer dielectric 60 can be set to the sidewall covering Semiconductor substrate 22 and sept 48.In addition, the first interlayer dielectric 60 partly can cover the sidewall of contact hole 70, and the upper side wall of contact hole 70 is not covered by the first interlayer dielectric 60.The top surface of the first interlayer dielectric 60 and the top surface of grid structure 39 can be positioned at same plane.Namely, the top surface of the first interlayer dielectric 60 can flush substantially with the top surface of grid structure 39.The top surface of the first interlayer dielectric 60 and the top surface of grid structure 39 can pass through flatening process, such as chemico-mechanical polishing (CMP) technique and be made for and be positioned at same plane.
Second interlayer dielectric 62 can be arranged on the first interlayer dielectric 60.Second interlayer dielectric 62 can the remainder of sidewall of overlies gate structure 39 and cover layer 53 and contact hole 70.
First and second interlayer dielectrics 60 and 62 can comprise at least one in such as oxide skin(coating), nitride layer and oxynitride layer.
Contact hole 70 can be separately positioned on source/drain regions 52.Contact hole 70 can penetrate the first and second interlayer dielectrics 60 and 62 and expose the top surface of source/drain regions 52 respectively.
Contact metal layer 72 can be formed along its basal surface respectively in contact hole 70.Contact metal layer 72 can contact source/drain regions 52 respectively.
Contact metal layer 72 can reduce the sheet resistance, contact resistance etc. of source/drain regions 52.Contact metal layer 72 can comprise electric conducting material, such as Pt, Ni, Co, Au or Al.
Contact 76 can be arranged in contact metal layer 72 with difference filling contact hole 70.Contact 76 can be made up of electric conducting material such as W, Al or Cu.But the present invention's design is not limited thereto.
As shown in Figure 3, each contact 76 can from having homogeneous thickness towards top bottom it.But the present invention's design is not limited thereto.Such as, each contact 76 also can broaden from bottom towards top.
The semiconductor device 4 of the example embodiment according to the present invention's design is described now with reference to Fig. 4.For simplicity, the description of the element substantially the same with the element of aforementioned embodiments will be omitted, and will describe current embodiment hereinafter, mainly concentrate in the difference with aforementioned embodiments.
Fig. 4 is the sectional view of semiconductor device 4 of the example embodiment according to the present invention's design.
With reference to Fig. 4, except the element of the semiconductor device 3 of Fig. 3, semiconductor device 4 can also comprise substrate 12.Substrate 12 can be arranged under Semiconductor substrate 22.Substrate 12 can be made up of one or more semi-conducting materials being such as selected from the group be made up of Si, Ge, SiGe, SiC and SiGeC.Substrate 12 also can be such as SOI substrate.Namely, substrate 12 can not comprise III element and V group element.
The semiconductor device 5 of the example embodiment according to the present invention's design is described now with reference to Fig. 5.For simplicity, the description of the element substantially the same with the element of aforementioned embodiments will be omitted, and will describe current embodiment hereinafter, mainly concentrate in the difference with aforementioned embodiments.
Fig. 5 is the sectional view of semiconductor device 5 of the example embodiment according to the present invention's design.
With reference to Fig. 5, substrate 12 can comprise nmos area I and PMOS district II.Nmos area I can be the structure identical with the semiconductor device 4 of Fig. 4.Work function key-course 44 can comprise at least one in such as TiAl, TiAlC, TiAlN, TaC, TiC and HfSi.
PMOS district II can be the structure identical with the semiconductor device 4 of Fig. 4, except grid structure 38.Grid structure 38 in PMOS district II can comprise two work function key-courses 44,48.Second work function key-course 44 can be stacked on the first work function key-course 48, and the first and second work function key-courses 48 and 44 can be recessed in shape.First work function key-course 48 can be arranged between the second work function key-course 44 and gate insulator 42.Gate metal 46 can be arranged in the recessed region formed by gate insulator 42, first work function key-course 48 and the second work function key-course 44 and to fill this recessed region.First work function key-course 48 can be P type work function key-course, and the second work function key-course 44 can be N-type work function key-course.Therefore, the second work function key-course 44 can comprise at least one in such as TiAl, TiAlC, TiAlN, TaC, TiC and HfSi, and the first work function key-course 48 can comprise such as TiN.First work function key-course 48 can affect the operation of the grid structure 38 in PMOS district II, and the second work function key-course 44 can affect the operation of the grid structure 39 in the I of nmos area.
The semiconductor device 6 of the example embodiment according to the present invention's design is described now with reference to Fig. 6 to Fig. 8.
Fig. 6 to Fig. 8 is the view of semiconductor device 6 of the example embodiment according to the present invention's design.Specifically, Fig. 6 is the perspective view of semiconductor device 6 of the example embodiment according to the present invention's design.Fig. 7 is the sectional view intercepted along the line A-A of Fig. 6.Fig. 8 is the sectional view intercepted along the line B-B of Fig. 6.In figure 6, the first and second interlayer dielectrics 130 and 132 are not illustrated.
With reference to Fig. 6 to Fig. 8, semiconductor device 6 can comprise substrate 101, fin F1, field insulating layer 110, grid structure 151, sept 121, source/drain regions 123, contact metal layer 191, contact the 193, first interlayer dielectric 130 and the second interlayer dielectric 132.
Specifically, substrate 101 can be made up of one or more semi-conducting materials being such as selected from the group be made up of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP.Substrate 101 also can be such as SOI substrate.
Fin F1 can in a longitudinal direction, and namely, second direction Y1 extends.Fin F1 can have long side and short side.In figure 6, long side to being second direction Y1, short side to being Width, namely, first direction X1.But the present invention's design is not limited thereto.Such as, the long side of fin F1 is to being first direction X1, and the short side of fin F1 is to being second direction Y1.Fin F1 can give prominence to from substrate 101 on third direction Z1.
Fin F1 can be the part of substrate 101, and can comprise the epitaxial loayer grown from substrate 101.
Fin F1 can comprise the first material and the second material.First material can be such as III element, and the second material can be such as V group element.III element can be at least one in Ga, In and Al.V group element can be at least one in such as P, As and Sb.Therefore, fin F1 can be made up of at least one in such as GaAs, InGaAs, AlGaAs, InAs, GaSb, InSb and InP.
Fin F1 can be included between source/drain regions 123 and channel region under grid structure 151.
The concentration of the first material that fin F1 comprises and the second material can according in fin F1, specifically, and the position within channel region and changing.Second material is greater than the concentration of the first material on the surface of the channel region of fin F in the concentration on the surface of the channel region of fin F1.Along with the channel region from fin F1 surface the degree of depth increase, the concentration of the first material can increase and the concentration of the second material can reduce.Certain depth place top surface in the channel region from fin F1, the concentration of the first material can be substantially equal to the concentration of the second material.
Specifically, the channel region of fin F1 comprises the first district 103 and the second district 105.First district 103 can be positioned at the surface of the channel region of fin F1, and the second district 105 can be arranged on the recessed intra-zone formed by the first district 103, as shown in Figure 7, and is arranged under the first district 103, as shown in Figure 7 and Figure 8.First district 103 can contact grid structure 151.On the top surface that first district 103 can be arranged on fin F1 and sidewall.First district 103 can have the thickness of such as 1 to 20nm.
The concentration of the first material and the concentration of the second material is described in detail now with reference to Figure 25.First district 103 of Fig. 6 to Fig. 8 corresponding to the second district 105 of the Reference numeral 23, Fig. 6 to Fig. 8 of Figure 25 corresponding to the Reference numeral 25 of Figure 25.
In the first district 103, the concentration of the first material increases gradually from the top surface in the first district 103 towards the surface in contact second district 105.Namely, the first material is less than the concentration of the first material in the surface in contact second district 105 in the first district 103 in the concentration at the top surface place in the first district 103.First material is 10% or less in the concentration at the top surface place in the first district 103.In the first district 103, the concentration of the first material is lower than the concentration of the second material.
In the first district 103, the concentration of the second material is higher than the concentration of the first material.Namely, the top surface place in the first district 103 and the surface contacting the second district 105 in the first district 103, the concentration of the second material is higher than the first material.But the concentration of the second material reduces towards the basal surface in the first district 103, and the difference between the concentration of the second material and the concentration of the first material reduces towards the basal surface in the first district 103.
First district 103 can comprise some oxygen atoms.Oxygen atom can reduce from the top surface in the first district 103 towards the basal surface in the first district 103, and no longer can be present in the certain depth place from the top surface in the first district 103.Namely, the oxygen atom at the top surface place in the first district 103 is more than the oxygen atom of the bottom surface in the first district 103.At the top surface place in the first district 103, the concentration of oxygen atom can be 5% or less.
In the second district 105, the concentration of the first material can be substantially equal to the concentration of the second material.Here, term " substantially " not only represents accurately identical, and allows the surplus of contingent error during technique.Therefore, as shown in figure 25, the concentration of the first material and the concentration of the second material can be unequal in the some parts in the second district 105.
In the second district 105, oxygen atom can exist hardly, as shown in figure 25.
Field insulating layer 110 can be arranged on the substrate 101, and partly can cover the sidewall of fin F1, exposes the top of fin F1 simultaneously.
Grid structure 151 can be arranged on fin F1 and crossing with fin F1.In figure 6, grid structure 151 extends along first direction X1.But the present invention's design is not limited thereto.Such as, grid structure 151 can with about the acute angle of fin F1 or obtuse angle crossing with fin F1.
Grid structure 151 can comprise gate electrode and gate insulator 153, and this gate electrode comprises the first metal layer 155 and the second metal level 157.
Gate electrode can comprise the first metal layer 155 and the second metal level 157.As shown in Figure 6 to 8, gate electrode can comprise the stacking of two or more metal levels.The first metal layer 155 regulatory work function, the second metal level 157 fills the space formed by the first metal layer 155.In one example, the first metal layer 155 can comprise at least one in TiAl, TiAlC, TiAlN, HfSi, TiN, TaN, TiC and TaC.In addition, the second metal level 157 can comprise such as W or Al.Alternatively, the gate electrode comprising the first metal layer 155 and the second metal level 157 can be made up of such as Si or SiGe of material than metal.In one example, grid structure 151 can be formed by such as replacing process.But the present invention's design is not limited thereto.
The first metal layer 155 can be arranged between gate insulator 153 and the second metal level 157.Second metal level 157 can fill the space formed by gate insulator 153 and the first metal layer 155.
Gate insulator 153 can be formed in fin F1 and comprise between the first metal layer 155 and the gate electrode of the second metal level 157.As shown in Figure 8, on gate insulator 153 top surface that can be formed in fin F1 and sidewall.Therefore, gate insulator 153 can contact the first district 103.In addition, gate insulator 153 can be arranged on comprise the first metal layer 155 and the second metal level 157 between gate electrode and field insulating layer 110.Gate insulator 153 can comprise the high k dielectric of the dielectric constant such as had than Si oxide floor height.Gate insulator 153 can comprise such as HfO 2, ZrO 2, LaO, Al 2o 3or Ta 2o 5.Gate insulator 153, the first metal layer 155 and the second metal level 157 can cover the top sidewall exposed by the first insulating barrier 110 of fin F1, and can cover field insulating layer 110.
Sept 121 can be arranged in the one side or the multi-lateral of grid structure 151.Each sept 121 can comprise at least one in nitride layer and oxynitride layer.In the alternative, each sept 121 can be multilayer, instead of individual layer as shown in Figure 6 to 8.
Source/drain regions 123 can be arranged in the one side or the multi-lateral of grid structure 151.Source/drain regions 123 can be arranged in fin F1.Source/drain regions can be spaced apart with first district 103 of fin F1 by second district 105 of fin F1.
Source/drain regions 123 can be overhead (elevated) source/drain regions.Therefore, the top surface of source/drain regions 123 can higher than the top surface of fin F1.
If semiconductor device 6 is PMOS transistor, then source/drain regions 123 can comprise compression material.Compression material can be the material such as with the lattice constant larger than the material of fin F1.Compression material can improve the mobility of the charge carrier in channel region by compression is applied to the channel region below grid structure 151.
If semiconductor device 6 is nmos pass transistor, then source/drain regions 123 can comprise tensile stress material.Source/drain regions 123 can comprise tensile stress material or the material identical with substrate 101.Source/drain regions 123 can comprise the material such as with the lattice constant less than fin F1.
Source/drain regions 123 can be formed by epitaxial growth.
Source/drain regions 123 can be arranged so that source/drain regions 123 does not contact the first district 103.Therefore, source/drain regions 123 contacts the second district 105.In the surface of each source/drain regions 123 of the contact of fin F1, the concentration of the first material and the concentration of the second material can be substantially equal.Namely, in the surface of the contact source/drain regions 52 in the second district 105, the concentration of the first material and the concentration of the second material can be substantially equal.
Contact metal layer 191 is separately positioned on source/drain regions 123.Contact metal layer 191 can reduce the sheet resistance, contact resistance etc. of source/drain regions 123.Contact metal layer 123 can comprise such as Pt, Ni, Co, Au or Al.
Contact 193 can be respectively formed in contact metal layer 191.Contact 193 can penetrate the first and second interlayer dielectrics 130 with 132 to contact contact metal layer 191 respectively.Contact 193 can be made up of such as electric conducting material such as W, Al or Cu.
As shown in the drawing, each contact 193 can from having homogeneous thickness towards top bottom it.But the present invention's design is not limited thereto.Such as, each contact 193 also can from broadening towards top bottom it.
First interlayer dielectric 130 and the second interlayer dielectric 132 can sequentially be formed on field insulating layer 110.First interlayer dielectric 130 can cover contact metal layer 191 and partly cover the sidewall of contact 194, and the upper portion side wall of contact 193 is not covered by the first interlayer dielectric 130.Second interlayer dielectric 132 can cover the remainder of the sidewall of contact 193.
As shown in Figure 7, the top surface of the first interlayer dielectric 130 and the top surface of grid structure 151 can be positioned at same plane.Namely, the top surface of the first interlayer dielectric 130 can flush substantially with the top surface of grid structure 151.The top surface of the first interlayer dielectric 130 and the top surface of grid structure 151 can pass through flatening process, such as CMP and be made for and be positioned at same plane.Second interlayer dielectric 132 can be formed on the first interlayer dielectric 130 with overlies gate structure 151, sept 121 and the remainder contacting 193.First and second interlayer dielectrics 130 and 132 can comprise at least one in such as oxide skin(coating), nitride layer and oxynitride layer.
In Fig. 6 to Fig. 8, substrate 101 does not comprise the first material and the second material.But the present invention's design is not limited thereto.Such as, as fin F1, substrate 101 also can comprise the first and second materials.
The semiconductor device 7 of the example embodiment according to the present invention's design is described now with reference to Fig. 9.For simplicity, the description of the element substantially the same with the element of aforementioned embodiments will be omitted, and will describe current embodiment hereinafter, mainly concentrate in the difference with aforementioned embodiments.
Fig. 9 is the perspective view of semiconductor device 7 of the example embodiment according to the present invention's design.In fig .9, the first and second interlayer dielectrics 130 and 132 are not illustrated.
With reference to Fig. 9, except the element of the semiconductor device 6 of Fig. 6, semiconductor device 7 also comprises cover layer 181.Specifically, cover layer 181 is arranged on grid structure 151, and gate insulator 153 and the first and second metal levels 155 and 157 are not exposed.The top surface that cover layer 181 is arranged on gate insulator 153, the first metal layer 155 and the second metal level 157, along the madial wall of sept 121, make the top surface of cover layer 181 substantially flush with the top surface of sept 121.
Cover layer 181, by grid structure 151 and external isolation, avoids the change of the performance of grid structure 151 thus.In addition, even if contact 193 misalignments, cover layer 181 also can prevent contact 193 from contacting grid structure 151.
Cover layer 181 can comprise at least one in such as oxide skin(coating), oxynitride layer and nitride layer.
The semiconductor device 8 of the example embodiment according to the present invention's design is described now with reference to Figure 10 to Figure 12.For simplicity, the description of the element substantially the same with the element of aforementioned embodiments will be omitted, and will describe current embodiment hereinafter, mainly concentrate in the difference with aforementioned embodiments.
Figure 10 to Figure 12 is the view of semiconductor device 8 of the example embodiment according to the present invention's design.Specifically, Figure 10 is the perspective view of semiconductor device 8 of the example embodiment according to the present invention's design.Figure 11 is the sectional view intercepted along line A-A and C-C of Figure 10.Figure 12 is the sectional view intercepted along line B-B and D-D of Figure 10.In Fig. 10, the first interlayer dielectric 130 and 230 and the second interlayer dielectric 132 and 232 are not illustrated.
With reference to Figure 10 to Figure 12, substrate 101 and substrate 201 can be divided into nmos area III and PMOS district IV.Nmos area III and PMOS district IV can be connected to each other or separated from one another.
Nmos area III can be the structure identical with the semiconductor device 6 of Fig. 6.Because nmos pass transistor is formed in the III of nmos area, so source/drain regions 123 can comprise the material with the lattice constant less than the material of fin F1.In addition, the first metal layer 155 can be N-type work function key-course, therefore can comprise at least one in such as TiAl, TiAlC, TiAlN, TaC, TiC and HfSi.
PMOS district IV can be the structure identical with the semiconductor device 6 of Fig. 6, except grid structure 251.In PMOS district IV, grid structure 251 also comprises the 3rd metal level 254.3rd metal level 254 can be P type work function key-course, and can comprise such as TiN.3rd metal level 254 can be arranged between gate insulator 253 and the first metal layer 255.Although the first metal layer 255 is arranged on the 3rd metal level 254, the 3rd metal level 254 is responsible for the work function of control gate structure 251.
The source/drain regions 233 of PMOS district IV can comprise the material with the large lattice constant of the material of ratio as fin F2.
Fin F2, substrate 201, field insulating layer 210, first and second interlayer dielectric 230 and 232, gate insulator 253, first and second metal level 255 and 257, contact metal layer 291 and contact 293 identical with the corresponding component of nmos area IV, therefore its detailed description will be omitted.
The semiconductor device of any one in the semiconductor device 1 to 8 comprising and manufacturing according to the example embodiment of the present invention's design is described now with reference to Figure 13 and Figure 14.
Figure 13 and Figure 14 is circuit diagram and the layout of the semiconductor device of any one comprised in the semiconductor device 1 to 8 of the Fig. 1 to Figure 12 manufactured according to the example embodiment of the present invention's design.Although used static RAM (SRAM) in figs. 13 and 14, the fin transistor according to the example embodiment manufacture of the present invention's design also can be applied to other semiconductor device.
With reference to Figure 13, semiconductor device can be included in the first and second transmission transistor PS1 and PS2 of a pair first and second inverter INV1 and INV2 be connected in parallel between power supply node VCC and ground nodes VSS and the output node being connected respectively to the first and second inverter INV1 and INV2.First and second transmission transistor PS1 and PS2 can be connected respectively to bit line BL and paratope line/BL.The grid of the first and second transmission transistor PS1 and PS2 can be connected to wordline WL.
First inverter INV1 comprises the first pull up transistor PU1 and the first pull-down transistor PD1, the second inverter INV2 be connected in series and comprises second pulling up transistor PU2 and the second pull-down transistor PD2 of being connected in series.First and second PU1 and PU2 that pull up transistor can be PMOS transistor, and the first and second pull-down transistor PD1 and PD2 can be nmos pass transistors.
The input node of the first inverter INV1 is connected to the output node of the second inverter INV2, the input node of the second inverter INV2 is connected to the output node of the first inverter INV1, therefore, the first and second inverter INV1 and INV2 can form single latch cicuit.
Refer again to Figure 13 and Figure 14, the first fin 310, second fin 320, the 3rd fin 330 and the 4th fin 340 can in a first direction, such as, vertical direction in Figure 14 extend, and can be separated from one another.Second fin 320 and the 3rd fin 330 can than the first fin 310 and the 4th fin 340 short.
In addition, first grid electrode 351, second grid electrode 352, the 3rd gate electrode 353 and the 4th gate electrode 354 can in a second direction, and horizontal direction in fig. 14 such as, extend, and crossing with first to fourth fin 310 to 340.Specifically, first grid electrode 351 can with the first fin 310 and the completely crossing and one end that is partly overlapping 3rd fin 330 of the second fin 320.3rd gate electrode 353 can with the 4th fin 340 and the fully crossing and one end that is partly overlapping second fin 320 of the 3rd fin 330.Second grid electrode 352 can be crossing with the first fin 310, and the 4th gate electrode 354 can be crossing with the 4th fin 340.
First PU1 that pulls up transistor can be limited at the near intersections of first grid electrode 351 and the second fin 320.First pull-down transistor PD1 can be limited at the near intersections of first grid electrode 351 and the first fin 310.First transmission transistor PS1 can be limited at the near intersections of second grid electrode 352 and the first fin 310.Second PU2 that pulls up transistor can be limited at the near intersections of the 3rd gate electrode 353 and the 3rd fin 330.Second pull-down transistor PD2 can be limited at the near intersections of the 3rd gate electrode 353 and the 4th fin 340.Second transmission transistor PS2 can be limited at the near intersections of the 4th gate electrode 354 and the 4th fin 340.
Although do not illustrate particularly, recess can be respectively formed at the both sides of each intersection point between first to fourth gate electrode 351 to 354 and first to fourth fin 310 to 340, and source/drain regions can be formed in recess.
Multiple contact 350 also can be formed.
Share contact 361 and can connect the second all fins 320, the 3rd gate line 353 and wiring 371.Share contact 362 and can connect the 3rd all fins 330, first grid polar curve 351 and wiring 372.
First PU1 and second that pulls up transistor pulls up transistor any one that PU2 each can comprise in the above semiconductor device 1 to 8 described referring to figs. 1 through Figure 12.
Figure 15 comprises the block diagram according to the electronic system 1100 of any one in the semiconductor device 1 to 8 of the example embodiment manufacture of the present invention's design.
With reference to Figure 15, the electronic system 1100 according to the example embodiment of the present invention's design can comprise controller 1110, I/O (I/O) device 1120, memory device 1130, interface 1140 and bus 1150.Controller 1110, I/O device 1120, memory device 1130 and/or interface 1140 can be connected to each other by bus 1150.Bus 1150 can be used as the path of transmission data.
Controller 1110 can comprise microprocessor, digital signal processor, microcontroller and can perform and at least one in the logical device of the functionally similar function of microprocessor, digital signal processor, microcontroller etc.I/O device 1120 can comprise keypad, keyboard, display unit etc.Memory device 1130 can store data/or instruction.Interface 1140 can be used to data are sent to communication network or receive data from communication network.Interface 1140 can be such as wired or wave point.Interface 1140 can comprise such as antenna or wired or wireless transceiver.Although do not illustrate in the drawings, electronic system 1110 can be the operational store of the operation for improving controller 1110, and can comprise high speed dram (DRAM) or SRAM.Here, may be provided in memory device 1130, in controller 1110 and/or in I/O device 1120 according to any one in the semiconductor device 1 to 8 of the above-mentioned execution mode of the present invention's design.
Electronic system 1110 can be applied to the electronic product of nearly all type that can transmit and/or receive information in wireless environments, such as personal digital assistant (PDA), portable computer, net book, radio telephone, mobile phone, digital music player, storage card etc.
Figure 16 and Figure 17 is the diagram of the example that semiconductor system is shown, the semiconductor device 1 to 8 according to Fig. 1 to Figure 12 of the example embodiment manufacture of the present invention's design can be applied to this semiconductor system.Figure 16 illustrates that tablet PC (PC) 1101, Figure 17 illustrates notebook computer 1102.As set forth herein, dull and stereotyped PC, notebook computer etc. can be used to according at least one in the semiconductor device 1 to 8 of Fig. 1 to Figure 12 of the above-mentioned example embodiment of the present invention's design.Be apparent that for the ordinary skill in the art, as set forth herein, also can be applied to the various IC devices except system set forth herein according to the semiconductor device 1 to 8 of Fig. 1 to Figure 12 of the example embodiment of the present invention's design.
The method of the manufacture semiconductor device of the example embodiment according to the present invention's design is described now with reference to Fig. 1 and Figure 18 to Figure 27.For simplicity, the description of substantially the same with element described above element will be omitted.
Figure 18 to Figure 27 is the view of the step of the method for the manufacture semiconductor device 1 of the example embodiment illustrated according to the present invention's design.Specifically, Figure 18, Figure 20, Figure 21, Figure 22, Figure 24, Figure 26 and Figure 27 are sectional view.Figure 19 is the curve chart of the concentration of the Semiconductor substrate 21 that Figure 18 is shown.Figure 23 is the curve chart of the concentration of the Semiconductor substrate 21 that Figure 22 is shown.
With reference to Figure 18 and Figure 19, provide Semiconductor substrate 21.Semiconductor substrate 21 can comprise the first material and the second material.First material can be such as III element, and the second material can be such as V group element.III element can be at least one in such as Ga, In and Al.V group element can be at least one in such as P, As and Sb.Therefore, Semiconductor substrate 21 can be made up of at least one in such as GaAs, InGaAs, AlGaAs, InAs, GaSb, InSb and InP.
Native oxide layer 31 can be formed in Semiconductor substrate 21.Native oxide layer 31 can be formed naturally instead of artificially by the reaction of the top surface of Semiconductor substrate 21 and oxygen atom.
Semiconductor substrate 21 comprises the first material and the second material with substantially equal concentration.But, because native oxide layer 31 is formed on the top surface of Semiconductor substrate 21, so the top surface of Semiconductor substrate 21 can comprise some oxygen atoms.With reference to Figure 19, because the top surface bonding of oxygen atom and Semiconductor substrate 21, so the concentration of oxygen atom is high at the top surface place of Semiconductor substrate 21.But oxygen atom is present in the certain depth place from the top surface of Semiconductor substrate 21 hardly, namely, be present in hardly in Semiconductor substrate 21.Namely, the concentration of oxygen atom is large at the bottom place of Semiconductor substrate 21 at the top surface place of Semiconductor substrate 21 ratio.Because the top surface of Semiconductor substrate 21 comprises oxygen atom, therefore the concentration of the first and second materials is low at the top surface place of Semiconductor substrate 21.But the concentration of the first material and the second material can increase along with the degree of depth the top surface from Semiconductor substrate 21 and increase gradually, and can certain depth place the top surface from Semiconductor substrate 21 substantially equal.The concentration of the first material and the second material is little at the bottom place of Semiconductor substrate 21 at the top surface place of Semiconductor substrate 21 ratio.
With reference to Figure 20, native oxide layer 31 is removed by the top surface of cleaning Semiconductor substrate 21.Therefore, be removed with the oxygen atom of Semiconductor substrate 21 bonding.
With reference to Figure 21, the top surface of Semiconductor substrate 21 is oxidized by oxidation technology 33.Oxidation technology 33 can under high pressure perform.Such as, oxidation technology 33 can at 5atm or higher and be performed 30 minutes to 2 hours at 300 DEG C or higher.Alternatively, oxidation technology 33 can perform 30 minutes to 2 hours under 600 DEG C or higher high temperature.Therefore, as shown in figure 22, oxide skin(coating) 35 can be formed on the top surface of Semiconductor substrate 21 artificially.
Oxidation technology 33 can cause the first material of Semiconductor substrate 21 and the second material and oxygen atom (O) bonding.In Semiconductor substrate 21, the reaction of the first material and oxygen atom is higher than the reaction of the second material and oxygen atom in Semiconductor substrate.Therefore, the first material can form the oxide more than the second material.Therefore, oxide skin(coating) 35 can comprise the oxide of first material more than the oxide of the second material.
With reference to Figure 23, due to the top surface bonding of oxygen atom in Figure 22 and Semiconductor substrate 21, so the concentration of oxygen atom is high at the top surface place of Semiconductor substrate 31.But along with the degree of depth the top surface from Semiconductor substrate 21 increases, the concentration of oxygen atom reduces in Semiconductor substrate 21.In addition, due to the top surface bonding of oxygen atom and Semiconductor substrate 21, so the first material and the second material reduce slightly in the concentration at the top surface place of Semiconductor substrate 21.
With reference to Figure 24, the oxide skin(coating) 35 be formed in Semiconductor substrate 21 is removed.In order to remove oxide skin(coating) 35, wet etching process can utilize HF, NH 4oH, HCl etc. are performed as etchant.Wet etching process can change the concentration of the first material in Semiconductor substrate 21 and the concentration of the second material in Semiconductor substrate 21.With reference to Figure 25, the second material is greater than the concentration of the first material at the top surface place of Semiconductor substrate 21 in the concentration at the top surface place of Semiconductor substrate 21.Along with the degree of depth the top surface from Semiconductor substrate 21 increases, the concentration of the first material in Semiconductor substrate 21 can increase, and the certain depth place the top surface from Semiconductor substrate 21, the concentration of the first material and the concentration of the second material can be substantially equal.Namely, along with the degree of depth the top surface from Semiconductor substrate 21 increases, the concentration of the second material can reduce to become substantially equal with the concentration of the first material.
Specifically, with reference to Figure 24 and Figure 25, Semiconductor substrate 21 comprises the first district 23 and the second district 25.First district 23 can be positioned at the top surface place of Semiconductor substrate 21, and the second district 25 can be arranged under the first district 23 of Semiconductor substrate 21.The grid structure 40 will formed after first district 23 can contact, as shown in figure 27.First district 21 can have the thickness of such as 1 to 20nm.
With reference to Figure 25, the concentration of the first material in the first district 23 increases gradually from the top surface in the first district 23 towards the basal surface in the first district 23.Namely, the first material is less than the concentration of the first material in the bottom surface in the first district 23 in the concentration at the top surface place in the first district 23.First material is 10% or less in the concentration at the top surface place in the first district 23.In the first district 23, the concentration of the first material is lower than the concentration of the second material.
In the first district 23, the concentration of the second material is higher than the concentration of the first material.Namely, in the top surface place in the first district 23 and the bottom surface in the first district 23, the concentration of the second material is higher than the first material.But the concentration of the second material reduces towards the basal surface in the first district 23, and the difference between the concentration of the second material and the concentration of the first material reduces towards the basal surface in the first district 23.
First district 23 can comprise not by the removed oxygen atom of wet etching process.Oxygen atom can reduce from the top surface in the first district 23 towards the basal surface in the first district 23, and no longer can be present in the certain depth place from the top surface in the first district 23.Namely, the oxygen atom at the top surface place in the first district 23 is more than the oxygen atom of the bottom surface in the first district 23.At the top surface place in the first district 23, the concentration of oxygen atom can be 5% or less.
In the second district 25, the concentration of the first material can be substantially equal to the concentration of the second material.Here, term " substantially " not only represents accurately identical, and allows the surplus of contingent error during technique.Therefore, as shown in figure 25, the concentration of the first material and the concentration of the second material can be unequal in the some parts in the second district 25.
In the second district 25, oxygen atom can exist hardly, as shown in figure 25.
Can sequentially be formed in Semiconductor substrate 21 with reference to Figure 26, gate insulator 41a, gate electrode 43a and hard mask layer 45a.
Gate insulator 41a can be formed as the first district 23 of contact semiconductor substrate 21.Gate insulator 41a can comprise and being such as selected from by such as HfSiON, HfO 2, ZrO 2, Al 2o 3, Ta 2o 5, TiO 2, SrTiO 3(Ba, Sr) TiO 3the material of the group formed.Alternatively, gate insulator 41a can be such as silicon oxide layer.Gate insulator 41a can be formed by such as ald (ALD) or chemical vapour deposition (CVD) (CVD).
Gate electrode 43a can be arranged on gate insulator 41a.Gate electrode 43a can comprise such as electric conducting material such as polysilicon.
Hard mask layer 45a can be arranged on gate electrode 43a.Hard mask layer 45 can comprise at least one in such as oxide skin(coating), nitride layer and oxynitride layer.
With reference to Figure 27, grid structure 40 can pass through patterned grid insulating layer 41a, gate electrode 43a and hard mask layer 45a and be formed.
But sept 47 can be formed in the one side or the multi-lateral of grid structure 40.Sept 47 can by forming spacer layer (not shown) to cover Semiconductor substrate 21 and grid structure 40 and then to eat-back spacer layer and be formed in the one side or the multi-lateral of grid structure 40.
Sept 47 can comprise at least one in such as oxide, nitrogen oxide and nitride.
Finally, source/drain regions 51 can be formed in the one side or the multi-lateral at grid structure 40 in Semiconductor substrate 21, completes the semiconductor device 1 of Fig. 1 thus.
The effect of the present invention's design is described now with reference to Figure 28.Figure 28 is the curve chart that the effect that the present invention conceives is shown.
In Figure 28, two curve chart A and B are illustrated.The A of Figure 28 is the curve chart that the electric capacity C-grid voltage Vg measured after grid structure 40 is formed in Semiconductor substrate 21 is shown.The B of Figure 28 is the curve chart of the electric capacity C-grid voltage Vg of the semiconductor device 1 illustrated according to the example embodiment of Fig. 1.Delayed on curve chart A (hysteresis) is measured as 1.30V, delayedly on curve chart B is measured as 0.51V.
In the present invention's design, oxide skin(coating) can be formed by oxide-semiconductor substrate 21, then can be removed to change the first material in the concentration of the top surface of Semiconductor substrate 21 and the second material concentration at the top surface of Semiconductor substrate 21.Which improve hysteresis, as shown in the curve chart B of Figure 28.Therefore, transistor can have low-density interface trapped charge (DIT).Therefore, the transistor with superperformance can be manufactured.
The method of the manufacture semiconductor device of the example embodiment according to the present invention's design is described now with reference to Fig. 3 and Figure 29 to Figure 35.For simplicity, the description of substantially the same with element described above element will be omitted.
Figure 29 to Figure 35 is the sectional view of the step of the method for the manufacture semiconductor device 3 of the example embodiment illustrated according to the present invention's design.
With reference to Figure 29, provide Semiconductor substrate 22.Semiconductor substrate 22 can comprise the first material and the second material.The first material in Semiconductor substrate 22 can be such as III element, and the second material in Semiconductor substrate 22 can be such as V group element.III element can be at least one in such as Ga, In and Al.V group element can be at least one in such as P, As and Sb.Therefore, Semiconductor substrate 22 can be made up of at least one in such as GaAs, InGaAs, AlGaAs, InAs, GaSb, InSb and InP.In Semiconductor substrate 22, the concentration of the first material can be substantially equal to the concentration of the second material.
Device isolation layer 20, such as STI layer can be formed in Semiconductor substrate 21 to be limited with source region.
Then, dummy gate electrode structure 19 can be formed.Dummy gate electrode structure 19 can comprise dummy gate electrode insulating barrier 17 and dummy gate electrode electrode 18.Dummy gate electrode insulating barrier 17 can be formed in Semiconductor substrate 22 and can be such as silicon oxide layer.Dummy gate electrode electrode 18 can be formed on dummy gate electrode insulating barrier 17.Dummy gate electrode electrode 18 can comprise such as polysilicon.
Sept 48 can be formed on one or more sidewalls of dummy gate electrode structure 19.Sept 48 can comprise such as oxide, nitride or nitrogen oxide.Sept 48 can form spacer layer (not shown) by utilizing CVD technique and then eat-back this spacer layer and be formed on one or more sidewalls of dummy gate electrode structure 19.Here, the shape of sept 48 is not limited to the shape shown in figure.
Source/drain regions 52 can be formed in Semiconductor substrate 22 as mask by utilizing dummy gate electrode structure 19 and sept 48.Source/drain regions 52 can be formed between device isolation layer 20 and sept 48.Channel region under dummy gate electrode structure 19 can be the region that P type charge carrier that the N-type carrier that comprises of source/drain regions 52 or source/drain regions 52 comprise moves by it.
First interlayer dielectric 60 can be formed in Semiconductor substrate 22.First interlayer dielectric 60 can cover the sidewall of sept 48 and expose the top surface of dummy gate electrode structure 19 and the top surface of sept 48.In order to expose the top surface of dummy gate electrode structure 19, after formation first interlayer dielectric 60, flatening process can be performed.In the alternative, the first interlayer dielectric 60 also can be formed by two or more insulating barriers stacking.
With reference to Figure 30, groove 30 can be formed by removing dummy gate electrode structure 19.
Groove 30 can expose the sidewall of sept 48 and the top surface of Semiconductor substrate 22.Namely, the top surface between sept 48 of Semiconductor substrate 22 can be exposed.The top surface of the exposure of Semiconductor substrate 22 and oxygen atom react, and form native oxide layer 32 thus in groove 30.
With reference to Figure 31, the native oxide layer 32 be formed in Semiconductor substrate 22 can be removed.Then, the top surface of the exposure in groove 30 of Semiconductor substrate 22 is oxidized by oxidation technology 34.Oxidation technology 34 can at 5atm or higher and 300 DEG C or higher execution 30 minutes to 2 hours.Alternatively, oxidation technology 34 can perform 30 minutes to 2 hours under 600 DEG C or higher high temperature.
With reference to Figure 32, oxide skin(coating) 36 can be formed on the top surface of Semiconductor substrate 22 by oxidation technology 34.The reaction of the first and second materials that oxide skin(coating) 36 can be comprised by oxygen and Semiconductor substrate 22 and being formed.In the oxidation technology 34 performed in the above conditions, the first material can than the second material and more oxygen atoms bond.
With reference to Figure 33, oxide skin(coating) 36 can be removed.In order to remove oxide skin(coating) 36, such as HF, NH can be utilized 4oH, HCl etc. perform wet etching process as etchant.
The removal of oxide skin(coating) 36 can change the concentration of the first material in the channel region of Semiconductor substrate 22 and the concentration of the second material in the channel region of Semiconductor substrate 22.The concentration of the first material in Semiconductor substrate 22 can increase along with the degree of depth the top surface of the channel region from Semiconductor substrate 22 and increase gradually.
Specifically, the channel region of Semiconductor substrate 22 comprises the first district 24 and the second district 26.First district 24 is positioned at the top surface place of the channel region of Semiconductor substrate 22, and the second district 26 is arranged under the first district 24.The grid structure 39 will formed after first district 24 can contact.First district 24 can have the thickness of such as 1-20nm.
In the first district 24, the concentration of the first material increases gradually from the top surface in the first district 24 towards the basal surface in the first district 24.Namely, the first material is less than the concentration of the first material in the bottom surface in the first district 24 in the concentration at the top surface place in the first district 24.First material is 10% or less in the concentration at the top surface place in the first district 24.In the first district 24, the concentration of the first material is lower than the concentration of the second material.
In the first district 24, the concentration of the second material is higher than the concentration of the first material.Namely, in the top surface place in the first district 24 and the bottom surface in the first district 24, the concentration of the second material is higher than the first material.But the concentration of the second material reduces towards the basal surface in the first district 24, and the difference between the concentration of the second material and the concentration of the first material reduces towards the basal surface in the first district 24.
First district 24 can comprise not by oxygen atom that wet etching process is removed.Oxygen atom can reduce from the top surface in the first district 24 towards the basal surface in the first district 24, and no longer can be present in the certain depth place from the top surface in the first district 24.Namely, the oxygen atom at the top surface place in the first district 24 is more than the oxygen atom of the bottom surface in the first district 24.At the top surface place in the first district 24, the concentration of oxygen atom can be 5% or less.
In the second district 26, the concentration of the first material can be substantially equal to the concentration of the second material.Here, term " substantially " not only represents accurately identical, and allows the surplus of contingent error during technique.Therefore, as shown in figure 25, the concentration of the first material and the concentration of the second material can be unequal in the some parts in the second district 26.
In the second district 26, oxygen atom can exist hardly.
Each source/drain regions 52 can be separated the width of each sept 48 with the first district 24.Therefore, in the surface of the contact source/drain regions 52 of Semiconductor substrate 22, the concentration of the first material can be substantially equal to the concentration of the second material.Namely, in the surface of the contact source/drain regions 52 in the second district 26, the concentration of the first material and the concentration of the second material can be substantially equal.
Can sequentially be formed in groove 30 with reference to Figure 34, gate insulator 42a, work function key-course 44a and gate metal 46a.
Gate insulator 42a can be formed in groove 30.Specifically, gate insulator 42a can be conformally formed along the top surface in the sidewall of sept 48 and the first district 24.Therefore, the gate insulator 42a be formed in groove 30 can be recessed in shape.Gate insulator 42a can the first district 24 of contact semiconductor substrate 22.
Work function key-course 44a can be formed on gate insulator 42a.Specifically, work function key-course 44a can be conformally formed along the top surface in the sidewall of sept 48 and the first district 24.Therefore, work function key-course 44a can be recessed in shape.
Gate metal 46a can be formed on work function key-course 44a with filling groove 30.Namely, gate metal 46a can the remainder of filling groove 30.
With reference to Figure 35, the first interlayer dielectric 60 can be exposed.In order to expose the first interlayer dielectric 60, flatening process can be performed.Therefore, the grid structure 39 comprising gate insulator 42, work function key-course 44 and gate electrode 46 can be formed, and the top surface of the top surface of grid structure 39 and the first interlayer dielectric 60 can be in same plane.
Then, cover layer 53 can be formed on grid structure 39.Cover layer 53 can overlies gate structure 39, and gate insulator 42, work function key-course 44 and gate electrode 46 are not exposed.
Second interlayer dielectric 62 is formed on the first interlayer dielectric 60.Second interlayer dielectric 62 can cover cover layer 53.
Contact hole 70 can be formed as penetrating the first and second interlayer dielectrics 60 and 62 and exposing source/drain regions 52, contact metal layer 72 with contact 76 and be sequentially formed in each contact hole 70, complete the semiconductor device 3 of Fig. 3 thus.
The method of the manufacture semiconductor device 6 of the example embodiment according to the present invention's design is described now with reference to Fig. 6 to Fig. 8 and Figure 36 to Figure 57.For simplicity, the description of substantially the same with element described above element will be omitted.
Figure 36 to Figure 57 is the view of the step of the method for the manufacture semiconductor device 6 of the example embodiment illustrated according to the present invention's design.Specifically, Figure 36 to Figure 39 and Figure 55 is perspective view.Figure 40, Figure 42, Figure 43, Figure 45, Figure 47, Figure 49, Figure 51 and Figure 53 are the sectional view intercepted along the line A-A of Figure 39.Figure 41, Figure 44, Figure 46, Figure 48, Figure 50, Figure 52 and Figure 54 are the sectional view intercepted along the line B-B of Figure 39.Figure 56 is the sectional view intercepted along the line A-A of Figure 55.Figure 57 is the sectional view intercepted along the line B-B of Figure 55.In Figure 41, hard mask layer 117 is not illustrated.In Figure 55, the first and second interlayer dielectrics 130 and 132 are not illustrated.
With reference to Figure 36, fin F1 can be formed on the substrate 101.Fin F1 can give prominence to from substrate 101 on third direction Z1.Fin F1 can extend along second direction Y1 (it is length direction).Fin F1 can have the long side on second direction Y1 and the short side on first direction X1 (it is Width).But the present invention's design is not limited thereto.Such as, long side is to also can being first direction X1, and short side is to also can being second direction Y1.
Fin F1 can be the part of substrate 101, and can comprise the epitaxial loayer grown from substrate 101.Fin F1 can comprise the first material and the second material.
Specifically, substrate 101 can be made up of one or more semi-conducting materials being such as selected from the group be made up of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP.Substrate 101 also can be such as SOI substrate.
Fin F1 can comprise the first material and the second material.First material can be such as III element, and the second material can be such as V group element.III element can be at least one in such as Ga, In and Al.V group element can be at least one in such as P, As and Sb.Therefore, fin F1 can be made up of at least one in such as GaAs, InGaAs, AlGaAs, InAs, GaSb, InSb and InP.
Although the execution mode that wherein Semiconductor substrate 101 is made up of the material being different from fin F1 is described, the present invention's design is not limited thereto execution mode.As fin F1, substrate 101 also can comprise the first material and the second material.
With reference to Figure 37, field insulating layer 110 can be formed on the substrate 101 with the top surface of the exposure of the sidewall and substrate 101 that cover fin F1.Field insulating layer 110 can be made up of the material of at least one comprised in such as silicon oxide layer, silicon-nitride layer and silicon oxynitride layer.
Upper part with reference to Figure 38, fin F1 can be exposed by making the upper part of field insulating layer 110 recessed.Recessed technique can comprise such as selective etch technique.
In the alternative, the upper part projected upwards from field insulating layer 110 of fin F1 also can be formed by epitaxy technique.Such as, after formation field insulating layer 110, the top surface exposed by field insulating layer 110 of fin F1 can be utilized to perform epitaxy technique as seed crystal, formed thus fin F1 ledge and without the need to recessed technique.
Next, dummy gate electrode structure 111 is formed on fin F1 with crossing with fin F1.In Figure 38, dummy gate electrode structure 111 is with the right angle relative to fin F1, namely, crossing with fin F1 on first direction X1.But the present invention's design is not limited thereto.Such as, dummy gate electrode structure 111 also can with relative to the acute angle of first direction X1 and/or obtuse angle crossing with fin F1.
Dummy gate electrode structure 111 can comprise dummy gate electrode insulating barrier 113 and dummy gate electrode electrode 115.Dummy gate electrode insulating barrier 113 and dummy gate electrode electrode 115 can be sequentially stacking.
Dummy gate electrode insulating barrier 113 can be conformally formed along the upper part of exposure do not covered by field insulating layer 110 of the sidewall of fin F1 and the top surface of fin F1.In addition, dummy gate electrode insulating barrier 113 can be arranged between dummy gate electrode electrode 115 and field insulating layer 110.
Dummy gate electrode electrode 115 can be formed on dummy gate electrode insulating barrier 113.
Such as, dummy gate electrode electrode 115 can comprise such as polysilicon, and dummy gate electrode insulating barrier 113 can comprise such as silicon oxide layer.
Illusory hard mask layer 117 can be formed in dummy gate electrode structure 111.Illusory hard mask layer 117 can comprise at least one in such as Si oxide, silicon nitride and silicon nitrogen oxide.
With reference to Figure 39 to Figure 41, sept 121 is formed on one or more sidewalls of dummy gate electrode structure 111.Sept 121 can expose the top surface of hard mask layer 117.Sept 121 can comprise such as silicon nitride or silicon nitrogen oxide.
Next, can not etched by the ledge that dummy gate electrode structure 111 covers of fin F1.Fin F1 can utilize sept 121 and dummy gate electrode structure 111 to be etched as etching mask.
Then, source/drain regions 123 can be formed in fin F1 by etching part.Source/drain regions 123 can be overhead (elevated) source/drain regions.Therefore, the top surface of source/drain regions 123 can higher than the top surface of fin F1, as shown in figure 40.
In order to form nmos pass transistor, source/drain regions 123 can be made up of tensile stress material or the material identical with substrate 101.Such as, if substrate 101 is Si, then source/drain regions 123 can be made up of the material with the lattice constant less than the material of fin F1.
In the alternative, in order to form PMOS transistor, source/drain regions 123 can comprise the material such as compression material with the lattice constant larger than the material of fin F1.Compression material can by being applied to the fin F1 under dummy gate electrode structure 111 by compression, namely, and channel region and improve the mobility of the charge carrier in channel region.
Source/drain regions 123 can be formed by epitaxial growth.
In Figure 39, source/drain regions 123 is pentagonal.But the present invention's design is not limited thereto.Such as, source/drain regions 123 also can be quadrangle, circle, hexagon etc.
Fin F1 covered by dummy gate electrode structure 111 and the part crossing with dummy gate electrode structure 111 can be channel region.The channel region of fin F1 can be arranged between source/drain regions 123.
With reference to Figure 42, the first interlayer dielectric 130 can be formed as covering source/drain regions 123.First interlayer dielectric 130 can cover the sidewall of sept 121 and expose top surface and the hard mask layer 117 of sept 121.First interlayer dielectric 130 can comprise such as Si oxide.
With reference to Figure 43 and Figure 44, groove 135 can be formed as the channel region exposing fin F1.In the process forming groove 135, first, hard mask layer 117 can be removed.Hard mask layer 117 can be removed by flatening process.Flatening process also partly can etch the first interlayer dielectric 130.
Then, dummy gate electrode structure 111 can be removed.Specifically, dummy gate electrode electrode 115 and dummy gate electrode insulating barrier 113 can be removed to expose fin F1.Groove 135 is formed in the original residing position of dummy gate electrode structure 111.The madial wall of sept 121 can be exposed by groove 135.Groove 135 exposes the upper part of fin F1, namely, and channel region.
Native oxide layer 137 can be formed in the upper part exposed by groove 135 of fin F1.Native oxide layer 137 can be reacted by the upper part of fin F1 and oxygen and be formed.
With reference to Figure 45 and Figure 46, native oxide layer 137 can be removed by cleaning.
With reference to Figure 47 and Figure 48, the surface of the upper part of the exposure of fin F1, namely, the surface of channel region, can be oxidized by oxidation technology 139.Oxidation technology 139 can at 5atm or higher and 300 DEG C or higher execution 30 minutes to 2 hours.Alternatively, oxidation technology 139 can perform 30 minutes to 2 hours under 600 DEG C or higher high temperature.
With reference to Figure 49 and Figure 50, oxidation technology 139 can form oxide skin(coating) 141 on the surface of the upper part of fin F1.The reaction of the first and second materials that oxide skin(coating) 141 can be comprised by oxygen and fin F1 and being formed.In the oxidation technology 139 performed in the above conditions, the first material in fin F1 can than the second material in fin F1 and more oxygen atoms bond.Therefore, oxide skin(coating) 141 can comprise the oxide of more first material.
With reference to Figure 51 and Figure 52, oxide skin(coating) 141 can be removed.In order to remove oxide skin(coating) 141, wet etching process can utilize HF, NH 4oH, HCl etc. are performed as etchant.
The removal of oxide skin(coating) 141 can change the concentration of the first material and the concentration of the second material in the channel region of fin F1.The concentration of the first material little by little can increase from the surface of the channel region of fin F1 towards the inner side of channel region or inside in the channel region of fin F1.
Specifically, the channel region of fin F1 can comprise the first district 103 and the second district 105.First district 103 can be positioned at the surface of the channel region of fin F1, and the second district 105 can be arranged under the first district 103.The grid structure 151 will formed after first district 103 can contact, as shown in fig. 55.On the top surface that first district 103 can be arranged on fin F and sidewall.First district 103 can have the thickness of such as 1 to 20nm.
In the first district 103, the concentration of the first material little by little increases from the surface in the first district 103 towards the surface in contact second district 105 in the first district 103.Namely, the first material is less than the concentration of the first material in the surface in contact second district 105 in the first district 103 in the concentration at the top surface place in the first district 103.First material is 10% or less in the concentration at the top surface place in the first district 103.In the first district 103, the concentration of the first material is lower than the concentration of the second material.
In the first district 103, the concentration of the second material is higher than the concentration of the first material.Namely, in the top surface place in the first district 103 and the surface contacting the second district 105 in the first district 103, the concentration of the second material is higher than the first material.But the concentration of the second material reduces towards the basal surface in the first district 103, and difference between the concentration of the concentration of the second material and the first material reduces towards the basal surface in the first district 103.
First district 103 can comprise not by oxygen atom that wet etching process is removed.Oxygen atom can reduce from the top surface in the first district 103 towards the basal surface in the first district 103, and no longer can be present in the certain depth place from the top surface in the first district 103.Namely, the oxygen atom at the top surface place in the first district 103 is more than the oxygen atom of the bottom surface in the first district 103.At the top surface place in the first district 103, the concentration of oxygen atom can be 5% or less.
In the second district 105, the concentration of the first material can be substantially equal to the concentration of the second material.Here, term " substantially " not only represents accurately identical, and allows the surplus of contingent error during technique.Therefore, the concentration of the first material and the concentration of the second material can be unequal in the some parts in the second district 105.
In the second district 105, oxygen atom can exist hardly.
Each source/drain regions 123 can be separated the width of each sept 121 with the first district 103.Therefore, in the surface of the contact source/drain regions 123 of fin F1, the concentration of the first material can be substantially equal to the concentration of the second material.Namely, in the surface of the contact source/drain regions 123 in the second district 105, the concentration of the first material and the concentration of the second material can be substantially equal.
The first metal layer 155a and the second metal level 157a of reference Figure 53 and Figure 54, gate insulator 153a and formation gate electrode can sequentially be formed in groove 135.
Gate insulator 153a can be conformally formed along the sidewall of groove 135 and basal surface.In addition, gate insulator 153a can be conformally formed along the top surface of the upper part of the sidewall of field insulating layer 110, fin F1 and fin F1.Gate insulator 153a can also be formed on the first interlayer dielectric 130 with on the top surface of sept 121.Gate insulator 153a can contact the first district 103.
Gate insulator 153a can comprise such as silicon oxide layer or have the high k dielectric of the dielectric constant than Si oxide floor height.Gate insulator 153a can comprise and being such as selected from by such as HfSiON, HfO 2, ZrO 2, Al 2o 3, Ta 2o 5, TiO 2, SrTiO 3(Ba, Sr) TiO 3the material of the group formed.Gate insulator 153a can be formed to suitable thickness according to the type of the device that will be formed.
The first metal layer 155a can be formed on gate insulator 153a.The first metal layer 155a can be conformally formed along the sidewall of groove 135 and basal surface.In addition, the first metal layer 155a can be conformally formed along the top surface of the upper part of the sidewall of field insulating layer 110, fin F1 and fin F1.The first metal layer 155a can also be formed on the first interlayer dielectric 130 with on the top surface of sept 121.The first metal layer 155a regulates the work function of transistor.
Such as, if the first metal layer 155a is N-type work function key-course, it can comprise such as TiN.If the first metal layer 155a is N-type work function key-course, it can comprise at least one in such as TiAl, TiAlC, TiAlN, TaC, TiC and HfSi.
In the accompanying drawings, the first metal layer 155a is illustrated as individual layer.But the present invention's design is not limited thereto.Such as, the first metal layer 155a also can be by P type work function key-course and be arranged on the multilayer that the N-type work function key-course on P type work function key-course forms.
Second metal level 157a can be formed on the first metal layer 155a.Second metal level 157a can the remainder of filling groove 135.Second metal level 157a also can be formed on the first interlayer dielectric 130 with on the top surface of sept 121.In addition, the first metal layer 155a can be formed along the top surface of the upper part of the sidewall along field insulating layer 110, fin F1 and fin F1.
Second metal level 157a can comprise such as Al, W etc.
With reference to Figure 55 to Figure 57, grid structure 151 can be formed.Specifically, the resulting structures of Figure 53 and Figure 54 can perform flatening process to expose the first interlayer dielectric 130.As a result, the grid structure 151 comprising gate insulator 153, the first metal layer 155 and the second metal level 157 can be formed.
Gate insulator 153 in groove 135 and the first metal layer 155 can be recessed in shape.
With reference to Figure 56 and Figure 57, the second interlayer dielectric 132 can be formed on the first interlayer dielectric 130.Second interlayer dielectric 132 can overlies gate structure 151.
Second interlayer dielectric 132 can comprise the material identical with the first interlayer dielectric 130, and can comprise at least one in such as oxide skin(coating) and oxynitride layer.
Contact metal layer 191 is formed on the top surface of source/drain regions 123, and contact 193 is formed through the first and second interlayer dielectrics 130 and 132, completes the semiconductor device 6 of Fig. 6 to Fig. 8 thus.
Contact metal layer 191 can reduce the sheet resistance, contact resistance etc. of source/drain regions 123, and can comprise such as Pt, Ni, Co, Au, Al etc.
Contact 193 can comprise such as W, Al, Cu, etc.
Although described the preferred implementation of the present invention's design for illustrative purposes, it will be understood by those skilled in the art that different modification, interpolation and replacement are possible and do not deviate from the scope and spirit of disclosed the present invention's design in the claims.
This application claims the U.S. Provisional Patent Application No.61/930 enjoying and submitting on January 23rd, 2014, the priority of the korean patent application No.10-2014-0154660 that on November 7th, 656 and 2014 submits in Korean Intellectual Property Office, its content is quoted combined at this by entirety.

Claims (20)

1. a semiconductor device, comprising:
Semiconductor substrate, comprises III element and V group element; And
Grid structure, on the semiconductor substrate,
Wherein, described Semiconductor substrate comprises:
Firstth district, contacts the basal surface of described grid structure; And
Secondth district, is arranged under described firstth district,
The concentration of wherein said III element in described firstth district is lower than the concentration of described V group element in described firstth district, and the concentration of described III element in described secondth district is substantially equal to the concentration of described V group element in described secondth district.
2. semiconductor device according to claim 1, wherein said III element is at least one in Ga, In and Al, and described V group element is at least one in P, As and Sb.
3. semiconductor device according to claim 1, the concentration of wherein said III element in described firstth district increases from the top surface in described firstth district towards the basal surface in described firstth district.
4. semiconductor device according to claim 1, the top surface in wherein said firstth district comprises 5% or less oxygen atom.
5. semiconductor device according to claim 1, wherein said firstth district has the thickness of 1 to 20nm.
6. semiconductor device according to claim 1, wherein said grid structure comprises the gate insulator contacting described firstth district and the gate electrode be arranged on described gate insulator.
7. semiconductor device according to claim 1, also comprises the source/drain regions be arranged in the one side or the multi-lateral in described firstth district and the secondth district in described Semiconductor substrate.
8. semiconductor device according to claim 1, also comprises the substrate be arranged under described Semiconductor substrate.
9. a semiconductor device, comprising:
Substrate;
Fin, projects upwards from described substrate in a first direction, and comprises the first material and the second material; And
On described fin and the grid structure crossing with described fin,
Wherein said fin comprises the channel region be arranged under described grid structure, and the concentration of described first material in described channel region increases from the surface of described channel region towards the inside of described channel region.
10. semiconductor device according to claim 9, wherein said first material comprises III element, and described second material comprises V group element.
11. semiconductor device according to claim 9, the concentration of wherein said second material in described channel region reduces from the surface of described channel region towards the inside of described channel region.
12. semiconductor device according to claim 11, wherein in the surface of described channel region, the concentration of described second material is higher than the concentration of described first material.
13. semiconductor device according to claim 9, the concentration of wherein said first material in the surface of described channel region is 10% or less.
14. semiconductor device according to claim 9, wherein said grid structure comprises the gate insulator contacting described channel region and the gate electrode be arranged on described gate insulator.
15. semiconductor device according to claim 9, also comprise the source/drain regions be formed in the one side or the multi-lateral of described grid structure in described fin, wherein in the surface of the described source/drain regions of the contact of described fin, the concentration of described first material is substantially equal to the concentration of described second material.
16. 1 kinds of semiconductor device, comprising:
Semiconductor substrate, comprises III element and V group element; And
Grid structure, on the semiconductor substrate,
Wherein said Semiconductor substrate comprises:
Firstth district, contacts the basal surface of described grid structure; And
Secondth district, is arranged under described firstth district,
Wherein in the surface of described Semiconductor substrate, the concentration of described V group element is higher than the concentration of described III element.
17. semiconductor device according to claim 16, the concentration of wherein said III element in described firstth district increases from the top surface in described firstth district towards the basal surface in described firstth district.
18. semiconductor device according to claim 16, the concentration of wherein said III element in described secondth district is substantially equal to the concentration of described V group element in described secondth district.
19. semiconductor device according to claim 16, the concentration of wherein said III element in described firstth district is lower than the concentration of described V group element in described firstth district.
20. semiconductor device according to claim 16, wherein said III element is at least one in Ga, In and Al, and described V group element is at least one in P, As and Sb.
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