CN104867864A - Method for realizing local interconnection - Google Patents
Method for realizing local interconnection Download PDFInfo
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- CN104867864A CN104867864A CN201510142147.9A CN201510142147A CN104867864A CN 104867864 A CN104867864 A CN 104867864A CN 201510142147 A CN201510142147 A CN 201510142147A CN 104867864 A CN104867864 A CN 104867864A
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- insulating barrier
- local interlinkage
- contact hole
- deep trench
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000005530 etching Methods 0.000 claims abstract description 33
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 17
- 230000008859 change Effects 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims description 59
- 238000005516 engineering process Methods 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000000992 sputter etching Methods 0.000 claims description 7
- 238000004528 spin coating Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 230000008569 process Effects 0.000 abstract description 12
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 238000002360 preparation method Methods 0.000 abstract 1
- 229910052714 tellurium Inorganic materials 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 23
- 238000001259 photo etching Methods 0.000 description 8
- 238000003860 storage Methods 0.000 description 8
- 230000007704 transition Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007630 basic procedure Methods 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- -1 titanium nitrides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention relates to the technical field of the semiconductor structure and the preparation process thereof, especially to a method for realizing local interconnection. According to the invention, the existing etching process or a special etching process is used for forming a contact hole; and thus polycrystalline silicone in a deep trench is led out and is used as a local interconnection wire, thereby reducing an area used by the device interconnection and thus reducing the device area. Meanwhile, the structure and manufacturing process of the phase change memory are used and titanium nitride and germanium-stibium-tellurium materials are used for forming local interconnection wires, thereby manufacturing a larger resistor with optimized precision.
Description
Technical field
The present invention relates to semiconductor structure and preparing technical field thereof, particularly relate to a kind of technology using deep trench isolation technique to realize local interlinkage and make accurate large resistance on very little area.
Background technology
Modern electronic circuit is coupled together by specific electric path by the device be separated one by one, therefore must semiconductor device can be kept apart in integrated circuit fabrication, these devices are also wanted can interconnect to form required specific circuit structure subsequently.In the manufacture process of integrated circuit, same substrate often can exist multiple semiconductor device, we need to ensure the electric isolation between each device, and isolate the problems such as bad meeting causes electric leakage, breakdown potential is forced down, latch-up.Therefore isolation technology is a key technology in IC manufacturing, and the isolation technology between current semiconductor device has following several:
1, knot isolation, backgate diode is mainly utilized to realize, this technology is mainly used in the isolation between bipolar transistor, under current CMOS technology, the isolation of PMOS and NMOS can be realized by N trap, N trap and P type epitaxial loayer form the effect that PN junction plays isolation, and the area that this isolation technology takies is larger;
2, localized oxidation of silicon isolation (LOCOS), the general structure adopting LOCOS of field oxygen isolation between the MOS process devices of more than 0.5um, this technology utilizes silicon nitride (such as Si
3n
4) feature of film oxidation masking layer, first cover one deck silicon nitride in the active area of device, then grow the thicker oxide layer of one deck in the isolated area place exposed by wet-oxygen oxidation, finally remove silicon nitride layer, be formed with source region, making devices in active area.This structure fabrication is simple, but can form beak effect in isolated area, reduces the length of active area;
3, shallow trench isolation technology (STI), shallow trench isolation is from the isolation technology being main application under current CMOS technology, the basic procedure of shallow trench isolation technology is first deposit silicon nitride, then the groove of certain depth is eroded away in isolated area, carry out side wall oxidation again, with chemical vapor deposition (CVD) deposit silicon dioxide in the trench, finally by chemico-mechanical polishing (CMP) planarization, form channel separating zone and active area.Shallow trench isolation technology has more effective device isolation, the surface area of device can be made to reduce, have superpower latch protection ability, do not corrode raceway groove, and with the CMP (Chemical Mechanical Polishing) process advantage such as compatible mutually, but to be process costs more expensive, more complicated for shortcoming.
4, deep trench isolation technology (DTI), deep trench isolation technology can be applicable in the manufacturing process of semiconductor device.
At present, how to pass through to realize local interlinkage in the device architecture with deep trench, to reduce device interconnection level used, and reduce the area of device, can utilize the Structure and energy feature of phase transition storage under less area, make more accurate large resistance becomes the direction that those skilled in the art are devoted to research simultaneously.
Summary of the invention
For above-mentioned Problems existing, the present invention discloses a kind of method realizing local interlinkage, comprises the steps:
The substrate that one has a conduction type is provided;
In described substrate, form deep trench, and after the first insulating barrier is formed on the bottom of described deep trench and sidewall thereof, prepare electric conducting material and be full of described deep trench;
Etching removes described first insulating barrier of part and the described conductive material layer of part, after a shallow trench is formed on top in described deep trench, prepares the second insulating barrier and is full of described shallow trench;
Described in partial etching, the second insulating barrier forms contact hole, is drawn described electric conducting material to realize local interlinkage by described contact hole.
The above-mentioned method realizing local interlinkage, wherein, described conduction type is P type or N-type.
The above-mentioned method realizing local interlinkage, wherein, adopts the method for deep reaction ion etching to form deep trench in described substrate.
The above-mentioned method realizing local interlinkage, wherein, described electric conducting material is the polysilicon of doping.
The above-mentioned method realizing local interlinkage, wherein, described first insulating barrier and described second insulating barrier are oxide layer.
The above-mentioned method realizing local interlinkage, wherein, the step forming the first insulating barrier in the bottom of described deep trench and sidewall thereof comprises:
Carry out oxidation technology, form oxide layer in the bottom of described deep trench and sidewall thereof.
The above-mentioned method realizing local interlinkage, wherein, when the thickness of described second insulating barrier is less than set point, the step that the second insulating barrier described in partial etching forms contact hole comprises:
In described second insulating barrier upper surface spin coating photoresist, and this photoresist is exposed, develop to be formed and have
figurethe photoresist of shape window;
Have with this
figurethe photoresist of shape window is mask, adopts the side of ion etching
method portiondivide etching described second insulating barrier, to form described contact hole.
The above-mentioned method realizing local interlinkage, wherein, when the thickness of described second insulating barrier is more than or equal to described set point, the step that the second insulating barrier described in partial etching forms contact hole comprises:
In described second insulating barrier upper surface spin coating photoresist, and this photoresist is exposed, develop to be formed and have
figurethe photoresist of shape window;
Have with this
figurethe photoresist of shape window is mask, adopts the second insulating barrier described in etching technics partial etching, to form described contact hole.
The invention also discloses a kind of method realizing local interlinkage, comprise the steps:
There is provided a phase change memory structure, described phase change memory structure comprises the first oxide layer, Ge-Sb-Te material layer and titanium nitride layer and the second oxide layer successively according to order from bottom to up;
Described in partial etching, the second oxide layer forms contact hole, is drawn described titanium nitride layer and described Ge-Sb-Te material layer to realize local interlinkage by described contact hole.
The above-mentioned method realizing local interlinkage, wherein, forms described titanium nitride layer by the mode of ald.
The invention discloses the method realizing local interlinkage, utilize the feature of deep trench isolation technology, by increasing specific technique, etching can be carried out the insulating barrier being arranged in shallow trench and form contact hole, by contact hole, the polysilicon in deep trench is picked out the interconnection line being used as local, device level used can be reduced by the interconnection line of these local, thus reduce the area of device, the present invention also utilizes the Structure and energy feature of phase transition storage, titanium nitride and Ge-Sb-Te material are used as local interlinkage line, thus more accurate large resistance can be made under less area.
Accompanying drawing explanation
By reading with reference to following
accompanying drawingto the detailed description that non-limiting example is done, the present invention and feature, profile and advantage will become more apparent.All
in accompanying drawingidentical mark indicates identical part.Can proportionally not draw
accompanying drawing, focus on purport of the present invention is shown.
fig. 1a-1k is the flowage structure signal of the method realizing local interlinkage in the embodiment of the present invention one
figure;
fig. 2it is the flow process of the method realizing local interlinkage in the embodiment of the present invention one
figure;
fig. 3a is the structural representation of the phase transition storage being formed with contact hole in the embodiment of the present invention two
figure;
fig. 3b adopts " L " shape titanium nitride to do the structural representation of large resistance in the embodiment of the present invention two
figure;
Embodiment
Below in conjunction with
accompanying drawingthe present invention is further illustrated with specific embodiment, but not as limiting to the invention.
Embodiment one:
as Fig. 2shown in, present embodiments provide a kind of method realizing local interlinkage, specifically comprise the steps:
Step S1, provide the substrate 1 that has a conduction type, this conduction type can be P type or N-type, and this substrate 1 can be silicon substrate or epitaxial loayer,
as Fig. 1structure shown in a.
Step S2, forms one deck etch mask 2 in the surface of substrate 1, in an embodiment of the present invention, forms etch mask 2, formed by the method for chemical vapour deposition (CVD) in the surface of substrate 1
as Fig. 1structure shown in b.
Step S3, the upper surface in etch mask 2 deposits one deck photoresist, after exposure, development, is formed and has window
figurethe photoresistance of shape, with this photoresistance for mask forms photoetching window in etch mask 2,
as Fig. 1structure shown in c.
Step S4, continue in substrate 1, to form deep trench 3 with etch mask 2 for mask, in an embodiment of the present invention, deep trench isolation technique is adopted to form deep trench 3 in substrate 1, preferably, the method of deep reaction ion etching (DRIE) can be adopted to carry out deep plough groove etched to substrate 1, form this deep trench 3
as Fig. 1structure shown in d.
Step S5, remove etch mask 2, the technique removing this etch mask 2 can adopt technology well-known to those skilled in the art, and at this, just it will not go into details, is formed
as Fig. 1structure shown in e.
Step S6, after the first insulating barrier 4 is formed on the bottom of deep trench 3 and sidewall thereof, continues to prepare electric conducting material and is full of this deep trench 3,
as Fig. 1structure shown in h.
In the present invention's preferred embodiment, above-mentioned steps S6 specifically comprises the steps:
First, oxidation technology is carried out to substrate 1, to form the first insulating barrier 4, it can thus be appreciated that the material of this first insulating barrier 4 is silicon dioxide in substrate 1 surface and the bottom of deep trench 3 and sidewall thereof;
as Fig. 1structure shown in f.
Secondly, filled conductive material (such as polysilicon) in deep trench 3, preferably, the upper surface in deep trench 3 and substrate 1 forms polysilicon layer 5, and carries out CMP to this polysilicon layer 5, is formed
as Fig. 1structure shown in g.
Again, remove the polysilicon layer 5 and the first insulating barrier 4 that are positioned at substrate 1 surface, remaining first insulating barrier 4 covers bottom and the sidewall thereof of deep trench 3, and remaining polysilicon layer 5 is full of this deep trench 3,
as Fig. 1structure shown in h.
Preferably, this polysilicon layer 5 for having the polysilicon of doping, to reduce its resistivity.
Step S7, continues etching and removes part first insulating barrier 4 and partial polysilicon layer 5, form shallow trench 7, prepare the second insulating barrier 8 and be full of shallow trench 7 with top in deep trench 3;
as Fig. 1structure shown in j.
In the present invention's preferred embodiment, above-mentioned steps S7 is specially, and first exists
as Fig. 1the top of the semiconductor structure shown in h forms one deck isolated mask 6, and photoetching process formation etching window is carried out to this isolated mask 6, then with this isolated mask 6 for mask etching removes part first insulating barrier 4 and partial polysilicon layer 5, to form shallow trench 7 above deep trench 3
as Fig. 1structure shown in i; Remove isolated mask 6 afterwards, and prepare the second insulating barrier 8 and be full of shallow trench 7, and make the surface planarisation of substrate 1 by chemico-mechanical polishing, formed
as Fig. 1structure shown in j.
Preferably, the material of isolated mask 6 is Si
3n
4.
Preferably, the material of the second insulating barrier 8 is SiO
2.
Step S8, partial etching second insulating barrier 8 forms contact hole 9, is drawn to realize local interlinkage by polysilicon layer 5 by contact hole 9.
When the thickness of the second insulating barrier 8 is less than set point, (contact hole namely prepared in standard CMOS process can be connected with the polysilicon in deep trench, the thickness of the second more than setting shallow trench 7 upper surface insulating barrier 8 is at about 100nm ~ 400nm, (because the second insulating barrier 8 is just full of shallow trench 7 time such as: 100nm, 150nm, 200nm, 250nm or 400nm etc.), namely the thickness of the second insulating barrier 8 equals the degree of depth of shallow trench 7), contact hole 9 can be obtained by existing etching technics etching
as Fig. 1shown in k (a).Now, the concrete steps forming contact hole 9 are: first carry out photoetching, formation photoetching
figureshape window (namely in the second insulating barrier 8 upper surface spin coating photoresist, and exposes this photoresist, develops, have to be formed
figurethe photoresist of shape window), then formed according to photoetching
figureshape window, etches the second insulating barrier 8 in the method for second insulating barrier 8 place's ion etching, forms contact hole and (namely has with this
figurethe photoresist of shape window is mask, adopts the side of ion etching
method portiondivide etching second insulating barrier 8, to form contact hole 9), metal or other conductive material is filled afterwards in contact hole 9, prepare interconnection line 10 so more just the polysilicon in deep trench to be connected out, for the interconnection of local, the contact hole technique in standard CMOS process can be used, new technique need not be added.
(because the second insulating barrier 8 is just full of shallow trench 7 when the thickness of the second insulating barrier 8 is more than or equal to set point time, namely the thickness of the second insulating barrier 8 equals the degree of depth of shallow trench 7), the degree of depth etched by existing technique is inadequate, if therefore the polysilicon in deep trench will be picked out, this contact hole 9 is formed with regard to needing to add extra etching process, can not be shaping together with the contact hole in standard technology
as Fig. 1shown in k (b).Now, the concrete steps forming contact hole 9 are: first carry out photoetching, formation photoetching
figureshape window (namely in the second insulating barrier 8 upper surface spin coating photoresist, and exposes this photoresist, develops, have to be formed
figurethe photoresist of shape window), then formed according to photoetching
figureshape window, etches the second insulating barrier 8 at the second new etching technics in insulating barrier 8 place, forms contact hole and (namely has with this
figurethe photoresist of shape window is mask, adopts new etching technics partial etching second insulating barrier 8, to form contact hole 9), then polysilicon is picked out for local interlinkage.
Preferably, in an embodiment of the present invention, no matter (that is the thickness of the second insulating barrier 8 be how many, thickness regardless of the second insulating barrier 8 is more than or equal to or is less than set point), the manufacture craft making local interlinkage of the polysilicon in deep trench all needs to carry out before the manufacture craft of polysilicon gate.
Embodiment two:
Except utilizing deep trench isolation technology using the polysilicon in groove as except interconnection line, we also can utilize the titanium nitride in phase change memory structure and Ge-Sb-Te material to do interconnection line.
Concrete, the present embodiment relates to a kind of method realizing local interlinkage, comprises the steps:
First, one phase change memory structure is provided, phase change memory structure comprises the first oxide layer, Ge-Sb-Te material layer and titanium nitride layer and the second oxide layer successively according to order from bottom to up, because the method forming phase change memory structure is well known to those skilled in the art, in order to reduce repetition, at this, just it will not go into details.
Secondly, titanium nitride layer and Ge-Sb-Te material layer, to form contact hole, are drawn to realize local interlinkage by this contact hole by partial etching second oxide layer.
accompanying drawing 3a is the structure of phase transition storage
figure,
in figure103 is titanium nitride (TiN), can by the side of atomic deposition (ALD)
method is producedraw, in the technique of phase transition storage, the titanium nitride shape of formation is " L " shape, 102 is Ge-Sb-Te material (GST), because the resistivity of titanium nitride is very high, therefore can be used for doing interconnection line, 101 is silicon dioxide or silicon nitride, and 104 is oxides.Therefore by contact hole 105, titanium nitride and Ge-Sb-Te material are drawn to be used as local interlinkage line, thus reduce the area of device.The manufacture craft of local interlinkage is done after the manufacture craft of polysilicon gate, before the manufacture craft of metal 106 with titanium nitride and Ge-Sb-Te material.
In addition, with polysilicon or diffusion region do that resistance all can not do very large and accuracy is not high under existing standard CMOS technology, though resistance do very large, but area is very large, that is large resistance is with area greatly cost.In the technique of phase transition storage, the shape of titanium nitride formed be " L " shape, and the resistivity of titanium nitride is very high, and therefore we can do large resistance more accurately with the titanium nitride of formation, and reducing further along with process, it is less that area can do by we.
as Fig. 3shown in b,
in figure103 is the titanium nitrides forming " L " shape in phase transition storage technique, we just do resistance with it, 108 is contact hole, 107 is local interlinkage lines of two " L " shape resistance, can do interconnection line with silicide diffusion region, also can be other materials, and multiple " L " shape resistance just can couple together with local interlinkage by we like this, make very large resistance, and area is very little; Preferably, the technique of ald is adopted to form the titanium nitride being somebody's turn to do " L " shape.
In sum, the present invention utilizes deep trench isolation technology, by utilizing existing etching technics or increasing special etching technics, form contact hole and be used as local interlinkage line to be picked out by the polysilicon in deep trench, which reduce the area used by device interconnection, thus reduce the area of device, also utilize structure and the manufacturing process of phase transition storage simultaneously, titanium nitride and Ge-Sb-Te material are used as local interlinkage line, thus larger more accurate resistance can be produced.
It should be appreciated by those skilled in the art that those skilled in the art are realizing change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. realize a method for local interlinkage, it is characterized in that, comprise the steps:
The substrate that one has a conduction type is provided;
In described substrate, form deep trench, and after the first insulating barrier is formed on the bottom of described deep trench and sidewall thereof, prepare electric conducting material and be full of described deep trench;
Etching removes described first insulating barrier of part and the described conductive material layer of part, after a shallow trench is formed on top in described deep trench, prepares the second insulating barrier and is full of described shallow trench;
Described in partial etching, the second insulating barrier forms contact hole, is drawn described electric conducting material to realize local interlinkage by described contact hole.
2. realize the method for local interlinkage as claimed in claim 1, it is characterized in that, described conduction type is P type or N-type.
3. realize the method for local interlinkage as claimed in claim 1, it is characterized in that, adopt the method for deep reaction ion etching to form deep trench in described substrate.
4. realize the method for local interlinkage as claimed in claim 1, it is characterized in that, described electric conducting material is the polysilicon of doping.
5. realize the method for local interlinkage as claimed in claim 1, it is characterized in that, described first insulating barrier and described second insulating barrier are oxide layer.
6. realize the method for local interlinkage as claimed in claim 5, it is characterized in that, the step forming the first insulating barrier in the bottom of described deep trench and sidewall thereof comprises:
Carry out oxidation technology, form oxide layer in the bottom of described deep trench and sidewall thereof.
7. realize the method for local interlinkage as claimed in claim 1, it is characterized in that, when the thickness of described second insulating barrier is less than set point, the step that the second insulating barrier described in partial etching forms contact hole comprises:
In described second insulating barrier upper surface spin coating photoresist, and this photoresist is exposed, develop to be formed the photoresist with graphical window;
Have the photoresist of graphical window for mask with this, the second insulating barrier described in the method partial etching of employing ion etching, to form described contact hole.
8. realize the method for local interlinkage as claimed in claim 7, it is characterized in that, when the thickness of described second insulating barrier is more than or equal to described set point, the step that the second insulating barrier described in partial etching forms contact hole comprises:
In described second insulating barrier upper surface spin coating photoresist, and this photoresist is exposed, develop to be formed the photoresist with graphical window;
There is the photoresist of graphical window for mask with this, adopt the second insulating barrier described in etching technics partial etching, to form described contact hole.
9. realize a method for local interlinkage, it is characterized in that, comprise the steps:
There is provided a phase change memory structure, described phase change memory structure comprises the first oxide layer, Ge-Sb-Te material layer and titanium nitride layer and the second oxide layer successively according to order from bottom to up;
Described in partial etching, the second oxide layer forms contact hole, is drawn described titanium nitride layer and described Ge-Sb-Te material layer to realize local interlinkage by described contact hole.
10. realize the method for local interlinkage as claimed in claim 9, it is characterized in that, form described titanium nitride layer by the mode of ald.
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| CN1628387A (en) * | 2002-06-14 | 2005-06-15 | 国际商业机器公司 | Enhanced structure and method for buried local interconnects |
| CN1702883A (en) * | 2004-05-27 | 2005-11-30 | 三星电子株式会社 | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same |
| WO2008144173A1 (en) * | 2007-05-14 | 2008-11-27 | Micron Technology, Inc. | Variable resistance memory device having reduced bottom contact area and method of forming the same |
| US20110018094A1 (en) * | 2009-07-21 | 2011-01-27 | International Business Machines Corporation | Bias-controlled deep trench substrate noise isolation integrated circuit device structures |
| US20120205777A1 (en) * | 2011-02-14 | 2012-08-16 | Lee Sang-Hyun | Semiconductor device and method for fabricating the same |
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