CN104867522A - High-speed low-power consumption charge pump SRAM and implementation method therefor - Google Patents
High-speed low-power consumption charge pump SRAM and implementation method therefor Download PDFInfo
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- CN104867522A CN104867522A CN201510300151.3A CN201510300151A CN104867522A CN 104867522 A CN104867522 A CN 104867522A CN 201510300151 A CN201510300151 A CN 201510300151A CN 104867522 A CN104867522 A CN 104867522A
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Abstract
The invention discloses a high-speed low-power consumption charge pump SRAM and an implementation method therefor, and the charge pump SRAM comprises an SRAM unit and a charge pump circuit; one end of the charge pump circuit is connected to a bit line of the SRAM unit while the other end is connected to a power source network, and the charge pump circuit is used for temporarily storing the charge discharged by the bit line of the SRAM unit into a capacitor, and transferring the charge stored in the capacitor into the power source network in a capacitor serial connection boosting manner; through the invention, power consumption of write operation of the SRAM is effectively reduced, and the write operation time of the SRAM is obviously shortened than that of the existing charge pump SRAM technology.
Description
Technical field
The present invention relates to a kind of static RAM, particularly relate to a kind of high-speed low-power-consumption charge pump SRAM and its implementation.
Background technology
Static RAM (Static Random Access Memory, be called for short SRAM) is one of important component part indispensable in electronic system.It is for the interim storage of data or instruction, have speed fast, low in energy consumption, be easy to the advantages such as embedded integration, so be the first-selected device of buffer memory in central processing unit (CentralProcessing Unit is called for short CPU).In modern high performance processor, the area of chip shared by SRAM is more than 90%.The coming years, along with the explosive growth of mobile Internet, Internet of Things and wearable electronic, the power consumption of chip will be subject to strict requirement and stern challenge, and SRAM stands in the breach.
Also have people to analyze the power consumption of each ingredient in SRAM circuit, the power consumption of its neutrality line (BitLine is called for short BL) discharge and recharge is the maximum consumption source of power consumption in SRAM, especially when write operation.First be that pairs of bit line discharge and recharge is exactly the charge and discharge to its electric capacity in fact because the electric capacity of bit line is very large; The second, the frequency of utilization of bit line is very high, operates (writing data or read data) at every turn all will be realized by bit line SRAM; 3rd, the bit line quantity simultaneously operated is a lot, wordline (Word Line in SRAM, be called for short WL) also possess above a few point patterns, and the parasitic capacitance value of single wordline is also greater than single bit line usually, but both power consumptions differ larger in the ratio of entirety, mainly because single job only has 1 wordline selected, and bit line is N velamen chooses, wherein N is the bit wide of data, in initial Computer Design, bus is 8bit bit wide, now normally 64bit bit wide, so single job bit line dynamic power consumption approximates greatly the N of wordline doubly; 4th, during write operation, bit line is full swing upset, the electric discharge namely from VDD to GND; Due to the introducing of sense amplifier, during read operation, bit line only has a very little voltage swing (the concrete numerical value of voltage swing depends on the precision of sense amplifier), so, power consumption when read operation is greater than for the power consumption bit line itself during write operation.
For above shortcoming, also occurred a kind of technology adopting charge pump on SRAM bit line at present, as shown in Figure 1, signal timing diagram as shown in Figure 2 for its circuit diagram.The step of this method is: the first, with electric charge on bit line during charge pump collection write operation; The second, complete write operation; 3rd, then the electric charge come will be collected from bit line, the principle of being boosted by charge pump is rotated back on bit line.This method has effectively reclaimed on bit line to be needed originally by the electric charge of releasing, and reaches the effect reducing power consumption.But, must wait for that (critical path of write operation is in Fig. 2 after above three steps complete, CLK1 rising edge starts to terminate to CLK2 negative edge), just can complete a write operation, carry out next operation, and these three steps extend the time of SRAM write operation, especially first and third step, time delay substantially exceeds second step.This sacrifices the performance of SRAM, makes it can not meet the designing requirement of High Speed System.
Summary of the invention
For overcoming the deficiency that above-mentioned prior art exists, one of the present invention object is to provide a kind of high-speed low-power-consumption charge pump SRAM and its implementation, it is by being connected on the bit line of SRAM by charge pump circuit, electric charge of being released by bit line is temporarily stored in the electric capacity of charge pump circuit, and the mode that the electric charge stored in electric capacity is boosted by capacitances in series is transferred to electric power network again, effectively can reduce the power consumption of SRAM write operation, and the write operation time of SRAM is significantly shortened than existing charge pump SRAM technology.
For reaching above-mentioned and other object, the present invention proposes a kind of high-speed low-power-consumption charge pump SRAM, comprise sram cell, this charge pump SRAM also comprises charge pump circuit, described charge pump circuit one end is connected on the bit line of described sram cell, the other end is connected to electric power network, and described charge pump circuit is temporarily stored in electric capacity for electric charge of being released by the bit line of described sram cell, and the mode that the electric charge stored in electric capacity is boosted by capacitances in series is transferred to electric power network.
Further, described charge pump circuit comprises n electric capacity (C1-Cn) and 3n-2 switch (S3-S (3n)), electric capacity (C1) one terminated nodes Node1, another terminated nodes Node2, Node2 is ground, electric capacity (Ck) meets node Node (2k-1) and node Node (2k), switch S (3k-3) is connected between node Node (2k-3) and node Node (2k-1), switch S (3k-2) is connected between node Node (2k-3) and node Node (2k), switch S (3k-1) is connected between node Node (2k) and ground, switch S (3n) is connected between node Node (2n-1) and power supply, k=2, n.
Further, described charge pump circuit is connected on the bit line of described sram cell by switch.
Further, each switch is made up of a NMOS or PMOS transistor.
Further, each switch is made up of a transmission gate.
Further, the switch that described charge pump circuit is connected with described sram cell is controlled by decoding by the data inputted.
Further, switch S (3k-3), S (3k-1) are controlled by control signal (CLK1), k=2 ..., n.
Further, switch S (3k-2), S (3n) are controlled by control signal CLK2, k=2 ..., n.
Further, under pre-charge state, the all bit lines of sram cell are all pre-charged to noble potential, the data write realize the change of two bit-line voltage differences by the switch (S1, S2) controlled between described sram cell and described charge pump circuit, under pre-charge state, two switches are all in closed condition; Open in switch (S1) or switch (S2), control signal (CLK1) make electric capacity in described charge pump circuit and sram cell bit line in parallel; Described switch (S1) and switch (S2) are closed, and the wordline of described sram cell is opened, and bit line is communicated with internal element, and the voltage difference of bit line is written to unit inside; Again enter pre-charge state, bit line carries out charging operations, and the control signal (CLK2) in described charge pump circuit makes the electric capacity in charge pump circuit become to be connected in series, and opens the switch of charge pump and electric power network.
For achieving the above object, the present invention also provides the implementation method of a kind of high-speed low-power-consumption charge pump SRAM, comprises the steps:
Step one, the pre-charge state before write operation, all bit lines of sram cell are all pre-charged to noble potential;
Step 2, the write operation first step, open for one in the switch (S1) that charge pump circuit is connected with sram cell or switch (S2), and control signal (CLK1) make the electric capacity in described charge pump circuit and sram cell bit line in parallel;
Step 3, write operation second step, the switch (S1) be connected with sram cell by described charge pump circuit and switch (S2) are closed, the wordline of described sram cell is opened, bit line is communicated with internal element, and the voltage difference of bit line is written to unit inside, and write operation completes;
Step 4, again enter pre-charge state, bit line carries out charging operations, and the control signal (CLK2) in described charge pump circuit makes the electric capacity in described charge pump circuit become to be connected in series, and opens the switch of described charge pump circuit and electric power network.
Compared with prior art, charge pump circuit is connected on the bit line of SRAM by the present invention a kind of high-speed low-power-consumption charge pump SRAM and its implementation, electric charge of being released by bit line is temporarily stored in the electric capacity of charge pump circuit, and the mode that the electric charge stored in electric capacity is boosted by capacitances in series is transferred to electric power network again, charge pump circuit of the present invention to electric power network charge operate in pre-charge state under complete, so do not take the clock period of write operation, improve the performance of SRAM, power saving effect is almost constant simultaneously.
Accompanying drawing explanation
Fig. 1 is prior art neutrality line charge pump SRAM schematic diagram;
Fig. 2 is prior art neutrality line charge pump SRAM write operation signal sequential chart;
Fig. 3 is the structural representation of a kind of high-speed low-power-consumption charge pump of the present invention SRAM;
Fig. 4 is the charge pump SRAM write operation signal sequential chart that the present invention proposes;
Fig. 5 is that the charge pump SRAM that the present invention proposes collects bit line charge state of switch schematic diagram;
Fig. 6 is the switch schematic diagram of the charge pump SRAM data write state that the present invention proposes;
Fig. 7 be charge pump SRAM electric charge that the present invention proposes again enter pre-charge state simultaneously Charger transfer to electric power network state of switch schematic diagram;
Fig. 8 is the flow chart of steps of the implementation method of a kind of high-speed low-power-consumption charge pump of the present invention SRAM.
Embodiment
Below by way of specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention is also implemented by other different instantiation or is applied, and the every details in this instructions also can based on different viewpoints and application, carries out various modification and change not deviating under spirit of the present invention.
Fig. 3 is the structural representation of a kind of high-speed low-power-consumption charge pump of the present invention SRAM.As shown in Figure 3, a kind of high-speed low-power-consumption charge pump of the present invention SRAM, comprising: sram cell 10 and charge pump circuit 20.
Wherein, sram cell 10 is identical with SRAM cell structure of the prior art, and in present pre-ferred embodiments, for 6 pipe elementary cells, but the present invention is not only applicable to the SRAM of 6 pipe elementary cells, is applicable in the SRAM elementary cell of other types simultaneously; Charge pump circuit 20 one end is connected on the bit line (BL/BL_N) of sram cell 10 by switch (being illustrated as S1, S2), the other end is connected to electric power network VDD, charge pump circuit 20 is temporarily stored in electric capacity for electric charge of being released by the bit line of sram cell 10, and the mode that the electric charge stored in electric capacity is boosted by capacitances in series is transferred to electric power network VDD again.Wherein, charge pump circuit 20 comprises some electric capacity and some switches.
Particularly, please refer to shown in Fig. 3, 10 is basic sram cell, it is connected with wordline WL, precharge control line PRE, bit line BL and BL_N, its bit line BL and BL_N is connected to the node 1 (Node1) of the charge pump circuit 20 of the present invention respectively by switch S 1 and S2, charge pump circuit 20 comprises n electric capacity C1-Cn, 3n-2 switch S 3-S (3n), wherein electric capacity C1 mono-terminated nodes 1 (Node1), another terminated nodes 2 (Node2), node 2 (Node2) is ground, electric capacity Ck connects node (2k-1) (Node (2k-1)) and node (2k) (Node (2k)), switch S (3k-3) is connected between node (2k-3) (Node (2k-3)) and node (2k-1) (Node (2k-1)), switch S (3k-2) is connected between node (2k-3) (Node (2k-3)) and node (2k) (Node (2k)), switch S (3k-1) is connected between node (2k) (Node (2k)) and ground, switch S (3n) is connected between node (2n-1) (Node (2n-1)) and power vd D, k=2, n.
In the specific embodiment of the invention, charge pump circuit 20 adopts 4 electric capacity, but the present invention is not as limit, particularly, charge pump circuit 20 comprises electric capacity C1, C2, C3, C4 and switch S 3, S4, S5, S6, S7, S8, S9, S10, S11, S12, wherein, the two ends of C1 are connected with node Node2 with node Node 1; The two ends of C2 are connected with node Node 4 with node Node 3; The two ends of C3 are connected with node Node 6 with node Node 5; The two ends of C4 are connected with node Node 8 with node Node 7.The two ends of switch S 3 are connected with node Node 3 with node Node 1; The two ends of switch S 4 are connected with node Node 4 with node Node 1; The two ends of switch S 5 are connected with ground wire (GND) with node Node 4; The two ends of switch S 6 are connected with node Node 5 with node Node 3; The two ends of switch S 7 are connected with node Node6 with node Node 3; The two ends of switch S 8 are connected with GND with node Node 6; The two ends of switch S 9 are connected with node Node 7 with node Node5; The two ends of switch S 10 are connected with node Node 8 with node Node 5; The two ends of switch S 11 are connected with GND with node Node 8; The two ends of switch S 12 are connected with power supply (VDD) with node Node 7.Node Node 1 accesses the bit line of SRAM simultaneously; Node Node 2 connects GND.
Wherein, each switch S 1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12 can be made up of a NMOS or PMOS transistor, also can be made up of a transmission gate.Switch S 1 and S2 are controlled by decoding by the data inputted; Switch S 3, S5, S6, S8, S9, S11 are controlled by control signal CLK1; Switch S 4, S7, S10, S12 are controlled by control signal CLK2, as shown in Figure 4.
Below coordinate Fig. 3 and Fig. 4 that principle of work of the present invention is described:
1), under pre-charge state, all bit lines are all pre-charged to noble potential.The data write, by gauge tap S1, S2, realize the change of two bit-line voltage differences, and under pre-charge state, two switches are all in closed condition.
3) the write operation first step.Switch S 1 or S2 have one to open.Control signal CLK1 make electric capacity in charge pump circuit and sram cell bit line in parallel.Namely the electric charge in the electric capacity share bit lines allowing in charge pump, by the charge storage of bit line in the electric capacity of charge pump, makes the voltage of bit line reduce simultaneously.The data write just are reflected in the voltage difference of two bit lines, i.e. the difference of the magnitude of voltage of two bit lines, represent the difference of data " 0 " and " 1 " that will write.
3) write operation second step.Switch S 1 and S2 close.(wordline WL represents the wordline of sram cell, opens as shown in Figure 4), and bit line is communicated with internal element, and the voltage difference of bit line is written to unit inside.At this moment write operation completes.
4) again pre-charge state is entered.Bit line carries out charging operations.Control signal CLK2 in charge pump circuit makes the electric capacity in charge pump circuit become to be connected in series, and opens the switch of charge pump and electric power network.Electric power network itself magnitude of voltage higher than supply voltage can be obtained, because can be equivalent to a huge electric capacity, so can by the Charger transfer in charge pump in electric power network after capacitances in series.
Embodiment
Suppose to write data " 0 " in sram cell.
1) pre-charge state before write operation, all bit lines are all pre-charged to noble potential.
2) the write operation first step, as shown in Figure 5.Because the data that will write are " 0 ", switch S 1 is opened.Control signal CLK1 makes switch S 3, S5, S6, S8, S9, S11 open, and switch S 4, S7, S10, S12 close.At this moment bit line BL shares electric charge with electric capacity C1, C2, C3, the C4 in charge pump, therefore the voltage drop of BL.And the voltage of BL_N to remain on VDD constant.
3) write operation second step, as shown in Figure 6.Switch S 1 and S2 close.The wordline (WL) of SRAM is opened.Reduce at the voltage of previous step neutrality line BL, the voltage of bit line BL_N remains unchanged.So data " 0 " can be written in sram cell smoothly.At this moment write operation completes, and namely data " 0 " are stored in sram cell.
4) again pre-charge state is entered, as shown in Figure 7.Signal PRE is " 0 ", and bit line BL and BL_N carries out charging operations.Meanwhile, the control signal CLK2 in charge pump makes switch S 4, S7, S10, S12 open, and switch S 3, S5, S6, S8, S9, S11 close.Electric capacity C1, C2, C3, C4 series connection in charge pump, will obtain a magnitude of voltage higher than supply voltage at Node 7 node, the electric charge of Node 7 node will be transferred in electric power network and go.
Fig. 8 is the flow chart of steps of the implementation method of a kind of high-speed low-power-consumption charge pump of the present invention SRAM.As shown in Figure 8, the implementation method of a kind of high-speed low-power-consumption charge pump of the present invention SRAM, comprises the steps:
Step 801, the pre-charge state before write operation, all bit lines of sram cell are all pre-charged to noble potential;
Step 802, the write operation first step.One is had to open in the switch S 1 be connected with sram cell by charge pump circuit or S2, and control signal CLK1 make electric capacity in charge pump circuit and sram cell bit line in parallel, namely the electric charge in the electric capacity share bit lines allowing in charge pump, by the charge storage of bit line in the electric capacity of charge pump, make the voltage of bit line reduce simultaneously.The data write just are reflected in the voltage difference of two bit lines, i.e. the difference of the magnitude of voltage of two bit lines, represent the difference of data " 0 " and " 1 " that will write;
Step 803, write operation second step.The switch S 1 be connected with sram cell by charge pump circuit and S2 close.The wordline of sram cell is opened, and bit line is communicated with internal element, and the voltage difference of bit line is written to unit inside.At this moment write operation completes;
Step 804, enters pre-charge state again, and bit line carries out charging operations, and the control signal CLK2 in charge pump makes the electric capacity in charge pump become to be connected in series, and opens the switch of charge pump and electric power network.Electric power network itself magnitude of voltage higher than supply voltage can be obtained, because can be equivalent to a huge electric capacity, so can by the Charger transfer in charge pump circuit in electric power network after capacitances in series.
In sum, charge pump circuit is connected on the bit line of SRAM by the present invention a kind of high-speed low-power-consumption charge pump SRAM and its implementation, electric charge of being released by bit line is temporarily stored in the electric capacity of charge pump circuit, and the mode that the electric charge stored in electric capacity is boosted by capacitances in series is transferred to electric power network again, compared with prior art, charge pump circuit of the present invention to electric power network charge operate in pre-charge state under complete, so do not take the clock period of write operation, improve the performance of SRAM, power saving effect is almost constant simultaneously.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can carry out modifying to above-described embodiment and change.Therefore, the scope of the present invention, should listed by claims.
Claims (10)
1. a high-speed low-power-consumption charge pump SRAM, comprise sram cell, it is characterized in that: this charge pump SRAM also comprises charge pump circuit, described charge pump circuit one end is connected on the bit line of described sram cell, the other end is connected to electric power network, described charge pump circuit is temporarily stored in electric capacity for electric charge of being released by the bit line of described sram cell, and the mode that the electric charge stored in electric capacity is boosted by capacitances in series is transferred to electric power network.
2. a kind of high-speed low-power-consumption charge pump SRAM as claimed in claim 1, it is characterized in that: described charge pump circuit comprises n electric capacity (C1-Cn) and 3n-2 switch (S3-S (3n)), electric capacity (C1) one terminated nodes Node1, another terminated nodes Node2, Node2 is ground, electric capacity (Ck) meets node Node (2k-1) and node Node (2k), switch S (3k-3) is connected between node Node (2k-3) and node Node (2k-1), switch S (3k-2) is connected between node Node (2k-3) and node Node (2k), switch S (3k-1) is connected between node Node (2k) and ground, switch S (3n) is connected between node Node (2n-1) and power supply, k=2, n.
3. a kind of high-speed low-power-consumption charge pump SRAM as claimed in claim 2, is characterized in that: described charge pump circuit is connected on the bit line of described sram cell by switch.
4. a kind of high-speed low-power-consumption charge pump SRAM as claimed in claim 3, is characterized in that: each switch is made up of a NMOS or PMOS transistor.
5. a kind of high-speed low-power-consumption charge pump SRAM as claimed in claim 3, is characterized in that: each switch is made up of a transmission gate.
6. a kind of high-speed low-power-consumption charge pump SRAM as claimed in claim 3, is characterized in that: the switch that described charge pump circuit is connected with described sram cell is controlled by decoding by the data inputted.
7. a kind of high-speed low-power-consumption charge pump SRAM as claimed in claim 6, is characterized in that: switch S (3k-3), S (3k-1) are controlled by control signal (CLK1), k=2 ..., n.
8. a kind of high-speed low-power-consumption charge pump SRAM as claimed in claim 6, is characterized in that: switch S (3k-2), S (3n) are controlled by control signal (CLK2), k=2 ..., n.
9. a kind of high-speed low-power-consumption charge pump SRAM as claimed in claim 8, it is characterized in that: under pre-charge state, the all bit lines of sram cell are all pre-charged to noble potential, the data write realize the change of two bit-line voltage differences by the switch (S1, S2) controlled between described sram cell and described charge pump circuit, under pre-charge state, two switches are all in closed condition; Open in switch (S1) or switch (S2), control signal (CLK1) make electric capacity in described charge pump circuit and sram cell bit line in parallel; Described switch (S1) and switch (S2) are closed, and the wordline of described sram cell is opened, and bit line is communicated with internal element, and the voltage difference of bit line is written to unit inside; Again enter pre-charge state, bit line carries out charging operations, and the control signal (CLK2) in described charge pump circuit makes the electric capacity in charge pump circuit become to be connected in series, and opens the switch of charge pump and electric power network.
10. an implementation method of high-speed low-power-consumption charge pump SRAM, comprises the steps:
Step one, the pre-charge state before write operation, all bit lines of sram cell are all pre-charged to noble potential;
Step 2, the write operation first step, open for one in the switch (S1) that charge pump circuit is connected with sram cell or switch (S2), and control signal (CLK1) make the electric capacity in described charge pump circuit and sram cell bit line in parallel;
Step 3, write operation second step, the switch (S1) be connected with sram cell by described charge pump circuit and switch (S2) are closed, the wordline of described sram cell is opened, bit line is communicated with internal element, and the voltage difference of bit line is written to unit inside, and write operation completes;
Step 4, again enter pre-charge state, bit line carries out charging operations, and the control signal (CLK2) in described charge pump circuit makes the electric capacity in described charge pump circuit become to be connected in series, and opens the switch of described charge pump circuit and electric power network.
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| CN201510300151.3A CN104867522B (en) | 2015-05-31 | 2015-05-31 | A kind of high-speed low-power-consumption charge pump SRAM and its implementation |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109979505A (en) * | 2017-12-28 | 2019-07-05 | 展讯通信（上海）有限公司 | SRAM write circuit |
| CN113497836A (en) * | 2020-04-01 | 2021-10-12 | 北京小米移动软件有限公司 | Distance sensor, control method thereof and mobile terminal |
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| CN1200547A (en) * | 1997-02-03 | 1998-12-02 | 松下电器产业株式会社 | Charge pump circuit and logic circuit |
| US20020163839A1 (en) * | 2001-05-07 | 2002-11-07 | Jeung Seong-Ho | Methods of reading and/or writing data to memory devices including virtual ground lines and/ or multiple write circuits and related devices |
| CN1467748A (en) * | 2002-06-07 | 2004-01-14 | 三星电子株式会社 | Pump circuits and methods for integrated circuits |
| CN101178931A (en) * | 2006-11-09 | 2008-05-14 | 天利半导体（深圳）有限公司 | Low-power consumption SRAM circuit structure design capable of realizing high speed write and windows write |
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- 2015-05-31 CN CN201510300151.3A patent/CN104867522B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1200547A (en) * | 1997-02-03 | 1998-12-02 | 松下电器产业株式会社 | Charge pump circuit and logic circuit |
| US20020163839A1 (en) * | 2001-05-07 | 2002-11-07 | Jeung Seong-Ho | Methods of reading and/or writing data to memory devices including virtual ground lines and/ or multiple write circuits and related devices |
| CN1467748A (en) * | 2002-06-07 | 2004-01-14 | 三星电子株式会社 | Pump circuits and methods for integrated circuits |
| CN101178931A (en) * | 2006-11-09 | 2008-05-14 | 天利半导体（深圳）有限公司 | Low-power consumption SRAM circuit structure design capable of realizing high speed write and windows write |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109979505A (en) * | 2017-12-28 | 2019-07-05 | 展讯通信（上海）有限公司 | SRAM write circuit |
| CN109979505B (en) * | 2017-12-28 | 2020-10-27 | 展讯通信（上海）有限公司 | SRAM write circuit |
| CN113497836A (en) * | 2020-04-01 | 2021-10-12 | 北京小米移动软件有限公司 | Distance sensor, control method thereof and mobile terminal |
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| CN104867522B (en) | 2017-12-22 |
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