CN104866457B - A kind of chip multi-core processor static framework based on shared buffer memory - Google Patents

Abstract

The invention discloses a static architecture of an on-chip multi-core processor based on a shared cache, which includes n nodes, where n is an even number greater than 0, and the nodes include n/2 A-type nodes and n/2 B-type nodes ; Class A nodes include processing core, local private cache L1, and router R; class B nodes include processing core, local private cache L1, router R, and shared cache l2bank; nodes communicate through routers; class A nodes It is intermittently distributed with class B nodes; the capacity of the shared cache l2bank is twice that of the shared cache in the general architecture. The present invention provides a static architecture of an on-chip multi-core processor based on a shared cache, which saves the hardware overhead of the last level of cache without increasing the access delay of the entire on-chip network and the degree of congestion of the entire on-chip network and area, saving cache static power.

Description

A Static Architecture of On-Chip Multi-Core Processor Based on Shared Cache

technical field

The invention relates to a static architecture of an on-chip multi-core processor based on a shared cache.

Background technique

As shown in Figure 1, a commonly used network-on-chip multi-core processor architecture, we take the commonly used 16-core, L2 cache as an example, this commonly used structure consists of 16 nodes, each node includes a communication The router R, processing core and local private cache L1 and a larger shared cache l2bank, because the structure is based on the shared cache mechanism for data interaction and communication, and the shared cache l2bank accounts for the entire on-chip network The area is very large, so it has a great impact on power consumption, especially the proportion of static power consumption.

From Figure 1, we can see that each processor core is connected to a shared cache l2bank, because in the process of program access, reading and writing data may need to read and write the shared memory where the processor core core is relatively far away. Cache the data stored in l2bank, so when doing static design, the average number of hops (the average distance between cores accessing the shared cache l2bank) and the congestion problem of the entire network (to ensure fairness) during the data interaction process are all factors that need to be considered , the requirements for data storage are getting bigger and bigger, and the area of the shared cache l2bank is also getting bigger and bigger, so the ratio of its static power consumption to the entire on-chip network is also showing a growing trend. The power consumption problem caused by too large area has also become a problem that cannot be ignored.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art, to provide a static architecture of multi-core processors on a chip based on a shared cache, and save The hardware overhead and area of the last level cache are reduced, and the static power consumption of the cache is saved.

The object of the present invention is achieved through the following technical solutions: a static architecture based on a shared cache on-chip multi-core processor, which includes n nodes, where n is an even number greater than 0, and the nodes include n/2 class A node and n/2 class B nodes; the class A node includes processing core core, local private cache L1 and router R; the class B node includes processing core core, local private cache L1, router R and Shared cache l2bank; said nodes communicate through routers; said A-type nodes and B-type nodes are intermittently distributed; said shared cache l2bank has twice the capacity of the shared cache in the general architecture.

The number of said nodes is 16, including 8 said A-type nodes and 8 said B-type nodes.

The local private cache L1 includes instruction cache and data cache.

The beneficial effects of the present invention are: (1) It can ensure that the average distance of accessing the shared cache l2bank is the same as the average distance of the general architecture, so that the access delay of the entire network on chip will not be additionally increased.

(2) In the hardware design process of the present invention, each shared cache l2bank structure is the same as the traditional one, except that the storage space is doubled, and the number of shared cache l2banks is reduced to half of the original, that is, the entire last level cache The shared cache capacity is the same as that of the general-purpose architecture, which is used to meet the needs of data storage; but reducing the l2bank by half also reduces the peripheral hardware overhead by half, such as the number of amplifiers and decoders. We have reduced by half, so The hardware design area will also be reduced, and the static power consumption of the cache will be reduced.

(3) The nodes that include the shared cache l2bank and the nodes that do not include the shared cache l2bank are intermittently distributed. In the process of data interaction, fairness can be guaranteed without causing network congestion.

Description of drawings

FIG. 1 is a schematic diagram of a commonly used network-on-chip multi-core processor architecture;

Fig. 2 is a structural schematic diagram of the present invention.

Detailed ways

The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

As shown in Fig. 2, a kind of on-chip multi-core processor static architecture based on shared cache, it includes n nodes, n is an even number greater than 0, and described nodes include n/2 A-type nodes and n/2 B Class node; said class A node includes processing core core, local private cache L1 and router R; said class B node includes processing core core, local private cache L1, router R and shared cache l2bank; said Nodes communicate through routers; the A-type nodes and B-type nodes are intermittently distributed; the capacity of the shared cache l2bank is twice that of the shared cache in the general architecture.

The number of said nodes is 16, including 8 said A-type nodes and 8 said B-type nodes.

The local private cache L1 includes instruction cache and data cache.

It can be seen from Figure 2 that the distribution of A-type nodes that do not include shared cache l2bank and B-type nodes that include shared cache l2bank, the 16 nodes shown in the figure are distributed in four rows and four columns, regardless of horizontal or vertical , every two class A nodes contain a class B node, and every two class B nodes contain a class A node; this is the intermittent distribution mentioned above.

Claims (1)

1. a kind of on-chip multi-core processor based on shared cache, it is characterized in that, its static framework is: it comprises n nodes, and n is the even number greater than 0, and described node comprises n/2 class A nodes and n/ 2 class B nodes; the class A node includes processing core core, local private cache L1 and router R; the class B node includes processing core core, local private cache L1, router R and shared cache l2bank; The nodes communicate through routers; the class A nodes and class B nodes are intermittently distributed; the capacity of the shared cache l2bank is twice that of the shared cache in the general architecture; The number is 16, including 8 said A-type nodes and 8 said B-type nodes; said local private cache L1 includes instruction cache and data cache.