CN104866457B

CN104866457B - A kind of chip multi-core processor static framework based on shared buffer memory

Info

Publication number: CN104866457B
Application number: CN201510302580.4A
Authority: CN
Inventors: 李嵩; 褚廷斌; 黄乐天; 袁正希
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2015-06-04
Filing date: 2015-06-04
Publication date: 2018-06-15
Anticipated expiration: 2035-06-04
Also published as: CN104866457A

Abstract

The invention discloses a kind of chip multi-core processor static frameworks based on shared buffer memory, it includes n node, and n is the even number more than 0, and the node includes n/2 A classes node and n/2 B class node；A classes node includes processing core core, local private cache L1 and router R；B classes node includes processing core core, local private cache L1, router R and shared buffer memory l2bank；It is communicated between node by router；A classes node and the into intermittent distribution of B classes node；The capacity of the shared buffer memory l2bank is twice of the shared buffer memory in generic structure.The present invention provides a kind of chip multi-core processor static frameworks based on shared buffer memory, on the basis of the access for not increasing entire network-on-chip is delayed and does not increase the Congestion Level SPCC of entire network-on-chip, the hardware spending and area of afterbody cache are saved, saves the quiescent dissipation of cache.

Description

A kind of chip multi-core processor static framework based on shared buffer memory

Technical field

The present invention relates to a kind of chip multi-core processor static frameworks based on shared buffer memory.

Background technology

As shown in Figure 1, a kind of common network-on-chip multi-core processor framework, we are with common 16 core, and two level is at a high speed For caching, this common structure is made of 16 nodes, and each node includes the router R for communication, process cores The shared buffer memory l2bank of heart core and local private cache L1 and a larger area, since the structure is based on shared The mechanism of caching carries out data interaction and communication, and shared buffer memory l2bank is in the area right and wrong shared by entire network-on-chip It is often big, therefore its power consumption for bringing influences also very big, the especially ratio shared by quiescent dissipation.

It will be seen that each processor core core is connected there are one shared buffer memory l2bank from Fig. 1, due to During routine access, read-write data may be read and write shared slow where the processor core core of relative distance farther out The data stored in l2bank are deposited, so when doing Static Design, average number of hops（Core accesses the average departure of shared buffer memory l2bank From）And during data interaction, the congestion problems of whole network（It guarantees fairness）All it is factor needed to be considered, number Increasing according to the requirement of storage, the area of shared buffer memory l2bank is also increasing, thus its quiescent dissipation accounts for entire on piece The ratio of network uses this generic structure since shared buffer memory l2bank areas are excessive also in the trend increased increasingly Caused power problems also become one it is very important the problem of.

Invention content

It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of chip multi-core processing based on shared buffer memory Device static framework, on the access delay for not increasing entire network-on-chip, the basis for the Congestion Level SPCC for not increasing entire network-on-chip On, the hardware spending and area of afterbody cache are saved, saves the quiescent dissipation of cache.

The purpose of the present invention is achieved through the following technical solutions：A kind of chip multi-core processing based on shared buffer memory Device static framework, it includes n node, and n is the even number more than 0, and the node includes n/2 A classes node and n/2 B class Node；The A classes node includes processing core core, local private cache L1 and router R；The B class nodes Including processing core core, local private cache L1, router R and shared buffer memory l2bank；Lead between the node Router is crossed to communicate；The A classes node and the into intermittent distribution of B classes node；The appearance of the shared buffer memory l2bank Measure twice for the shared buffer memory in generic structure.

The node number is 16, including the B class nodes described in the A classes node described in 8 and 8.

The local private cache L1 includes instruction buffer and data buffer storage.

The beneficial effects of the invention are as follows：（1）It can ensure the average distance and generic structure of access shared buffer memory l2bank Average distance it is the same, so as to will not additionally increase entire network-on-chip access delay.

（2）The present invention is in design process of hardware, and each shared buffer memory l2bank structures and traditional identical are only deposited Storage space increases one times, and the number of shared buffer memory l2bank is reduced to original half, i.e., entire afterbody is slow at a high speed The shared buffer memory capacity deposited and generic structure it is identical, for meeting the needs of data storage；But reduce the l2bank of half, Also reduce the peripheral hardware expense of half, for example, the number of amplifier and decoder we reduce half, therefore it is hard Part design area can also be reduced, and the quiescent dissipation of cache can also reduce.

（3）The into intermittent distribution of node comprising shared buffer memory l2bank and the node not comprising shared buffer memory l2bank, During data interaction, the problem of can guaranteeing fairness, network congestion will not be brought.

Description of the drawings

Fig. 1 is common network-on-chip multi-core processor configuration diagram；

Fig. 2 is the structure diagram of the present invention.

Specific embodiment

Technical scheme of the present invention is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to It is as described below.

As shown in Fig. 2, a kind of chip multi-core processor static framework based on shared buffer memory, it includes n node, and n is Even number more than 0, the node include n/2 A classes node and n/2 B class node；The A classes node includes process cores Heart core, local private cache L1 and router R；The B classes node includes processing core core, local privately owned high speed Cache L1, router R and shared buffer memory l2bank；It is communicated between the node by router；The A class nodes With the into intermittent distribution of B classes node；The capacity of the shared buffer memory l2bank is twice of the shared buffer memory in generic structure.

The local private cache L1 includes instruction buffer and data buffer storage.

From figure 2 it can be seen that A classes node not comprising shared buffer memory l2bank and including shared buffer memory l2bankB classes The distribution situation of node, shown in the figure 16 Node distributions are arranged for four rows four, no matter from laterally or longitudinal, each two A B class node is all included between A class nodes, an A class node is all included between each two B class nodes；Here it is hereinbefore carry The intermittent distribution arrived.

Claims

1. a kind of chip multi-core processor based on shared buffer memory, which is characterized in that its static framework is：It includes n node, N is the even number more than 0, and the node includes n/2 A classes node and n/2 B class node；The A classes node includes processing Core core, local private cache L1 and router R；The B classes node includes processing core core, local privately owned height Speed caching L1, router R and shared buffer memory l2bank；It is communicated between the node by router；The A class sections Point and the into intermittent distribution of B classes node；The capacity of the shared buffer memory l2bank is two of the shared buffer memory in generic structure Times；The node number is 16, including the B class nodes described in the A classes node described in 8 and 8；The local is privately owned Cache L1 includes instruction buffer and data buffer storage.