CN104866240B - A kind of date storage method for neticdomain wall memory - Google Patents
A kind of date storage method for neticdomain wall memory Download PDFInfo
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- CN104866240B CN104866240B CN201510279359.1A CN201510279359A CN104866240B CN 104866240 B CN104866240 B CN 104866240B CN 201510279359 A CN201510279359 A CN 201510279359A CN 104866240 B CN104866240 B CN 104866240B
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Abstract
The invention discloses a kind of date storage method for neticdomain wall memory, it comprises the following steps：Step 1, the memory cell on neticdomain wall memory is divided into multiple memory paragraphs, the corresponding read/write port of each memory paragraph；Step 2, offset address identical memory cell in each memory paragraph is formed into a collection of equal value；Step 3, the read-write operation according to all data in application program, data access sequence corresponding to application program is generated；Step 4, the data acquisition system in data access sequence is divided into multiple data subsets, it is most by the number of connected reference between the data in data subset；Step 5, each data subset is corresponded into a predetermined collection of equal value, and each data in data subset is stored in the corresponding memory cell of corresponding collection of equal value by address of cache formula.Advantages of the present invention：A large amount of track moving operations are avoided, the energy consumption of neticdomain wall memory can be reduced, and can ensures the response speed of quickening system.
Description
Technical field
The invention belongs to computer memory technical field, and in particular to a kind of data storage side for neticdomain wall memory
Method.
Background technology
Neticdomain wall memory (Domain Wall Memory, DWM) is a kind of new nonvolatile memory, and it has
The performances such as VHD, low-power consumption, high-speed read-write, and stored using in embedded systems with substituting traditional DRAM, SRAM
Device.Although the power consumption of neticdomain wall memory is relatively low, performance is higher, and it has the problem of essence：Neticdomain wall stores
Device is stored data in the memory cell of track, when accessing the data on neticdomain wall memory every time, first to move track, will
The memory cell accessed is moved to write-in/read port.Multiple moving operation, moving operation may be needed by accessing a data
The expense of caused energy consumption and delay expense often beyond read-write data in itself.This energy consumption and time overhead store for neticdomain wall
The use of device in embedded systems brings very big challenge.
Because embedded system is mainly directed towards all kinds of application-specifics, if reading and writing data pattern, read-write number etc. can be considered
The internal characteristicses of Embedded Application, and the feature for combining the neticdomain wall memory of more read/write ports optimizes, then neticdomain wall
The advantage of memory is in embedded systems by the more obvious of performance.For neticdomain wall memory having in embedded systems
Imitate the research utilized to have deployed, existing technical research is mainly entered from circuit-level, storage device level, system architecture level etc.
Row optimization, and it is made that corresponding contribution in the performance of neticdomain wall memory and energy optimization etc..It is however, existing at present
Technical research does not have the reading and writing data rule for considering application-specific in embedded system, studies excellent mainly for hardware layer
Change, this can undoubtedly increase the complexity of embedded system, so as to limit neticdomain wall memory pushing away in embedded system
Extensively.
The content of the invention
For the deficiency of above-mentioned technical research method, the technical problems to be solved by the invention are that code is excellent from compiler
The aspect of change, a kind of date storage method for neticdomain wall memory is provided for system, it can reduce neticdomain wall memory and exist
Energy consumption in embedded system, and the response speed of system can be improved.
The technical problems to be solved by the invention realize that it comprises the following steps by such technical scheme：
Step 1, the memory cell on neticdomain wall memory is divided into multiple memory paragraphs, each memory paragraph is corresponding one
Read/write port；
Step 2, offset address identical memory cell in each memory paragraph is formed into a collection of equal value, connected reference storage
Moving operation is not needed in the memory cell that equivalence is concentrated；
Step 3, the read-write operation according to all data in application program, data access sequence corresponding to application program is generated
Row；
Step 4, the data acquisition system in data access sequence is divided into multiple data subsets, the data phase in data subset
It is most by the number of connected reference between mutually；
Step 5, each data subset is corresponded into a predetermined collection of equal value, and by address of cache formula data
The each data concentrated are stored in the corresponding memory cell of corresponding collection of equal value.
Because the most data of mutual connected reference number are all stored in same collection of equal value, connected reference is same
No longer cause moving operation during the data of data subset, so as to substantially reduce the number moving operation when accessing neticdomain wall memory.
Reduce the energy consumption of neticdomain wall memory and the average time of data read-write operation, shorten the time of system response.Present invention tool
There is following advantage：A large amount of track moving operations are avoided, the energy consumption of neticdomain wall memory can be reduced, and can ensures quickening system
Response speed.
Brief description of the drawings
The brief description of the drawings of the present invention is as follows：
Fig. 1 is the data storage flow chart of the neticdomain wall memory of the present invention；
Fig. 2 is the memory paragraph of one embodiment of the invention and the division schematic diagram of collection of equal value；
Fig. 3 is mapping and the storage schematic diagram of the data subset of one embodiment of the invention.
Embodiment
The invention will be further described with reference to the accompanying drawings and examples：
In neticdomain wall memory, memory cell, which has to move to special circuit, could read and write data, and this circuit claims
For " port ".
The design of present method invention is：The continuous memory cell in address on track is divided into the section of multiple equal lengths,
Referred to as " memory paragraph ", a section collection for bias internal address identical memory cell composition memory cell is selected from each memory paragraph
Close, be referred to as " equivalence collection ", the connected reference data of equal value concentrated need not move track；, can be with for specific application program
It will be grouped into a set, be referred to as " data subset " by the most data of connected reference number between each other in program.
Connected reference specifies data to refer to：The continuous accessing operation of program, successively data specified by read/write.Such as two
Secondary accessing operation connected reference data " a " and " b ", refer to first time accessing operation read/write data " a ", second of accessing operation
Read/write data " b ".
The specific steps of present method invention have：Neticdomain wall memory is divided into memory paragraph by division first；According to memory paragraph
It is determined that collection of equal value；The data access patterns of application program are analyzed, generate data access sequence；By the data in data access sequence
It is divided into multiple data subsets；Data subset is corresponded to the of equal value of neticdomain wall memory and collected；According to address mapping equation
The storage address of each data is calculated, application program uses the addresses access data when performing.
Fig. 1 is the data storage flow chart of the neticdomain wall memory of the present invention, and the flow starts from step 101, then：
In step 102, data initialization, according to the feature of neticdomain wall memory in system, the memory paragraph to be divided is specified
The initial address of quantity, each memory paragraph；Application code is analyzed, generates data access sequence；
Application code is analyzed, the method for generating data access sequence：
The method that applicant uses when the 1st, testing is as follows：
Step 1), an existing emulator processor SimpleScalar is set, it is assumed that the memory used is magnetic domain
Wall memory；
Step 2) runs application program in set simulated environment, collects the information of application program reading and writing data；
Step 3) filters out required memory access letter according to the characteristics of programmed instruction in the information being collected into from step 2)
Breath, the sequence that these memory access information in chronological sequence sequentially form are exactly required data access sequence.
2nd, it is also contemplated that using other existing instruments, such as referring to " ATOM:a system for building
customized program analysis tools”,Amitabh Srivastava；Alan Eustace,ACM
SIGPLAN Conference on Programming Language Design and Implementation(PLDI),
1994,Page(s)196-205,ISBN:0-89791-662-X(“ATOM:A kind of system that can customize program analysis tool ",
Amitabh Srivastava；Alan Eustace, the programming language special interest group programming language design of american computer association and reality
Existing meeting 1994, the 196-205 pages, International Standard Book Number ISBN:0-89791-662-X).
In step 103, according to the total quantity of neticdomain wall memory cell and the quantity of port, it is equal that memory is divided into length
Deng memory paragraph.To storage segment number and record the initial address Addr of each memory paragraph, the storage segment number of each memory cell
=int (memory unit address/storage segment length).Memory cell in each memory paragraph is only read and write by corresponding a port.
If the total quantity of memory cell can not be divided exactly by port number, the memory cell in last memory paragraph of add drop；
In step 104, it is calculated in the offset address in the memory paragraph of place according to each access unit address.Skew ground
The calculating of location has a variety of methods.For example, method one：Offset address=access unit address-single storage segment length * [storages
Element address/single storage segment length]；Method two：Offset address=memory unit address % storage segment length；
In step 105, offset address identical memory cell is incorporated into same collection of equal value.One equivalence is concentrated each
Element belongs to different memory paragraphs；
In step 106, the data access sequence from first to last generated in traversal step 102；If it is currently t-th of sequence
Data access, if the data accessed are di；
In step 107, determine whether it has been last data access, if it is not, then performing step 108, otherwise perform
Step 109；
In step 108, travel through to the t+1 data access, if the data accessed are dj；By data di and dj quilt each other
The number increase by 1 of connected reference, i.e. Fij+1.Return and perform step 106；
In step 109, according to data each other by the number of connected reference, the total data in data access sequence is drawn
It is divided into multiple data subsets.According to the feature of multiport neticdomain wall memory, the data in the same data subset of connected reference
When, it is not necessary to mobile track, it is possible to reduce energy consumption and delay.The method of generation data subset has a variety of, and main thought is number
Same data subset is assigned to according to the most data of mutual connected reference number.Such as method one, will be continuous between data
The relationship expression of access is a non-directed graph, and wherein summit represents data, and the side between summit represents the continuous visit between data
Relation is asked, the weight on side represents two connected data by the number of connected reference；It is thus that data are continuous between each other
The number of access is converted into the optimization problem of figure, can be solved using respective algorithms, for example with the figure based on Greedy strategy
Partitioning algorithm solves；
In step 110, for the data subset divided in step 109, calculate between data subset by connected reference
Number；
In step 111, the most data subset of mutual connected reference number is placed on adjacent position so that continuous
It is minimum to access moving operation required during the data in different pieces of information subset；Data subset is mapped to one by one by relative position
Valency collection；
In step 112,；The initial address Addr (s initial value is 0) of s-th of memory paragraph is obtained, obtains pth data
The offset address q of collection of equal value corresponding to collection；
In step 113, a data in pth data subset are stored in memory cell, the access unit address
=Addr+q；The data are removed from pth data subset；
In step 114, judge in pth data subset whether no data, if also data, perform step 115；If
No data, perform step 116；
In step 115, Addr is updated to the initial address of the s+1 memory paragraph, return to step 113；
In step 116, determine whether to have stored all data subsets, if also data subset does not store, hold
Row step 117, otherwise perform step 118；
In step 117, next data subset, the i.e. data subset of pth+1, return to step 112 are selected；
In step 118, all data have been stored, have terminated whole flow process.
Embodiment
As shown in Fig. 2 there are 16 memory cell and 4 ports on neticdomain wall memory track.16 all storages are single
Member is divided into 4 memory paragraphs, and each memory paragraph respectively includes 4 memory cell, i.e. length is 4.Memory cell 0~3 belongs to
0th memory paragraph, their data can and can only be read and write by port 0.
The affiliated collection of equal value of memory cell is can be determined that by offset address calculation formula.For example, use above-mentioned steps
Method one in 104 can calculate, and address is offset address=5-4* [5/4]=5-4=1 of 5 memory cell.So storage
Unit 5 belongs to collection 1 of equal value；The skew for the memory cell that address is 14 can be calculated using the method two in above-mentioned steps 104
Location=14%4=2, i.e. memory cell 14 belong to collection 2 of equal value.Equally, the memory paragraph of memory cell can be determined using step 103
Number.
Fig. 3 is mapping and storage schematic diagram, 4 data subsets of data subset, is mapped to a collection of equal value one by one respectively.
For example, data subset 2 is mapped to collection 3 of equal value, so the data in data subset 2 are all placed on offset address in each memory paragraph
For 3 memory cell.Such as data m is put first, obtain the initial address of memory paragraph 0, i.e. Addr=0；Data m is just stored in ground
Location is Addr+3=3 memory cell.
Claims (4)
1. a kind of date storage method for neticdomain wall memory, it is characterized in that：Comprise the following steps：
Step 1, the memory cell on neticdomain wall memory is divided into multiple memory paragraphs, the corresponding read/write of each memory paragraph
Port；
Step 2, offset address identical memory cell in each memory paragraph is formed into a collection of equal value, connected reference is stored in
The memory cell that valency is concentrated does not need moving operation；
Step 3, the read-write operation according to all data in application program, data access sequence corresponding to application program is generated；
Step 4, it is a non-directed graph by the relationship expression of connected reference between data, wherein pushing up according to the access sequence of data
Put and represent data, the side between summit represents the connected reference relation between data, and the weight on side represents two connected data
By the number of connected reference；Data are converted into the optimization problem of figure by the number of connected reference between each other, data access
Data acquisition system in sequence is divided into multiple data subsets so that the data in data subset are between each other by time of connected reference
Number is most；
Step 5, each data subset is corresponded into a predetermined collection of equal value, and by address of cache formula in data subset
Each data be stored in the corresponding memory cell of corresponding of equal value collection.
2. the date storage method according to claim 1 for neticdomain wall memory, it is characterized in that：In step 1, give
Storage segment number simultaneously records the initial address Addr of each memory paragraph.
3. the date storage method according to claim 1 for neticdomain wall memory, it is characterized in that, in step 2, deposit
Offset address of the storage unit in memory paragraph be：Offset address=access unit address-[storage is single by single storage segment length *
First address/single storage segment length], or offset address=memory unit address % storage segment length.
4. the date storage method according to claim 1 for neticdomain wall memory, it is characterized in that, in steps of 5, institute
The address of cache formula stated：Deposit initial address Addr+ data of memory unit address=memory paragraph of data subset element
The offset address q of collection of equal value corresponding to collection.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103650058A (en) * | 2010-12-30 | 2014-03-19 | 意法半导体国际有限公司 | Method and system for controlling loss of reliability of non-volatile memory |
| CN104516912A (en) * | 2013-09-29 | 2015-04-15 | 中国移动通信集团黑龙江有限公司 | Dynamic data storage method and device |
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| US8279667B2 (en) * | 2009-05-08 | 2012-10-02 | Samsung Electronics Co., Ltd. | Integrated circuit memory systems and program methods thereof including a magnetic track memory array using magnetic domain wall movement |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103650058A (en) * | 2010-12-30 | 2014-03-19 | 意法半导体国际有限公司 | Method and system for controlling loss of reliability of non-volatile memory |
| CN104516912A (en) * | 2013-09-29 | 2015-04-15 | 中国移动通信集团黑龙江有限公司 | Dynamic data storage method and device |
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