CN104854556B - 建立分支目标指令高速缓冲存储器条目的方法和系统 - Google Patents

建立分支目标指令高速缓冲存储器条目的方法和系统 Download PDF

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Publication number
CN104854556B
CN104854556B CN201380061574.3A CN201380061574A CN104854556B CN 104854556 B CN104854556 B CN 104854556B CN 201380061574 A CN201380061574 A CN 201380061574A CN 104854556 B CN104854556 B CN 104854556B
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China
Prior art keywords
instruction
subroutine
btic
entries
address
Prior art date
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CN201380061574.3A
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English (en)
Chinese (zh)
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CN104854556A (zh
Inventor
詹姆斯·诺里斯·迪芬德尔费尔
迈克尔·威廉·莫罗
迈克尔·斯科特·麦克勒瓦伊内
达朗·尤金·施特雷特
维马尔·K·雷迪
布莱恩·迈克尔·斯坦普尔
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
CN201380061574.3A 2012-11-28 2013-11-27 建立分支目标指令高速缓冲存储器条目的方法和系统 Active CN104854556B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261730717P 2012-11-28 2012-11-28
US61/730,717 2012-11-28
US13/792,335 US9317293B2 (en) 2012-11-28 2013-03-11 Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media
US13/792,335 2013-03-11
PCT/US2013/072372 WO2014085683A1 (en) 2012-11-28 2013-11-27 Establishing a branch target instruction cache (btic) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media

Publications (2)

Publication Number Publication Date
CN104854556A CN104854556A (zh) 2015-08-19
CN104854556B true CN104854556B (zh) 2017-11-10

Family

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Family Applications (1)

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CN201380061574.3A Active CN104854556B (zh) 2012-11-28 2013-11-27 建立分支目标指令高速缓冲存储器条目的方法和系统

Country Status (5)

Country Link
US (1) US9317293B2 (enExample)
EP (1) EP2926240A1 (enExample)
JP (1) JP6271572B2 (enExample)
CN (1) CN104854556B (enExample)
WO (1) WO2014085683A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170083333A1 (en) * 2015-09-21 2017-03-23 Qualcomm Incorporated Branch target instruction cache (btic) to store a conditional branch instruction
GB2542831B (en) * 2015-09-30 2018-05-30 Imagination Tech Ltd Fetch unit for predicting target for subroutine return instructions
US11099849B2 (en) * 2016-09-01 2021-08-24 Oracle International Corporation Method for reducing fetch cycles for return-type instructions
US11481221B2 (en) * 2018-05-02 2022-10-25 Micron Technology, Inc. Separate branch target buffers for different levels of calls
US11880231B2 (en) * 2020-12-14 2024-01-23 Microsoft Technology Licensing, Llc Accurate timestamp or derived counter value generation on a complex CPU

Citations (4)

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Publication number Priority date Publication date Assignee Title
US5604877A (en) * 1994-01-04 1997-02-18 Intel Corporation Method and apparatus for resolving return from subroutine instructions in a computer processor
US5850543A (en) * 1996-10-30 1998-12-15 Texas Instruments Incorporated Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return
CN1549113A (zh) * 2003-01-14 2004-11-24 智权第一公司 将加载管线式微处理器指令队列的指令删除的设备及方法
CN102483696A (zh) * 2009-08-19 2012-05-30 高通股份有限公司 用以预测有条件非分支指令的不执行的方法和设备

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US5179673A (en) * 1989-12-18 1993-01-12 Digital Equipment Corporation Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline
US5230068A (en) 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
US5276882A (en) * 1990-07-27 1994-01-04 International Business Machines Corp. Subroutine return through branch history table
US5623614A (en) 1993-09-17 1997-04-22 Advanced Micro Devices, Inc. Branch prediction cache with multiple entries for returns having multiple callers
US5561782A (en) 1994-06-30 1996-10-01 Intel Corporation Pipelined cache system having low effective latency for nonsequential accesses
US6279106B1 (en) 1998-09-21 2001-08-21 Advanced Micro Devices, Inc. Method for reducing branch target storage by calculating direct branch targets on the fly
US6170054B1 (en) * 1998-11-16 2001-01-02 Intel Corporation Method and apparatus for predicting target addresses for return from subroutine instructions utilizing a return address cache
US6289444B1 (en) * 1999-06-02 2001-09-11 International Business Machines Corporation Method and apparatus for subroutine call-return prediction
US6823444B1 (en) 2001-07-03 2004-11-23 Ip-First, Llc Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap
JP4247132B2 (ja) 2004-01-29 2009-04-02 株式会社ルネサステクノロジ 情報処理装置
JP4354990B2 (ja) 2005-04-08 2009-10-28 パナソニック株式会社 プロセッサ
US7447883B2 (en) 2006-08-10 2008-11-04 Arm Limited Allocation of branch target cache resources in dependence upon program instructions within an instruction queue
JP2008299795A (ja) 2007-06-04 2008-12-11 Nec Electronics Corp 分岐予測制御装置及びその方法
US7882338B2 (en) 2008-02-20 2011-02-01 International Business Machines Corporation Method, system and computer program product for an implicit predicted return from a predicted subroutine

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604877A (en) * 1994-01-04 1997-02-18 Intel Corporation Method and apparatus for resolving return from subroutine instructions in a computer processor
US5850543A (en) * 1996-10-30 1998-12-15 Texas Instruments Incorporated Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return
CN1549113A (zh) * 2003-01-14 2004-11-24 智权第一公司 将加载管线式微处理器指令队列的指令删除的设备及方法
CN102483696A (zh) * 2009-08-19 2012-05-30 高通股份有限公司 用以预测有条件非分支指令的不执行的方法和设备

Also Published As

Publication number Publication date
CN104854556A (zh) 2015-08-19
JP2015535634A (ja) 2015-12-14
US9317293B2 (en) 2016-04-19
EP2926240A1 (en) 2015-10-07
US20140149726A1 (en) 2014-05-29
JP6271572B2 (ja) 2018-01-31
WO2014085683A1 (en) 2014-06-05

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