CN104853213B - A kind of method and its system for improving Video Decoder cache treatment effeciencies - Google Patents
A kind of method and its system for improving Video Decoder cache treatment effeciencies Download PDFInfo
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- CN104853213B CN104853213B CN201510223715.8A CN201510223715A CN104853213B CN 104853213 B CN104853213 B CN 104853213B CN 201510223715 A CN201510223715 A CN 201510223715A CN 104853213 B CN104853213 B CN 104853213B
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Abstract
The present invention provides a kind of method for improving Video Decoder cache treatment effeciencies, increase by an address compression device in the input terminal of Video Decoder cache, the address compression device is to the address of two or more reference blocks that continuously inputs into the expansion of row address, on the basis of expansion, folding operation is carried out to address identical in continuous reference block, and marks the position for folding the address after merging；Increase one-over-one address decompression machine in the output terminal of Video Decoder cache, which is transmitted through the mark come, and utilizes the mark, when the data of corresponding reference block are come in, reduces the data on the address of folding.The present invention also provides a kind of system for improving Video Decoder cache treatment effeciencies, the present invention promotes Video Decoder cache data-handling capacities, the service efficiency of Video Decoder cache is improved, so as to promote the access performance of Video Decoder.
Description
Technical field
The present invention relates to field of communication technology more particularly to a kind of methods for improving Video Decoder cache treatment effeciencies
And its system.
Background technology
Existing Video Decoder cache needs to expend certain cycle (Xun Huan) when handling each address command
Number, therefore when Video Decoder cache front ends have the substantial amounts of address command to input, can cause that Video Decoder cache's is busy,
Cause the reduction of Video Decoder cache treatment effeciencies.
Shown in Figure 1, the prior art is in the front and back end processing module of Video Decoder cache, the reference to input
Block address is that the address command of Video Decoder cache is sent to by rule ordering generation, i.e. reference block is input to Cache addresses
The address of corresponding reference block is produced after maker, Video Decoder cache obtains data data from DDR, incite somebody to action according to address
Data are put on the address of corresponding reference block.In this way, Video Decoder cache is in the address command that processing sequence is come in
Pressure is bigger, and bottleneck is just appeared in the processing capacity of Video Decoder cache.
A kind of " method and be that the dynamic caching module of the data deduplication of optimization selects is disclosed in the prior art
System ", is shown in Publication No.：104050098A, publication date are：The Chinese patent of 2014-09-17, the embodiment of the invention provide use
In method, system and computer program product that the dynamic caching module of the data deduplication for optimization selects.At this
In the embodiment of invention, provide to be directed to the method that the dynamic caching module of the data deduplication of optimization selects.The party
Method includes receiving the request of retrieval data and the request of classifying.This method further include from it is each have it is different configuration of it is multiple not
Identification specific cache module associated with the classification asked in same cache module.Finally, this method includes
To data deduplication in the cache module of identification.But the technical solution of the invention with the present invention and differ, this specially
Profit application is compressed operation for the address repeated, is not for address using the characteristic of caching and video Decoded Reference block
The data carried are compressed operation, by transferring the address information of compression, then the correctly data in reduction corresponding address
Information.The technical issues of disclosed patent solves simultaneously differs, and is that the data being directed to are operated, and present patent application not pin
Data are operated, and the address where data is operated.
The content of the invention
One of the technical problem to be solved in the present invention is to provide a kind of raising Video Decoder cache treatment effeciencies
Method promotes Video Decoder cache data-handling capacities, improves the service efficiency of Video Decoder cache, is regarded so as to be promoted
The access performance of frequency decoder.
What one of problem of the present invention was realized in：A kind of method for improving Video Decoder cache treatment effeciencies,
Video Decoder cache input terminal increase an address compression device, the address compression device to continuously input two
The address of a or multiple reference blocks into row address expansion, on the basis of expansion, to ground identical in continuous reference block
Location carries out folding operation, and marks the position for folding the address after merging；
Increase one-over-one address decompression machine in the output terminal of Video Decoder cache, the address decompression machine processing address compression device
The mark come is transmitted through, and utilizes the mark, when the data of corresponding reference block are come in, reduces the number on the address of folding
According to.
Further, the address judgment mode of two or more reference blocks continuously inputted is：The ginseng of input terminal input
The order of block is examined, generates the address of reference block after Cache address generators with reference to block command, the order of the reference block designates
The address of the reference block, width, elevation information, the address of continuous reference block are then the lives of two reference blocks continuously entered
Order, which is one group.
Further, it is described to be specially to address progress folding operation identical in continuous reference block：Based on video solution
The characteristic of code device cache, the width of a Video Decoder cache line is 256bit, i.e. Video Decoder cache storages,
The data length read once is 256bit, and it is long that the address that two continuous reference blocks have part is located at same 256bit addresses
In degree, the address of overlapping is exactly to be present in the address in same 256bit in two reference blocks, eliminates the latter reference block
It neutralizes previous reference block and identical address folding is carried out with the address in a 256bit.
Further, the method is further included：It is pressed in a manner that 256bit aligns all addresses of two reference blocks
Order is unfolded, and obtains the address arrangement after two expansion, and it is to overlap to have part in the two address arrangements, right in order
Label, this label are the position of the address of reference block successively for the 256bit addresses progress of two expansion.
Further, the position that the mark folds the address after merging is specially：Specific mark is represented using label
The mode of A_ labels B, n-th of address of the first reference block that label A representatives merge refer to position in the block first,
, it is necessary to which the data address of copy is in the position of the second reference block merged after label B representatives fold.
Further, the data on the address of the reduction folding are specially：Two reference blocks continuously entered, then two
The overlapping of the address of reference block at most only occurs once, and address compression device is compressed according to the order of label, then
The command queue that data are transmitted to address decompression machine must be in a manner that a label A corresponds to a label B, be decompressed in address
Device accordingly inserts identical data in the corresponding buffer positions of label B when inserting the buffer positions of label A, complete
Into reduction process.
The second technical problem to be solved by the present invention is to provide a kind of raising Video Decoder cache treatment effeciencies
System promotes Video Decoder cache data-handling capacities, improves the service efficiency of Video Decoder cache, is regarded so as to be promoted
The access performance of frequency decoder.
What the two of problem of the present invention were realized in：A kind of system for improving Video Decoder cache treatment effeciencies, it is described
System includes compression module and decompression module；
The compression module, for increasing an address compression device, the address compression in the input terminal of Video Decoder cache
Device to the address of two or more reference blocks that continuously inputs into the expansion of row address, on the basis of expansion, to continuous
Identical address carries out folding operation in reference block, and marks the position for folding the address after merging；
The decompression module, for increasing one-over-one address decompression machine, address decompression in the output terminal of Video Decoder cache
The mark come is transmitted through in device processing input terminal, and utilizes the mark, when the data of corresponding reference block are come in, reduction folds
Address on data.
Further, the address judgment mode of two or more reference blocks continuously inputted is：The ginseng of input terminal input
The order of block is examined, generates the address of reference block after Cache address generators with reference to block command, the order of the reference block designates
The address of the reference block, width, elevation information, the address of continuous reference block are then the lives of two reference blocks continuously entered
Order, which is one group.
Further, it is described to be specially to address progress folding operation identical in continuous reference block：Based on video solution
The characteristic of code device cache, the width of a Video Decoder cache line is 256bit, i.e. Video Decoder cache storages,
The data length read once is 256bit, and it is long that the address that two continuous reference blocks have part is located at same 256bit addresses
In degree, the address of overlapping is exactly to be present in the address in same 256bit in two reference blocks, eliminates the latter reference block
It neutralizes previous reference block and identical address progress folding is carried out with the address in a 256bit.
Further, the system further comprises label module：The label module：For owning to two reference blocks
Address by 256bit align in the way of be unfolded in order, obtain two expansion after address arrangement, the two addresses row
It is to overlap to have part in row, and to the two 256bit addresses being unfolded progress, label, this label are reference successively in order
The position of the address of block.
Further, the position that the mark folds the address after merging is specially：Specific mark is represented using label
The mode of A_ labels B, n-th of address of the first reference block that label A representatives merge refer to position in the block first,
, it is necessary to which the data address of copy is in the position of the second reference block merged after label B representatives fold.
Further, the data on the address of the reduction folding are specially：Two reference blocks continuously entered, then two
The overlapping of the address of reference block at most only occurs once, and address compression device is compressed according to the order of label, then
The command queue that data are transmitted to address decompression machine must be in a manner that a label A corresponds to a label B, be decompressed in address
Device accordingly inserts identical data in the corresponding buffer positions of label B when inserting the buffer positions of label A, complete
Into reduction process.
The invention has the advantages that：The present invention is used respectively increases by one on Video Decoder cache front end processing blocks
Address compression device to the two or more reference blocks continuously inputted, first carries out the expansion of reference block address, on the basis of expansion
On, folding operation is carried out to the address of overlapping, in the output terminal of cache, increases one-over-one address solution contracting device, for handling front-end processing
The mark come is transmitted through in module, and utilizes the mark, when corresponding data are come in, reduces the data on the address of folding；
Video Decoder cache data-handling capacities are promoted, the service efficiency of Video Decoder cache are improved, so as to promote video solution
The access performance of code device.
Description of the drawings
Fig. 1 is the structure diagram of existing Video Decoder cache.
Fig. 2 is the structure diagram of the Video Decoder cache of the present invention.
Fig. 3 is the method for the present invention flow diagram.
Fig. 4 is the structure diagram of present system.
Specific embodiment
It refers to shown in Fig. 2 and Fig. 3, a kind of method of raising Video Decoder cache treatment effeciencies of the invention,
Video Decoder cache input terminal increase an address compression device, the address compression device to continuously input two
The address of a or multiple reference blocks into row address expansion, on the basis of expansion, to ground identical in continuous reference block
Location carries out folding operation, and marks the position for folding the address after merging；
All addresses of two reference blocks are unfolded in order in a manner that 256bit aligns, after obtaining two expansion
Address arrangement, it is to overlap to have part in the two address arrangements, and the 256bit addresses of two expansion are carried out successively in order
Label, this label are the position of the address of reference block.
Increase one-over-one address decompression machine in the output terminal of Video Decoder cache, the address decompression machine processing address compression device
The mark come is transmitted through, and utilizes the mark, when the data of corresponding reference block are come in, reduces the number on the address of folding
According to.The data of the corresponding reference block come in be：Video Decoder cache Notify Address decompression machines, have corresponding
The data needs of 256bit store, and the data transfer sequence of Video Decoder cache is transmitted in strict accordance with address compression device
What the designated command order of Video Decoder cache carried out data transmission, therefore, the data of reference block are all corresponding references
Block.
Wherein, the address judgment mode of two or more reference blocks continuously inputted is：The reference block of input terminal input
Order, the address of reference block is generated after Cache address generators with reference to block command, the order of the reference block designates the ginseng
The address of block is examined, width, elevation information, the address of continuous reference block is then the order of two reference blocks continuously entered, should
The order for continuously entering two reference blocks is one group.
It is described to be specially to address progress folding operation identical in continuous reference block：Based on Video Decoder cache
Characteristic, the width of a Video Decoder cache line is 256bit, i.e. Video Decoder cache storage, read once
Data length be 256bit, the address that two continuous reference blocks have part is located in same 256bit address sizes, weight
Folded address is exactly to be present in the address in same 256bit in two reference blocks, is eliminated in the latter reference block and previous
A reference block is to carry out identical address to carry out folding with the address in a 256bit.
In the present invention, specific mark is represented using label A_ labels B by the way of, and label A represents the merged
N-th of address of one reference block refers to position in the block first, it is necessary to the data address of copy after label B representatives fold
In the position of the second reference block merged.(such as the 5th of the 2nd address of first reference block and second reference block
A address overlap, then the address that the needs after folding copy is the 5th address, then labeled as A2_B5, such as first reference block
The 4th address and second reference block the 3rd address overlap, then the address that copies of needs after folding is the 4th address,
Then it is labeled as A4_B3.
In addition, in the present invention, the data on address that the reduction folds are specially：Two reference blocks continuously entered,
Then the overlapping of the address of two reference blocks at most only occurs once, and address compression device is compressed according to the order of label
, then the command queue that data are transmitted to address decompression machine must be in a manner that label A corresponds to a label B,
It is buffer corresponding that identical data are inserted label B by address decompression machine when inserting the buffer positions of label A, accordingly
In putting, reduction process is completed.
It refers to shown in Fig. 2 and Fig. 4, a kind of system for improving Video Decoder cache treatment effeciencies, the system comprises
Compression module, label module and decompression module；
The compression module, for increasing an address compression device, the address compression in the input terminal of Video Decoder cache
Device to the address of two or more reference blocks that continuously inputs into the expansion of row address, on the basis of expansion, to continuous
Identical address carries out folding operation in reference block, and marks the position for folding the address after merging；
The label module：For being opened up in order in a manner that 256bit aligns to all addresses of two reference blocks
It opens, obtains the address arrangement after two expansion, it is to overlap to have part in the two address arrangements, and two are unfolded in order
Label, this label are the position of the address of reference block to the progress of 256bit addresses successively.
The decompression module, for increasing one-over-one address decompression machine, address decompression in the output terminal of Video Decoder cache
The mark come is transmitted through in device processing input terminal, and utilizes the mark, when the data of corresponding reference block are come in, reduction folds
Address on data.The data of the corresponding reference block come in be：Video Decoder cache Notify Address decompression machines,
The data needs for having corresponding 256bit store, and the data transfer sequence of Video Decoder cache is pressed in strict accordance with address
What the designated command order that contracting device is transmitted to Video Decoder cache carried out data transmission, therefore, the data of reference block are all corresponding
Reference block.
Wherein, the address judgment mode of two or more reference blocks continuously inputted is：The reference block of input terminal input
Order, the address of reference block is generated after Cache address generators with reference to block command, the order of the reference block designates the ginseng
The address of block is examined, width, elevation information, the address of continuous reference block is then the order of two reference blocks continuously entered, should
The order for continuously entering two reference blocks is one group.
It is described to be specially to address progress folding operation identical in continuous reference block：Based on Video Decoder cache
Characteristic, the width of a Video Decoder cache line is 256bit, i.e. Video Decoder cache storage, read once
Data length be 256bit, the address that two continuous reference blocks have part is located in same 256bit address sizes, weight
Folded address is exactly to be present in the address in same 256bit in two reference blocks, is eliminated in the latter reference block and previous
A reference block is to carry out identical address to carry out folding with the address in a 256bit.
In the present invention, the position that the mark folds the address after merging is specially：Specific mark is represented using mark
The mode of number A_ labels B, n-th of address of the first reference block that label A representatives merge refer to position in the block first
It puts, it is necessary to which the data address of copy is in the position of the second reference block merged after label B representatives fold.
It is described reduction fold address on data be specially：Two reference blocks continuously entered, then two reference blocks
The overlapping of address at most only occurs once, and address compression device is compressed according to the order of label, then data are transmitted to
The command queue of address decompression machine must be in a manner that a label A corresponds to a label B, and in address, decompression machine is being inserted
During the buffer positions of label A, identical data are inserted in the corresponding buffer positions of label B accordingly, completion reduced
Journey.
In short, the present invention is used respectively increases by an address compression device on Video Decoder cache front end processing blocks, to even
Two or more reference blocks of continuous input, first carry out the expansion of reference block address, on the basis of expansion, to the address of overlapping into
Row folding operation in the output terminal of cache, increases one-over-one address solution contracting device, for handling the mark for being transmitted through coming in front end processing block
Note, and the mark is utilized, when corresponding data are come in, reduce the data on the address of folding；Promote Video Decoder
Cache data-handling capacities improve the service efficiency of Video Decoder cache, so as to promote the access performance of Video Decoder.
The foregoing is merely presently preferred embodiments of the present invention, all equivalent changes done according to scope of the present invention patent with
Modification should all belong to the covering scope of the present invention.
Claims (10)
- A kind of 1. method for improving Video Decoder cache treatment effeciencies, it is characterised in that：Increase by an address compression device in the input terminal of Video Decoder cache, the address compression device to continuously input two or The address of the multiple reference blocks of person into row address expansion, on the basis of expansion, to address identical in continuous reference block into Row folding operation, and mark the position for folding the address after merging；It is described that address identical in continuous reference block is rolled over Folded operation is specially：Based on the characteristic of Video Decoder cache, the width of a Video Decoder cache line is 256bit, i.e. Video Decoder cache storage, the data length read once are 256bit, and two continuous reference blocks have portion Point address be located in same 256bit address sizes, the address of overlapping be exactly be present in two reference blocks it is same Address in 256bit, eliminates in the latter reference block and previous reference block is carried out with the address in a 256bit Identical address folding；Increase one-over-one address decompression machine in the output terminal of Video Decoder cache, which is transmitted through The mark come, and the mark is utilized, when the data of corresponding reference block are come in, reduce the data on the address of folding.
- 2. a kind of method for improving Video Decoder cache treatment effeciencies according to claim 1, it is characterised in that：Even The address judgment mode of two or more reference blocks of continuous input is：The order of the reference block of input terminal input, reference block life The address that reference block is generated after Cache address generators is made, the order of the reference block designates the address of the reference block, wide Degree, elevation information, the address of continuous reference block is then the order of two reference blocks continuously entered, this continuously enters two ginsengs The order for examining block is one group.
- 3. a kind of method for improving Video Decoder cache treatment effeciencies according to claim 1, it is characterised in that：Institute The method of stating further comprises：All addresses of two reference blocks are unfolded in order in a manner that 256bit aligns, and obtain two Address arrangement after a expansion, it is to overlap to have part in the two address arrangements, in order to the 256bit of two expansion Label, this label are the position of the address of reference block successively for location progress.
- 4. a kind of method for improving Video Decoder cache treatment effeciencies according to claim 3, it is characterised in that：Institute The position for stating the address after mark folding merges is specially：Specific mark expression is by the way of label A_ labels B, label A Represent n-th of address of the first reference block merged refers to position in the block first, after label B represents folding, needs The address of data is copied in the position of the second reference block merged.
- 5. a kind of method for improving Video Decoder cache treatment effeciencies according to claim 4, it is characterised in that：Institute State reduction fold address on data be specially：Two reference blocks continuously entered, the then overlapping of the address of two reference blocks At most only occur once, and address compression device is compressed according to the order of label, then data are transmitted to address decompression machine Command queue must be in a manner that label A corresponds to a label B, in address, decompression machine is inserting label A's During buffer positions, identical data are inserted in the corresponding buffer positions of label B accordingly, complete reduction process.
- 6. a kind of system for improving Video Decoder cache treatment effeciencies, it is characterised in that：The system comprises compression module and Decompression module；The compression module, for increasing an address compression device, the address compression device pair in the input terminal of Video Decoder cache The address of two or more reference blocks continuously inputted into row address expansion, on the basis of expansion, to continuously referring to Identical address carries out folding operation in block, and marks the position for folding the address after merging；It is described in continuous reference block Identical address carries out folding operation：Based on the characteristic of Video Decoder cache, a Video Decoder cache The width of line is 256bit, i.e. Video Decoder cache storages, the data length read once are 256bit, and two continuous The reference block address that has part be located in same 256bit address sizes, the address of overlapping is exactly to exist in two reference blocks Address in same 256bit, eliminates in the latter reference block and previous reference block is the same as the ground in a 256bit Location is to carry out identical address to carry out folding；The decompression module, at the output terminal of Video Decoder cache increasing one-over-one address decompression machine, the address decompression machine The mark come is transmitted through in reason input terminal, and utilizes the mark, when the data of corresponding reference block are come in, reduces the ground of folding Data on location.
- 7. a kind of system for improving Video Decoder cache treatment effeciencies according to claim 6, it is characterised in that：Even The address judgment mode of two or more reference blocks of continuous input is：The order of the reference block of input terminal input, reference block life The address that reference block is generated after Cache address generators is made, the order of the reference block designates the address of the reference block, wide Degree, elevation information, the address of continuous reference block is then the order of two reference blocks continuously entered, this continuously enters two ginsengs The order for examining block is one group.
- 8. a kind of system for improving Video Decoder cache treatment effeciencies according to claim 6, it is characterised in that：Institute The system of stating further comprises label module：The label module：For aliging to all addresses of two reference blocks by 256bit Mode be unfolded in order, obtain the address arrangement after two expansion, it is to overlap to have part in the two address arrangements, To the two 256bit addresses being unfolded progress, label, this label are the position of the address of reference block successively in order.
- 9. a kind of system for improving Video Decoder cache treatment effeciencies according to claim 8, it is characterised in that：Institute The position for stating the address after mark folding merges is specially：Specific mark expression is by the way of label A_ labels B, label A Represent n-th of address of the first reference block merged refers to position in the block first, after label B represents folding, needs The data address to be copied is in the position of the second reference block merged.
- 10. a kind of system for improving Video Decoder cache treatment effeciencies according to claim 9, it is characterised in that：Institute State reduction fold address on data be specially：Two reference blocks continuously entered, the then overlapping of the address of two reference blocks At most only occur once, and address compression device is compressed according to the order of label, then data are transmitted to address decompression machine Command queue must be in a manner that label A corresponds to a label B, in address, decompression machine is inserting label A's During buffer positions, identical data are inserted in the corresponding buffer positions of label B accordingly, complete reduction process.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622628A (en) * | 2004-12-21 | 2005-06-01 | 北京中星微电子有限公司 | A writing method for macro block data of reference frame in video encoding-decoding process |
| CN101399978A (en) * | 2007-09-28 | 2009-04-01 | 上海杰得微电子有限公司 | Reference frame data reading method in hardware decoder and apparatus thereof |
| CN103034455A (en) * | 2012-12-13 | 2013-04-10 | 东南大学 | Method and system for managing data information buffer based on pre-decoding and analyzing |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622628A (en) * | 2004-12-21 | 2005-06-01 | 北京中星微电子有限公司 | A writing method for macro block data of reference frame in video encoding-decoding process |
| CN101399978A (en) * | 2007-09-28 | 2009-04-01 | 上海杰得微电子有限公司 | Reference frame data reading method in hardware decoder and apparatus thereof |
| CN103034455A (en) * | 2012-12-13 | 2013-04-10 | 东南大学 | Method and system for managing data information buffer based on pre-decoding and analyzing |
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| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |