CN104853213A - Method and system for improving cache processing efficiency of video decoder - Google Patents
Method and system for improving cache processing efficiency of video decoder Download PDFInfo
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Abstract
The present invention provides a method for improving the cache processing efficiency of a video decoder, which comprises the steps of adding an address compressor at the input end of the cache of the video decoder, unfolding the addresses of two or more continuously input reference blocks by the address compressor, folding the same address of the continuous reference blocks after the above unfolding process, marking the positions of folded and combined addresses, adding an address decompressor at the output end of the cache of the video decoder, processing the marks transmitted from the address compressor by the address decompressor, and based on the above marks, restoring the data of the above folded addresses when the data of corresponding reference blocks are input. The invention also provides a system for improving the cache processing efficiency of the video decoder. The data processing capability of the cache of the video decoder is improved, and the application efficiency of the cache of the video decoder is increased. Therefore, the access performance of the video decoder is improved.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of method and the system thereof that improve Video Decoder cache treatment effeciency.
Background technology
Existing Video Decoder cache needs when processing each address command to expend certain cycle (circulation) number, therefore when Video Decoder cache front end has a large amount of address commands to input, can cause that Video Decoder cache's is busy, cause the reduction of Video Decoder cache treatment effeciency.
Shown in Figure 1, prior art is in the front and back end processing module of Video Decoder cache, the address command sending to Video Decoder cache is just regularly sequentially generated to the reference block address of input, namely reference block produces the address of corresponding reference block after being input to Cache address generator, Video Decoder cache is according to address, from DDR, obtain data data, data are put on the address of corresponding reference block.Like this, Video Decoder cache pressure ratio when the address command that processing sequence is come in is comparatively large, and bottleneck just appears in the disposal ability of Video Decoder cache.
One " method and system of the dynamic caching model choice of the data deduplication of optimization " is disclosed in prior art, see that publication number is: 104050098A, publication date is: the Chinese patent of 2014-09-17, and this inventive embodiment is provided for for the method for dynamic caching model choice of the data deduplication optimized, system and computer program.In this inventive embodiment, be provided for the method for the dynamic caching model choice for the data deduplication optimized.The method comprises the request and this request of classifying that receive retrieve data.The method also comprises the specific cache module be associated from each classification with identification and request the multiple different cache module of different configuration.Finally, the method is included in the cache module of identification data deduplication.But the technical scheme of this invention and the present invention are not identical, present patent application utilizes the characteristic of buffer memory and video decode reference block, squeeze operation is carried out for the address of repeating, not that the data carried for address carry out squeeze operation, by transmitting the address information of compression, then the data message in correct reduction corresponding address.The technical problem that this patent disclosed solves is not identical, be for data operate, and present patent application does not operate for data, and operates the address at data place.
Summary of the invention
One of the technical problem to be solved in the present invention, be to provide a kind of method improving Video Decoder cache treatment effeciency, promote Video Decoder cache data-handling capacity, improve the service efficiency of Video Decoder cache, thus promote the peek performance of Video Decoder.
One of problem of the present invention is achieved in that a kind of method improving Video Decoder cache treatment effeciency,
Increase by an address compression device at the input of Video Decoder cache, the expansion of address is carried out in the address of this address compression device to two or more reference blocks of input continuously, on the basis of launching, folding operation is carried out to address identical in continuous print reference block, and mark folds the position of the address after merging;
Increase one-over-one address decompression machine at the output of Video Decoder cache, this address decompression machine process address compression device passes the mark of coming, and utilizes this mark, when the data of corresponding reference block are come in, and the data on the address that reduction is folding.
Further, the address judgment mode of two or more reference blocks of continuous input is: the order of the reference block of input input, the address of reference block order generating reference block after Cache address generator, the order of this reference block designates the address of this reference block, width, elevation information, the address of continuous print reference block is then the order of two reference blocks entered continuously, and this order entering two reference blocks is continuously one group.
Further, describedly folding operation is carried out to address identical in continuous print reference block be specially: based on the characteristic of Video Decoder cache, the width of a Video Decoder cache line is 256bit, namely Video Decoder cache stores, the data length read once is 256bit, two continuous print reference blocks have the address of part to be arranged in same 256bit address size, overlapping address is exactly the address be present in two reference blocks in same 256bit, eliminate the address coexisted in a 256bit with previous reference block in a rear reference block and namely carry out identical address folding.
Further, described method comprises further: the mode alignd by 256bit in all address of two reference blocks is launched in order, obtain the address arrangement after two expansion, part is had to be overlap in these two address arrangement, carry out label successively to the 256bit address that two are launched in order, namely this label is the position of the address of reference block.
Further, the position of the address after described mark folds merging is specially: concrete mark represents the mode adopting label A_ label B, the position in the first reference block of the n-th address of the first reference block merged is carried out in label A representative, after label B represents and folds, need the data address of copy in the position of the second reference block carrying out merging.
Further, data on the address that described reduction folds are specially: two reference blocks entered continuously, then the overlap of the address of two reference blocks at most only occurs once, and address compression device carries out compressing according to the order of label, so data pass to the command queue of address decompression machine must be mode according to the corresponding label B of label A, at address decompression machine when inserting the buffer position of label A, accordingly identical data are inserted in buffer position corresponding to label B, complete reduction process.
The technical problem to be solved in the present invention two, be to provide a kind of system improving Video Decoder cache treatment effeciency, promote Video Decoder cache data-handling capacity, improve the service efficiency of Video Decoder cache, thus promote the peek performance of Video Decoder.
Two of problem of the present invention is achieved in that a kind of system improving Video Decoder cache treatment effeciency, and described system comprises compression module and decompression module;
Described compression module, for increasing by an address compression device at the input of Video Decoder cache, the expansion of address is carried out in the address of this address compression device to two or more reference blocks of input continuously, on the basis of launching, folding operation is carried out to address identical in continuous print reference block, and mark folds the position of the address after merging;
Described decompression module, increase one-over-one address decompression machine, the mark passed in this address decompression machine process input for the output at Video Decoder cache, and utilize this mark, when the data of corresponding reference block are come in, the data on the address that reduction is folding.
Further, the address judgment mode of two or more reference blocks of continuous input is: the order of the reference block of input input, the address of reference block order generating reference block after Cache address generator, the order of this reference block designates the address of this reference block, width, elevation information, the address of continuous print reference block is then the order of two reference blocks entered continuously, and this order entering two reference blocks is continuously one group.
Further, describedly folding operation is carried out to address identical in continuous print reference block be specially: based on the characteristic of Video Decoder cache, the width of a Video Decoder cache line is 256bit, namely Video Decoder cache stores, the data length read once is 256bit, two continuous print reference blocks have the address of part to be arranged in same 256bit address size, overlapping address is exactly the address be present in two reference blocks in same 256bit, to eliminate in a rear reference block and namely address that previous reference block coexists in a 256bit is carried out identical address and carried out folding.
Further, described system comprises label module further: described label module: the mode of aliging by 256bit for the address all to two reference blocks is launched in order, obtain the address arrangement after two expansion, part is had to be overlap in these two address arrangement, carry out label successively to the 256bit address that two are launched in order, namely this label is the position of the address of reference block.
Further, the position of the address after described mark folds merging is specially: concrete mark represents the mode adopting label A_ label B, the position in the first reference block of the n-th address of the first reference block merged is carried out in label A representative, after label B represents and folds, need the data address of copy in the position of the second reference block carrying out merging.
Further, data on the address that described reduction folds are specially: two reference blocks entered continuously, then the overlap of the address of two reference blocks at most only occurs once, and address compression device carries out compressing according to the order of label, so data pass to the command queue of address decompression machine must be mode according to the corresponding label B of label A, at address decompression machine when inserting the buffer position of label A, accordingly identical data are inserted in buffer position corresponding to label B, complete reduction process.
Tool of the present invention has the following advantages: the present invention adopts each increase by one address compression device on Video Decoder cache front end processing block, to two or more reference blocks of input continuously, first carry out the expansion of reference block address, on the basis of launching, folding operation is carried out to the address of overlap, at the output of cache, increase one-over-one address and separate contracting device, for the treatment of the mark passed in front end processing block, and utilize this mark, when corresponding data are come in, the data on the address that reduction is folding; Promote Video Decoder cache data-handling capacity, improve the service efficiency of Video Decoder cache, thus promote the peek performance of Video Decoder.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of existing Video Decoder cache.
Fig. 2 is the structured flowchart of Video Decoder cache of the present invention.
Fig. 3 is the inventive method schematic flow sheet.
Fig. 4 is the structural representation of present system.
Embodiment
Refer to shown in Fig. 2 and Fig. 3, a kind of method improving Video Decoder cache treatment effeciency of the present invention,
Increase by an address compression device at the input of Video Decoder cache, the expansion of address is carried out in the address of this address compression device to two or more reference blocks of input continuously, on the basis of launching, folding operation is carried out to address identical in continuous print reference block, and mark folds the position of the address after merging;
The mode alignd by 256bit in all address of two reference blocks is launched in order, obtain the address arrangement after two expansion, part is had to be overlap in these two address arrangement, carry out label successively to the 256bit address that two are launched in order, namely this label is the position of the address of reference block.
Increase one-over-one address decompression machine at the output of Video Decoder cache, this address decompression machine process address compression device passes the mark of coming, and utilizes this mark, when the data of corresponding reference block are come in, and the data on the address that reduction is folding.The data of this corresponding reference block come in be: Video Decoder cache Notify Address decompression machine, the data of corresponding 256bit are had to need to store, the data transfer sequence of Video Decoder cache is that the designated command order passing to Video Decoder cache in strict accordance with address compression device carries out transfer of data, therefore, the data of reference block are all corresponding reference blocks.
Wherein, the address judgment mode of two or more reference blocks of continuous input is: the order of the reference block of input input, the address of reference block order generating reference block after Cache address generator, the order of this reference block designates the address of this reference block, width, elevation information, the address of continuous print reference block is then the order of two reference blocks entered continuously, and this order entering two reference blocks is continuously one group.
Describedly folding operation is carried out to address identical in continuous print reference block be specially: based on the characteristic of Video Decoder cache, the width of a Video Decoder cache line is 256bit, namely Video Decoder cache stores, the data length read once is 256bit, two continuous print reference blocks have the address of part to be arranged in same 256bit address size, overlapping address is exactly the address be present in two reference blocks in same 256bit, to eliminate in a rear reference block and namely address that previous reference block coexists in a 256bit is carried out identical address and carried out folding.
In the present invention, concrete mark represents the mode adopting label A_ label B, the position in the first reference block of the n-th address of the first reference block merged is carried out in label A representative, after label B represents and folds, needs the data address of copy in the position of the second reference block carrying out merging.(such as, 2nd address of first reference block and the 5th address overlap of second reference block, the address of the needs copy after then folding is the 5th address, then be labeled as A2_B5,4th address of such as first reference block and the 3rd address overlap of second reference block, the address of the needs copy after then folding is the 4th address, be then labeled as A4_B3.
In addition, in the present invention, data on the address that described reduction folds are specially: two reference blocks entered continuously, then the overlap of the address of two reference blocks at most only occurs once, and address compression device carries out compressing according to the order of label, so data pass to the command queue of address decompression machine must be mode according to the corresponding label B of label A, at address decompression machine when inserting the buffer position of label A, accordingly identical data are inserted in buffer position corresponding to label B, complete reduction process.
Refer to shown in Fig. 2 and Fig. 4, a kind of system improving Video Decoder cache treatment effeciency, described system comprises compression module, label module and decompression module;
Described compression module, for increasing by an address compression device at the input of Video Decoder cache, the expansion of address is carried out in the address of this address compression device to two or more reference blocks of input continuously, on the basis of launching, folding operation is carried out to address identical in continuous print reference block, and mark folds the position of the address after merging;
Described label module: the mode of aliging by 256bit for the address all to two reference blocks is launched in order, obtain the address arrangement after two expansion, part is had to be overlap in these two address arrangement, carry out label successively to the 256bit address that two are launched in order, namely this label is the position of the address of reference block.
Described decompression module, increase one-over-one address decompression machine, the mark passed in this address decompression machine process input for the output at Video Decoder cache, and utilize this mark, when the data of corresponding reference block are come in, the data on the address that reduction is folding.The data of this corresponding reference block come in be: Video Decoder cache Notify Address decompression machine, the data of corresponding 256bit are had to need to store, the data transfer sequence of Video Decoder cache is that the designated command order passing to Video Decoder cache in strict accordance with address compression device carries out transfer of data, therefore, the data of reference block are all corresponding reference blocks.
Wherein, the address judgment mode of two or more reference blocks of continuous input is: the order of the reference block of input input, the address of reference block order generating reference block after Cache address generator, the order of this reference block designates the address of this reference block, width, elevation information, the address of continuous print reference block is then the order of two reference blocks entered continuously, and this order entering two reference blocks is continuously one group.
Describedly folding operation is carried out to address identical in continuous print reference block be specially: based on the characteristic of Video Decoder cache, the width of a Video Decoder cache line is 256bit, namely Video Decoder cache stores, the data length read once is 256bit, two continuous print reference blocks have the address of part to be arranged in same 256bit address size, overlapping address is exactly the address be present in two reference blocks in same 256bit, to eliminate in a rear reference block and namely address that previous reference block coexists in a 256bit is carried out identical address and carried out folding.
In the present invention, the position of the address after described mark folds merging is specially: concrete mark represents the mode adopting label A_ label B, the position in the first reference block of the n-th address of the first reference block merged is carried out in label A representative, after label B represents and folds, need the data address of copy in the position of the second reference block carrying out merging.
Data on the address that described reduction folds are specially: two reference blocks entered continuously, then the overlap of the address of two reference blocks at most only occurs once, and address compression device carries out compressing according to the order of label, so data pass to the command queue of address decompression machine must be mode according to the corresponding label B of label A, at address decompression machine when inserting the buffer position of label A, accordingly identical data are inserted in buffer position corresponding to label B, complete reduction process.
In a word, the present invention adopts each increase by one address compression device on Video Decoder cache front end processing block, to two or more reference blocks of input continuously, first carries out the expansion of reference block address, on the basis of launching, folding operation is carried out to the address of overlap, at the output of cache, increases one-over-one address and separate contracting device, for the treatment of the mark passed in front end processing block, and utilize this mark, and when corresponding data are come in, the data on the address that reduction is folding; Promote Video Decoder cache data-handling capacity, improve the service efficiency of Video Decoder cache, thus promote the peek performance of Video Decoder.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. improve a method for Video Decoder cache treatment effeciency, it is characterized in that:
Increase by an address compression device at the input of Video Decoder cache, the expansion of address is carried out in the address of this address compression device to two or more reference blocks of input continuously, on the basis of launching, folding operation is carried out to address identical in continuous print reference block, and mark folds the position of the address after merging;
Increase one-over-one address decompression machine at the output of Video Decoder cache, this address decompression machine process address compression device passes the mark of coming, and utilizes this mark, when the data of corresponding reference block are come in, and the data on the address that reduction is folding.
2. a kind of method improving Video Decoder cache treatment effeciency according to claim 1, it is characterized in that: the address judgment mode of two or more reference blocks of input is continuously: the order of the reference block of input input, the address of reference block order generating reference block after Cache address generator, the order of this reference block designates the address of this reference block, width, elevation information, the address of continuous print reference block is then the order of two reference blocks entered continuously, and this order entering two reference blocks is continuously one group.
3. a kind of method improving Video Decoder cache treatment effeciency according to claim 1, it is characterized in that: describedly folding operation is carried out to address identical in continuous print reference block be specially: based on the characteristic of Video Decoder cache, the width of a Video Decoder cache line is 256bit, namely Video Decoder cache stores, the data length read once is 256bit, two continuous print reference blocks have the address of part to be arranged in same 256bit address size, overlapping address is exactly the address be present in two reference blocks in same 256bit, eliminate the address coexisted in a 256bit with previous reference block in a rear reference block and namely carry out identical address folding.
4. a kind of method improving Video Decoder cache treatment effeciency according to claim 1, it is characterized in that: described method comprises further: the mode alignd by 256bit in all address of two reference blocks is launched in order, obtain the address arrangement after two expansion, part is had to be overlap in these two address arrangement, carry out label successively to the 256bit address that two are launched in order, namely this label is the position of the address of reference block.
5. a kind of method improving Video Decoder cache treatment effeciency according to claim 4, it is characterized in that: the position of the address after described mark folds merging is specially: concrete mark represents the mode adopting label A_ label B, the position in the first reference block of the n-th address of the first reference block merged is carried out in label A representative, label B needs the address of copies data in the position of the second reference block carrying out merging after representing and folding.
6. a kind of method improving Video Decoder cache treatment effeciency according to claim 5, it is characterized in that: the data on the address that described reduction folds are specially: two reference blocks entered continuously, then the overlap of the address of two reference blocks at most only occurs once, and address compression device carries out compressing according to the order of label, so data pass to the command queue of address decompression machine must be mode according to the corresponding label B of label A, at address decompression machine when inserting the buffer position of label A, accordingly identical data are inserted in buffer position corresponding to label B, complete reduction process.
7. improve a system for Video Decoder cache treatment effeciency, it is characterized in that: described system comprises compression module and decompression module;
Described compression module, for increasing by an address compression device at the input of Video Decoder cache, the expansion of address is carried out in the address of this address compression device to two or more reference blocks of input continuously, on the basis of launching, folding operation is carried out to address identical in continuous print reference block, and mark folds the position of the address after merging;
Described decompression module, increase one-over-one address decompression machine, the mark passed in this address decompression machine process input for the output at Video Decoder cache, and utilize this mark, when the data of corresponding reference block are come in, the data on the address that reduction is folding.
8. a kind of system improving Video Decoder cache treatment effeciency according to claim 7, it is characterized in that: the address judgment mode of two or more reference blocks of input is continuously: the order of the reference block of input input, the address of reference block order generating reference block after Cache address generator, the order of this reference block designates the address of this reference block, width, elevation information, the address of continuous print reference block is then the order of two reference blocks entered continuously, and this order entering two reference blocks is continuously one group.
9. a kind of system improving Video Decoder cache treatment effeciency according to claim 7, it is characterized in that: describedly folding operation is carried out to address identical in continuous print reference block be specially: based on the characteristic of Video Decoder cache, the width of a Video Decoder cache line is 256bit, namely Video Decoder cache stores, the data length read once is 256bit, two continuous print reference blocks have the address of part to be arranged in same 256bit address size, overlapping address is exactly the address be present in two reference blocks in same 256bit, to eliminate in a rear reference block and namely address that previous reference block coexists in a 256bit is carried out identical address and carried out folding.
10. a kind of system improving Video Decoder cache treatment effeciency according to claim 7, it is characterized in that: described system comprises label module further: described label module: the mode of aliging by 256bit for the address all to two reference blocks is launched in order, obtain the address arrangement after two expansion, part is had to be overlap in these two address arrangement, carry out label successively to the 256bit address that two are launched in order, namely this label is the position of the address of reference block.
11. a kind of systems improving Video Decoder cache treatment effeciency according to claim 10, it is characterized in that: the position of the address after described mark folds merging is specially: concrete mark represents the mode adopting label A_ label B, the position in the first reference block of the n-th address of the first reference block merged is carried out in label A representative, after label B represents and folds, need the data address of copy in the position of the second reference block carrying out merging.
12. a kind of systems improving Video Decoder cache treatment effeciency according to claim 11, it is characterized in that: the data on the address that described reduction folds are specially: two reference blocks entered continuously, then the overlap of the address of two reference blocks at most only occurs once, and address compression device carries out compressing according to the order of label, so data pass to the command queue of address decompression machine must be mode according to the corresponding label B of label A, at address decompression machine when inserting the buffer position of label A, accordingly identical data are inserted in buffer position corresponding to label B, complete reduction process.
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