CN104851460A - Flash memory device - Google Patents
Flash memory device Download PDFInfo
- Publication number
- CN104851460A CN104851460A CN201410168060.4A CN201410168060A CN104851460A CN 104851460 A CN104851460 A CN 104851460A CN 201410168060 A CN201410168060 A CN 201410168060A CN 104851460 A CN104851460 A CN 104851460A
- Authority
- CN
- China
- Prior art keywords
- erasing
- transistor
- couple
- control
- end points
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Read Only Memory (AREA)
Abstract
The invention provides a flash memory device, which comprises a plurality of memory cell regions. Each of the memory cell regions is composed of a plurality of memory units, a programming voltage control generator and an erasing voltage control generator. Each memory unit receives the programming control voltage through a control endpoint for programming operations, and the memory unit receives the erasing voltage through an erasing endpoint for erasing operations. The programming voltage control generator supplies all the programming control voltages to the memory units. The erasing voltage control generator supplies all the erasing voltages to the memory units.
Description
Technical field
The present invention relates generally to flash memory device, in particular, relates to the flash memory device with booster circuit.
Background technology
Now, storer can be categorized as volatile memory and nonvolatile memory.The volatile memory such as such as dynamic RAM (dynamic random access memory, DRAM) have the advantage of fast programming and reading.But volatile memory only just operates when electric power is applied to flash memory.On the other hand, although the nonvolatile memories such as such as flash memory slowly operate when programming and read, information can be retained in inside by flash memory for a long time, is applied to flash memory also like this even without electric power.
Usually for the operation of flash memory, when programming or wipe, specific voltage is needed to draw for by charge injection to the floating grid of flash memory or by the floating grid of electric charge from flash memory.Therefore, usually need charge pump circuit or voltage generation circuit for operating flash storer.Therefore, the voltage generation circuit of flash memory circuit plays an important role in the operation of flash memory.
Summary of the invention
Therefore, the present invention relates to a kind of flash memory device, and more relate to the flash memory with low operating voltage and low power consumption.
The invention provides a kind of flash memory device.Described flash memory device comprises multiple memory cell area.Each in described memory cell area comprises multiple memory cell, programming Control voltage generator and erasing control voltage generator.Each in memory cell receives programming Control voltage by controlling end points, and receives erasing control voltage by erasing end points.Described programming Control voltage generator comprises pre-charge voltage transmitter and pumping capacitor.Described pre-charge voltage transmitter is couple to all described control end points of the described memory cell in described memory cell area.Described pumping capacitor is coupled between the described control end points of described memory cell and pumping voltage.Described pre-charge voltage is applied to the described control end points of described memory cell by described pre-charge voltage transmitter during the cycle very first time according to precharge enable signal.Described pumping voltage is applied to described pumping capacitor during the second time cycle, and produces the described control voltage for programming at the described control end points place of described memory cell.Described erasing control voltage generator comprises erasing pre-charge voltage transmitter and erasing pumping capacitor.Described erasing pre-charge voltage transmitter is couple to all described erasing end points of the described memory cell in described memory cell area.Described erasing pumping capacitor is coupled between the described erasing end points of described memory cell and erasing pumping voltage.Erasing pre-charge voltage is applied to the described erasing end points of described memory cell by described erasing pre-charge voltage transmitter during the 3rd time cycle according to erasing precharge enable signal.Described erasing pumping voltage is applied to described erasing pumping capacitor during the 4th time cycle, and produces the erasing control voltage for wiping at the described erasing end points place of described memory cell.
The invention provides another flash memory device.Described flash memory device comprises multiple memory cell area.Each in described memory cell area comprises multiple memory cell, multiple programming Control voltage generator and erasing control voltage generator.Each in memory cell receives programming Control voltage by controlling end points, and receives erasing control voltage by erasing end.Each in described programming Control voltage generator comprises pre-charge voltage transmitter and pumping capacitor.Described pre-charge voltage transmitter is couple to the described control end points of described correspond to memories unit.Described pre-charge voltage is applied to the described control end points of described correspond to memories unit by described pre-charge voltage transmitter during the cycle very first time according to precharge enable signal.Described pumping capacitor is coupled between the described control end points of described correspond to memories unit and pumping voltage.Described pumping voltage is applied to described pumping capacitor during the second time cycle, and produces the described programming Control voltage for programming at the described control end points place of described correspond to memories unit.Described erasing control voltage generator comprises erasing pre-charge voltage transmitter and erasing pumping capacitor.Described erasing pre-charge voltage transmitter is couple to all described erasing end points of described memory cell.Described erasing pumping capacitor is coupled between the described erasing end points of described memory cell and erasing pumping voltage.Erasing pre-charge voltage is applied to the described erasing end points of described memory cell by described erasing pre-charge voltage transmitter during the 3rd time cycle according to erasing precharge enable signal.Described erasing pumping voltage is applied to described erasing pumping capacitor during the 4th time cycle, and produces the erasing control voltage for wiping at the described erasing end points place of described memory cell.
As mentioned above, the invention provides a kind of flash memory device.The pre-charge voltage of outside is transferred to described control end points or the erasing end points of described memory cell by described flash memory device by pre-charge voltage transmitter, and makes the described pre-charge voltage received by the described control end points of described memory cell or erasing end points boost to the described programming Control voltage for operating described flash memory device or wipe control voltage.The pre-charge voltage applied from described device outside will decline and the power consumption of the outside of described device supply pre-charge voltage will reduce.
Accompanying drawing explanation
Comprise accompanying drawing to provide a further understanding of the present invention, and accompanying drawing to be incorporated in this instructions and to form the part of this instructions.Described graphic explanation embodiments of the invention, and together with the description in order to explain principle of the present invention.
Fig. 1 shows the schematic diagram of flash memory device according to an embodiment of the invention.
Fig. 2 A shows the schematic diagram of programming Control voltage generator 210.
Fig. 2 B shows the schematic diagram of the embodiment of pre-charge voltage transmitter 211 according to an embodiment of the invention.
Fig. 2 C displaying applies waveform according to an embodiment of the invention.
Fig. 3 A shows another part schematic diagram of flash memory device 300 according to an embodiment of the invention.
Fig. 3 B shows the schematic diagram wiping pre-charge voltage transmitter 331 according to an embodiment of the invention.
Fig. 3 C shows another embodiment of the erasing pre-charge voltage transmitter 331 comprising erasing precharge switch 333 according to an embodiment of the invention.
Fig. 3 D shows another embodiment of wiping pre-charge voltage transmitter 331 according to an embodiment of the invention.
Fig. 3 E shows another schematic diagram of the erasing pre-charge voltage transmitter 331 comprising erasing precharge switch 335 and 337 according to an embodiment of the invention.
Fig. 4 shows another schematic diagram of flash memory device 400 according to an embodiment of the invention.
Fig. 5 shows the another schematic diagram of flash memory device 500 according to an embodiment of the invention.
Fig. 6 shows the schematic diagram of memory cell area 600 according to an embodiment of the invention.
Fig. 7 shows another schematic diagram of memory cell area 700 according to an embodiment of the invention.
[main element label declaration]
100: flash memory device
110: programming Control voltage generator
120: memory cell
210: programming Control voltage generator
201: curve
203: curve
205: curve
207: curve
211: pre-charge voltage transmitter
213: precharge program switch
217: curve
220: memory cell
300: flash memory device
320: memory cell
330: erasing control voltage generator
331: erasing pre-charge voltage transmitter
333: erasing precharge switch
335: erasing precharge switch
337: erasing precharge switch
400: flash memory device
410: programming Control voltage generator
420: memory cell
430: erasing control voltage generator
500: flash memory device
501 ~ 50N: memory cell area
511 ~ 51M: memory cell
520: programming Control voltage generator
530: erasing control voltage generator
600: memory cell area
611 ~ 61N: memory cell
620: programming Control voltage generator
630: erasing control voltage generator
700: memory cell area
711 ~ 71N: memory cell
721 ~ 72N: programming Control voltage generator
730: erasing control voltage generator
BL: bit line
Cf: grid capacitor
Cfe: erase gate gated transistors
CL: control end points
Cp: pumping capacitor
Cpe: erasing pumping capacitor
CTLS: control signal
CTLS1: the first erasing control signal
CTLS2: the second erasing control signal
EL: erasing end points
M1: transistor
M2: transistor
M3: transistor
M4: transistor
MF: single many floating grid transistors
MO: operate transistor
MS: select transistor
PREN: precharge enable signal
PRENE: erasing precharge enable signal
PRENE1: the first erasing precharge enable signal
PRENE2: the second erasing precharge enable signal
SL: source electrode line
T1: time cycle
T2: time cycle
Vc: programming Control voltage
Vce: erasing control voltage
Vpr: pre-charge voltage
Vpre: erasing pre-charge voltage
Vpre1: the first erasing pre-charge voltage
Vpre2: the second erasing pre-charge voltage
Vpu: pumping voltage
Vpue: erasing pumping voltage
Embodiment
With detailed reference to embodiments of the invention, the example is illustrated in the accompanying drawings.As possible, same reference numbers is in the accompanying drawings and the description in order to refer to same or similar part.
Fig. 1 shows the schematic diagram of flash memory device 100 according to an embodiment of the invention.Please refer to Fig. 1.Flash memory device 100 comprises multiple memory cell 120 and multiple programming Control voltage generator 110.Memory cell 120 is by arranged in arrays, and programming Control voltage generator 110 is couple to the control end points CL of memory cell 120 respectively.In general, the memory cell 120 of flash memory device 100 comprises MF, such as, and piled grids floating grid transistor, single polycrystalline silicon layer floating grid transistor or dielectric memory transistor.The two ends of each in memory cell 120 are couple to source electrode line SL and bit line BL respectively.Memory cell 120 receives the programming Control voltage Vc produced by programming Control voltage generator 110 respectively and performs data program operation to control end points CL by it.
Fig. 2 A shows the schematic diagram of programming Control voltage generator 210.In fig. 2, programming Control voltage generator 210 comprises pre-charge voltage transmitter 211 and pumping capacitor Cp.Wherein, pre-charge voltage transmitter 211 is couple to the control end points CL of correspond to memories unit 220.About the operation of pre-charge voltage transmitter 211, first, precharge enable signal PREN is applied to pre-charge voltage transmitter 211 within the cycle very first time, and pre-charge voltage transmitter 211 is connected accordingly.Meanwhile, pre-charge voltage Vpr is applied to the control end points CL of correspond to memories unit 220 by the pre-charge voltage transmitter 211 connected.Meanwhile, the value of programming Control voltage Vc approximates the value of pre-charge voltage Vpr.On the other hand, pumping capacitor Cp is coupled between the control end points CL of correspond to memories unit 220 and pumping voltage Vpu.After the cycle very first time, pumping voltage Vpu is applied to one end of the pumping capacitor Cp of the one end not being couple to pre-charge voltage transmitter 211 during the second time cycle.Therefore, programming Control voltage Vc boosts at the control end points CL place of correspond to memories unit 220.In fact, the value of programming Control voltage Vc approximates the summation of the value of pumping voltage Vpu and the value of pre-charge voltage Vpr.
Then, please refer to Fig. 2 B.Fig. 2 B shows the schematic diagram of the embodiment of pre-charge voltage transmitter 211 according to an embodiment of the invention.In this embodiment, pre-charge voltage transmitter 211 comprises by the precharge program switch 213 of transistor M1 construction.Precharge program switch 213 has first end, the second end and control end.The first end of precharge program switch 213 is couple to the control end points CL of correspond to memories unit 220, and the second termination of precharge program switch 213 receives pre-charge voltage Vpr, and the control end of precharge program switch 213 receives precharge enable signal PREN.
For further explanation, please refer to Fig. 2 B and Fig. 2 C.Fig. 2 C displaying applies waveform according to an embodiment of the invention.In this embodiment, apply waveform and describe the multiple programming Control voltage generators 210 how simultaneously programming of execution selective data and data erase operation.When to the CL charging of control end points, please refer to the curve 201,203,205 and 207 in Fig. 2 C.During period of time T 1, second termination of transistor M1 receives the pre-charge voltage Vpr (curve 201) of such as 5 volts.In addition, the precharge enable signal PREN received by the control end of transistor M1 is biased into (such as) 7.5 volts (curve 203) and transistor M1 connects accordingly.Now, the initial value of pumping voltage Vpu is (such as) 0 volt (curve 205) and pre-charge voltage Vpr is transferred to the control end points CL of correspond to memories unit 220, and the value of programming Control voltage Vc equals the value (curve 207) of pre-charge voltage Vpr.Then, during period of time T 2, pumping voltage Vpu is biased into (such as) 5 volts (curve 205) and programming Control voltage Vc boosts to the value (curve 207) of (such as) 9.5 volts, and it approximates the summation of pre-charge voltage Vpr and pumping voltage Vpu.Then, memory cell 220 can perform data program operation.
According to another embodiment of the present invention, when to the CL electric discharge of control end points, please refer to curve 203,205,211 and 217.In this embodiment, precharge enable signal PREN and pumping voltage Vpu show identical with 205 with the curve 203 of above-described embodiment.In addition, during period of time T 1, transistor M1 receives the pre-charge voltage Vpr (curve 211) of (such as) 5 volts and the value of programming Control voltage Vc equals the value (curve 217) of pre-charge voltage Vpr.During period of time T 2, pre-charge voltage Vpr is driven into (such as) 0 volt (curve 211) downwards and programming Control voltage Vc discharges into (such as) 0 volt (curve 217).Then, memory cell 120 can perform data erase operation.
It should be noted that the level of precharge enable signal PREN can drive a little to the value of the pre-charge voltage entered before cycle T 2 downwards, such as, from 7.5 volts to 5 volts (curve 203).Now, transistor M1 cuts off, and is regarded as diode, and diode reverse is biased between pre-charge voltage Vpr and programming Control voltage Vc.So, when programming Control voltage Vc boosts during cycle T 2, pre-charge voltage Vpr does not affect the boosting of programming Control voltage Vc.
Fig. 3 A shows another part schematic diagram of flash memory device 300 according to an embodiment of the invention.Please refer to Fig. 3 A.Except data program operation, flash memory device 300 also needs voltage generation circuit to perform data erase operation.Therefore, in the flash memory device 300 of the present embodiment, erasing end points EL is couple to erasing control voltage generator 330, and erasing pre-charge voltage Vpre is transferred to the erasing end points EL of memory cell 320 according to erasing precharge enable signal PRENE.Then, the erasing control voltage Vce for wiping produces according to the erasing pumping voltage Vpue being applied to erasing pumping capacitor Cpe.Wherein, memory cell 320 comprises MF, such as, and piled grids floating grid transistor, single polycrystalline silicon layer floating grid transistor or dielectric memory transistor.
Fig. 3 B shows the schematic diagram wiping pre-charge voltage transmitter 331 according to an embodiment of the invention.Please refer to Fig. 3 B.Erasing pre-charge voltage transmitter 331 comprises erasing precharge switch 333.In this embodiment, erasing precharge switch 333 can be the transistor M1 be coupled between erasing pre-charge voltage Vpre and the erasing end points EL of correspond to memories unit 320, and transistor M1 connects according to erasing precharge enable signal PRENE.
Fig. 3 C shows another embodiment of the erasing pre-charge voltage transmitter 331 comprising erasing precharge switch 333 according to an embodiment of the invention.Please refer to Fig. 3 C, erasing precharge switch 333 also can be two transistor M1 and M2 be coupled in series between erasing pre-charge voltage Vpre and the erasing end points EL of correspond to memories unit 320, and transistor M1 and transistor M2 enables according to erasing precharge enable signal PRENE and control signal CTLS respectively.
Fig. 3 D shows another embodiment of wiping pre-charge voltage transmitter 331 according to an embodiment of the invention.Please refer to Fig. 3 D, erasing pre-charge voltage transmitter 331 comprises erasing precharge switch 335 and 337.Erasing precharge switch 335 and 337 can be coupled in the first erasing pre-charge voltage Vpre1 and correspond to memories unit 320 respectively erasing end points EL between and transistor M1 and M2 between the second erasing end points EL wiping pre-charge voltage Vpre2 and correspond to memories unit 320.Erasing precharge switch 335 and 337 is respectively by the first erasing precharge enable signal PRENE1 being applied to transistor M1 or the second erasing precharge enable signal PRENE2 being applied to transistor M2 and operating.
Fig. 3 E shows another schematic diagram of the erasing pre-charge voltage transmitter 331 comprising erasing precharge switch 335 and 337 according to an embodiment of the invention.Please refer to Fig. 3 E.Erasing precharge switch 335 and 337 can be implemented respectively by the transistor of two coupled in series.Erasing precharge switch 335 comprises transistor M1 and M3 between the erasing end points EL being coupled in series in the first erasing pre-charge voltage Vpre1 and correspond to memories unit 320, and erasing precharge switch 337 comprises transistor M2 and M4 between the erasing end points EL being coupled in series in the second erasing pre-charge voltage Vpre2 and correspond to memories unit 320.Or transistor M1 and M3 connects according to the first erasing precharge enable signal PRENE1 and first erasing control signal CTLS1, or transistor M2 and M4 connects according to the second erasing precharge enable signal PRENE2 and second erasing control signal CTLS2.By above process, erasing precharge switch 335 and erasing precharge switch 337 operate respectively.
Fig. 4 shows another schematic diagram of flash memory device 400 according to an embodiment of the invention.Please refer to Fig. 4.Flash memory device 400 comprises multiple programming Control voltage generator 410, multiple memory cell 420 and multiple erasing control voltage generator 430.More particularly, each being coupled in the memory cell 420 between source electrode line SL and bit line BL comprises single polycrystalline silicon layer floating grid transistor MF, selects transistor MS, operate transistor MO, grid capacitor Cf and erase gate gated transistors Cfe.
In the present embodiment, programming Control voltage Vc is provided to grid capacitor Cf by programming Control voltage generator 410, and erasing control voltage Vce is provided to erase gate electrode capacitor Cfe by erasing control voltage generator 330.Programming Control voltage generator 410 can be identical with the programming Control voltage generator 210 in Fig. 2 B.Erasing control voltage generator 430 can be identical with the one in the erasing control voltage generator 330 in Fig. 3 B to Fig. 3 E.
In addition, in general, the block of memory cell can operate while being wiped free of.Therefore, the number wiping pre-charge voltage transmitter reduces by an erasing pre-charge voltage transmitter and the integrated design of multiple memory cell.
It should be noted that being provided to the programming Control voltage Vc controlling end points CL has higher voltage level when memory cell 420 is programmed, and the programming Control voltage Vc being provided to control end points CL has lower voltage level when unit 420 is wiped free of.On the other hand, the erasing control voltage Vce being provided to erasing end points EL has higher voltage level when memory cell 420 is programmed or wipes.That is, boost during the same time cycle that programming Control voltage Vc and erasing control voltage Vce can be programmed at memory cell 420.
The another schematic diagram of flash memory device 500 is according to an embodiment of the invention shown referring to Fig. 5, Fig. 5.Flash memory device 500 comprises multiple memory cell area 501 to 50N.Memory cell area 501 comprises multiple memory cell, programming Control voltage generator and erasing control voltage generator to each in 50N.For example, memory cell area 501 comprises memory cell 511 to 51M, programming Control voltage generator 520 and erasing control voltage generator 530.
Programming Control voltage generator 520 can be implemented by programming Control voltage generator 210.Describe the operation of programming Control voltage generator 210 in detail before, and no longer repeated description herein.
It should be noted that all memory cells 511 in same memory cell area 501 are couple to programming Control voltage generator 520 to 51M herein.When memory cell 511 is programmed to the one in 51M, memory cell 511 is suppressed to the multiple not selected memory cells in 51M, and memory cell 511 is not suppressed to the word-select memory unit in 51M.
Erasing control voltage generator 530 can be implemented by erasing control voltage generator 330.Describe the operation of erasing control voltage generator 330 in detail before, and no longer repeated description herein.
All memory cells 511 in same memory cell area 501 are couple to erasing control voltage generator 530 to 51M.That is, all memory cells 511 being couple to erasing control voltage generator 530 in same memory cell area 501 can be wiped free of to 51M simultaneously.
The schematic diagram of memory cell area 600 is according to an embodiment of the invention shown referring to Fig. 6, Fig. 6.Memory cell area 600 comprises multiple memory cell 611 to 61N, programming Control voltage generator 620 and erasing control voltage generator 630.Programming Control voltage generator 620 is identical with wiping control voltage generator 530 with programming Control voltage generator 520 respectively with erasing control voltage generator 630.Memory cell 611 can be implemented by the memory cell 420 in Fig. 4 or the memory cell 120 in Fig. 1 to each in 61N.
For example, when memory cell 612 is chosen for when programming to each in 61N, memory cell 611 is suppressed.In this embodiment, memory cell 611 selection grid, select line, wordline and bit line can receive the voltage identical with the voltage (such as, 3.3 volts) for suppressing memory cell 611.In another embodiment, select grid and select line can be applied in a voltage (3.3 volts or 0 volt), and wordline and bit line can be applied in another voltage (0 volt or 3.3 volts) for suppression memory cell 611.That is, memory cell 612 to the memory cell in 61N by control store unit selection grid, select the voltage level of line, wordline and bit line and suppressed or not suppressed for programming.
Another schematic diagram of memory cell area 700 according to an embodiment of the invention is shown referring to Fig. 7, Fig. 7.Memory cell area 700 comprises multiple memory cell 711 to 71N, multiple programming Control voltage generator 721 to 72N and erasing control voltage generator 730.Programming Control voltage generator 721 is couple to memory cell 711 to 71N respectively to 72N, and multiple programming Control voltage is provided to memory cell 711 to 71N for programming operation to 72N by programming Control voltage generator 721 respectively.That is, memory cell 711 can individually be programmed to each in 71N.When memory cell 711 is programmed to each in 71N, programming Control voltage can be provided to the memory cell be programmed by corresponding programming Control voltage generator.
In a word, the invention provides a kind of flash memory device.The voltage applied from device outside reduces according to the boost operations of flash memory device, so that power consumption when reducing device outside supply voltage.In addition, memory cell can share erasing control voltage generator and/or programming Control voltage generator, and this causes the area of flash memory device to reduce.In addition, provide the design of multiple input voltage to expand the scope of input voltage and flash memory device is suitable at the electric pressing operation of difference.
It will be apparent to one skilled in the art that can when do not depart from the scope of the present invention or spirit various modifications and variations are done to structure of the present invention.In view of above content, wish that modifications and variations of the present invention are contained in the present invention, as long as described modifications and variations fall in the scope of appended claims and its equivalent.
Claims (22)
1. a flash memory device, comprising:
Multiple memory cell area, each in wherein said memory cell area comprises:
Multiple memory cell, each in wherein said memory cell receives programming Control voltage by controlling end points, and receives erasing control voltage by erasing end points;
Programming Control voltage generator, is couple to described memory cell, and wherein said programming Control voltage generator comprises:
Pre-charge voltage transmitter, is couple to all described control end points of described memory cell, according to precharge enable signal, pre-charge voltage is provided to the described control end points of described memory cell during the cycle very first time; And
Pumping capacitor, is coupled between the described control end points of described memory cell and the pumping voltage being applied to described pumping capacitor during the second time cycle, produces described programming Control voltage at the described control end points place of described memory cell; And
Erasing control voltage generator, be couple to described memory cell, wherein said erasing control voltage generator comprises:
Erasing pre-charge voltage transmitter, is couple to all described erasing end points of described memory cell, according to erasing precharge enable signal, erasing pre-charge voltage is provided to the described erasing end points of described memory cell during the 3rd time cycle; And
Erasing pumping capacitor, being coupled between the described erasing end points of described memory cell and the erasing pumping voltage being applied to described erasing pumping capacitor during the 4th time cycle, producing the described erasing control voltage for wiping.
2. flash memory device according to claim 1, wherein said pre-charge voltage transmitter comprises:
Precharge program switch, be coupled between described pre-charge voltage and the described control end points of described memory cell, described precharge program switch is connected according to described precharge enable signal and is transferred to described control end points for by described pre-charge voltage.
3. flash memory device according to claim 2, wherein said precharge program switch comprises:
The first transistor, there is first end, the second end and control end, the described first end of wherein said the first transistor and described second end are couple to the described control end points of described correspond to memories unit and described pre-charge voltage respectively, and the described control end of described the first transistor receives described precharge enable signal.
4. flash memory device according to claim 3, wherein said precharge program switch also comprises:
Transistor seconds, being coupled in described the first transistor is couple on the path of described control end points of described correspond to memories unit, there is first end, the second end and control end, the described first end of wherein said transistor seconds is couple to the described control end points of described correspond to memories unit, described second end of described transistor seconds is couple to the described first end of described the first transistor, and the described control end reception control signal of described transistor seconds.
5. flash memory device according to claim 1, wherein said pre-charge voltage transmitter comprises:
First precharge program switch, is coupled between the first pre-charge voltage and the described control end points of described correspond to memories unit; And
Second precharge program switch, is coupled between the second pre-charge voltage and the described control end points of described correspond to memories unit,
Wherein said first precharge program switch and described second precharge program switch are controlled by the first precharge enable signal and the second precharge enable signal respectively, and described first pre-charge voltage is transferred to the described control end points that described second pre-charge voltage is transferred to described correspond to memories unit by the described control end points of described correspond to memories unit or described second precharge program switch by described first precharge program switch.
6. flash memory device according to claim 5, wherein said first precharge program switch comprises:
The first transistor, there is first end, the second end and control end, the described first end of wherein said the first transistor and described second end are couple to the described control end points of described correspond to memories unit and described first pre-charge voltage respectively, and the described control end of described the first transistor receives described first precharge enable signal; And
Described second precharge program switch comprises:
Transistor seconds, there is first end, the second end and control end, wherein said first end and described second end are couple to the described control end points of described correspond to memories unit and described second pre-charge voltage respectively, and the described control end of described transistor seconds receives described second precharge enable signal.
7. flash memory device according to claim 6, wherein said first precharge program switch also comprises:
Third transistor, being coupled in described the first transistor is couple on the path of described control end points of described correspond to memories unit, there is first end, the second end and control end, the described first end of wherein said third transistor is couple to the described control end points of described correspond to memories unit, described second end of described third transistor is couple to the described first end of described the first transistor, and the described control end of described third transistor receives the first control signal; And
Described second precharge program switch also comprises:
4th transistor, being coupled in described transistor seconds is couple on the path of described control end points of described correspond to memories unit, there is first end, the second end and control end, the described first end of wherein said 4th transistor is couple to the described control end points of described correspond to memories unit, described second end of described 4th transistor is couple to the described first end of described transistor seconds, and the described control end of described 4th transistor receives the second control signal.
8. flash memory device according to claim 7, wherein said transistor seconds and described 4th transistor are P-type crystal pipe, and described the first transistor and described third transistor are N-type transistor.
9. flash memory device according to claim 1, each in wherein said memory cell comprises:
Floating grid transistor.
10. flash memory device according to claim 9, wherein said floating grid transistor is by following manufacture technics:
Single polycrystalline silicon layer CMOS technology.
11. flash memory devices according to claim 1, wherein said memory cell comprises:
Dielectric memory transistor.
12. flash memory devices according to claim 1, each being wherein couple in the described memory cell of source electrode line and bit line comprises:
Memory transistor, has first end, the second end and control end, and the described first end of wherein said memory transistor is couple to described source electrode line, and described second end of described memory transistor is couple to described bit line;
Select transistor, being coupled in described source electrode line is couple on the path of described memory transistor, there is first end, the second end and control end, the described first end of wherein said selection transistor is couple to described source electrode line, described second end of described selection transistor is couple to the first end of described memory transistor, and the described control end of described selection transistor receives selection signal;
Operate transistor, being coupled in described bit line is couple on the path of described memory transistor, there is first end, the second end and control end, the described first end of wherein said operate transistor is couple to described second end of described memory transistor, described second end of described operate transistor is couple to described bit line, and the described control end reception wordline of described operate transistor enables signal; And
Grid capacitor, is coupled between described programming Control voltage and the described control end of described memory transistor; And
Erase gate electrode capacitor, is coupled between erasing control voltage and the erasing end points of described memory transistor.
13. flash memory devices according to claim 12, wherein said memory transistor is:
Floating grid transistor.
14. flash memory devices according to claim 1, wherein said erasing pre-charge voltage transmitter comprises:
Erasing precharge switch, between the erasing end points being coupled in described erasing pre-charge voltage and described correspond to memories unit, it is connected according to described erasing precharge enable signal and is transferred to described erasing end points for by described erasing pre-charge voltage.
15. flash memory devices according to claim 14, wherein said erasing precharge switch comprises:
The first transistor, there is first end, the second end and control end, the described first end of wherein said the first transistor and described second end are couple to the described erasing end points of described correspond to memories unit and described erasing pre-charge voltage respectively, and the described control end of described the first transistor receives described erasing precharge enable signal.
16. flash memory devices according to claim 15, wherein said erasing precharge switch also comprises:
Transistor seconds, being coupled in described the first transistor is couple on the path of described erasing end points of described correspond to memories unit, there is first end, the second end and control end, the described first end of wherein said transistor seconds is couple to the described erasing end points of described correspond to memories unit, described second end of described transistor seconds is couple to the described first end of described the first transistor, and the described control end reception control signal of described transistor seconds.
17. flash memory devices according to claim 1, wherein said erasing pre-charge voltage transmitter comprises:
First erasing precharge switch, is coupled between the first erasing pre-charge voltage and the described erasing end points of described correspond to memories unit; And
Second erasing precharge switch, is coupled between the second erasing pre-charge voltage and the described erasing end points of described correspond to memories unit,
Wherein said first erasing precharge switch and described second erasing precharge switch are controlled by the first erasing precharge enable signal and the second erasing precharge enable signal respectively, and described first erasing pre-charge voltage or described second erasing pre-charge voltage are transferred to the described erasing end points of described correspond to memories unit.
18. flash memory devices according to claim 17, wherein said first erasing precharge switch comprises:
The first transistor, there is first end, the second end and control end, the described first end of wherein said the first transistor and described second end are couple to the described erasing end points of described correspond to memories unit and described first erasing pre-charge voltage respectively, and the described control end of described the first transistor receives described first erasing precharge enable signal; And
Described second erasing precharge switch comprises:
Transistor seconds, there is first end, the second end and control end, the described first end of wherein said transistor seconds and described second end are couple to the described erasing end points of described correspond to memories unit and described second erasing pre-charge voltage respectively, and the described control end of described transistor seconds receives described second erasing precharge enable signal.
19. flash memory devices according to claim 18, wherein said first erasing precharge switch also comprises:
Third transistor, being coupled in described the first transistor is couple on the path of described erasing end points of described correspond to memories unit, there is first end, the second end and control end, the described first end of wherein said third transistor is couple to the described erasing end points of described correspond to memories unit, described second end of described third transistor is couple to the described first end of described the first transistor, and the described control end of described third transistor receives the first erasing control signal; And
Described second erasing precharge switch also comprises:
4th transistor, being coupled in described transistor seconds is couple on the path of described erasing end points of described correspond to memories unit, there is first end, the second end and control end, the described first end of wherein said 4th transistor is couple to the described erasing end points of described correspond to memories unit, described second end of described 4th transistor is couple to the described first end of described transistor seconds, and the described control end of described 4th transistor receives the second erasing control signal.
20. flash memory devices according to claim 19, wherein said transistor seconds and described 4th transistor are P-type crystal pipe, and described the first transistor and described third transistor are N-type transistor.
21. flash memory devices according to claim 1, wherein said 3rd time cycle is overlapping with at least one in the described cycle very first time and described second time cycle, and described 4th time cycle is overlapping with at least one in the described cycle very first time and described second time cycle.
22. 1 kinds of flash memory devices, comprising:
Multiple memory cell area, each in wherein said memory cell area comprises:
Multiple memory cell, each in wherein said memory cell receives programming Control voltage by controlling end points, and receives erasing control voltage by erasing end points;
Multiple programming Control voltage generator, is couple to described memory cell respectively, in wherein said programming Control voltage generator described each comprise:
Pre-charge voltage transmitter, is couple to the described control end points of described correspond to memories unit, according to precharge enable signal, pre-charge voltage is provided to the described control end points of described correspond to memories unit during the cycle very first time; And
Pumping capacitor, be coupled between the described control end points of described correspond to memories unit and the pumping voltage being applied to described pumping capacitor during the second time cycle, produce described programming Control voltage at the described control end points place of described correspond to memories unit; And
Erasing control voltage generator, be couple to described memory cell, wherein said erasing control voltage generator comprises:
Erasing pre-charge voltage transmitter, is couple to all described erasing end points of memory cell, according to erasing precharge enable signal, erasing pre-charge voltage is provided to the described erasing end points of described memory cell during the 3rd time cycle; And
Erasing pumping capacitor, being coupled between the described erasing end points of described memory cell and the erasing pumping voltage being applied to described erasing pumping capacitor during the 4th time cycle, producing the described erasing control voltage for wiping.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/180,373 | 2014-02-14 | ||
| US14/180,373 US9153327B2 (en) | 2011-08-01 | 2014-02-14 | Flash memory apparatus with voltage boost circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104851460A true CN104851460A (en) | 2015-08-19 |
Family
ID=53851054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410168060.4A Pending CN104851460A (en) | 2014-02-14 | 2014-04-24 | Flash memory device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104851460A (en) |
| TW (1) | TWI528367B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5774392A (en) * | 1996-03-28 | 1998-06-30 | Ramtron International Corporation | Bootstrapping circuit utilizing a ferroelectric capacitor |
| CN101640067A (en) * | 2007-11-06 | 2010-02-03 | 旺宏电子股份有限公司 | Operation methods for memory cell and array for reducing punch through leakage |
| CN102915763A (en) * | 2011-08-01 | 2013-02-06 | 力旺电子股份有限公司 | Flash memory device |
-
2014
- 2014-03-21 TW TW103110715A patent/TWI528367B/en active
- 2014-04-24 CN CN201410168060.4A patent/CN104851460A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5774392A (en) * | 1996-03-28 | 1998-06-30 | Ramtron International Corporation | Bootstrapping circuit utilizing a ferroelectric capacitor |
| CN101640067A (en) * | 2007-11-06 | 2010-02-03 | 旺宏电子股份有限公司 | Operation methods for memory cell and array for reducing punch through leakage |
| CN102915763A (en) * | 2011-08-01 | 2013-02-06 | 力旺电子股份有限公司 | Flash memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI528367B (en) | 2016-04-01 |
| TW201532045A (en) | 2015-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100479063C (en) | Memory using boosted substrate/tub, method and system for operating same | |
| KR100252476B1 (en) | Non-volatile semiconductor memory device having electrically erasable and programmable memory cells of plate cell structure and program method thereof | |
| CN1866544B (en) | Nonvolatile semiconductor memory device | |
| KR102046073B1 (en) | Nonvolatile semiconductor memory device and Method of driving wordlines thereof | |
| TWI446524B (en) | Nand flash memory having multiple cell substrates | |
| CN101136249B (en) | Voltage generator circuit capable of generating different voltages based on operating mode of non-volatile semiconductor memory device | |
| US10020056B2 (en) | Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor | |
| KR100374640B1 (en) | Decoder for having not charge pump and non-volatile memory device including the same | |
| US9406685B2 (en) | Flash memory unit and memory array, and programming, erasing and reading method thereof | |
| CN106158037A (en) | Reading method and and nand type flash memory with nand type flash memory | |
| CN101675481A (en) | Non-volatile memory and method for compensation for voltage drops along a word line | |
| JP2008269727A (en) | Voltage booster circuit, semiconductor memory and drive method thereof | |
| JP2006252641A (en) | Semiconductor memory device, and method of driving semiconductor memory device | |
| CN105006247A (en) | High voltage switch circuit and nonvolatile memory including the same | |
| US9153327B2 (en) | Flash memory apparatus with voltage boost circuit | |
| CN102915763B (en) | Flash memory device | |
| CN101034591A (en) | Method for erasing the fast flash memory unit and fast flash memory device using the same | |
| US9564231B2 (en) | Non-volatile memory device and corresponding operating method with stress reduction | |
| US20130176793A1 (en) | Flash memory apparatus | |
| CN104851460A (en) | Flash memory device | |
| CN105989886B (en) | Nonvolatile semiconductor memory device | |
| JP3011570B2 (en) | Semiconductor memory | |
| CN107086052A (en) | Flash memory | |
| US9013925B2 (en) | Nonvolatile semiconductor memory device | |
| TWI485711B (en) | Flash memory apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150819 |
|
| WD01 | Invention patent application deemed withdrawn after publication |