CN102915763A - Flash memory device - Google Patents
Flash memory device Download PDFInfo
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- CN102915763A CN102915763A CN2012101476872A CN201210147687A CN102915763A CN 102915763 A CN102915763 A CN 102915763A CN 2012101476872 A CN2012101476872 A CN 2012101476872A CN 201210147687 A CN201210147687 A CN 201210147687A CN 102915763 A CN102915763 A CN 102915763A
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Abstract
The present invention provides a flash memory device, comprising a plurality of memory cells and a plurality of write control voltage generators. Each of the memory cells receives a write control voltage through a control endpoint, and performs the data writing operation according to the write control voltage. Each of the write control voltage generators includes a pre-charge voltage transmitter and a boost capacitor. These pre-charge voltage transmitters provide pre-charge voltages to the control endpoints corresponding to each of the memory cells, according to pre-charge driving signals in a first time period; a pushing up voltage is provided to the boost capacitor at a second time period, and the write control voltage is generated in the memory cells of the control endpoint.
Description
Technical field
The invention relates to a kind of flash memory device, and particularly relevant for a kind of flash memory device with voltage lifting circuit.
Background technology
Storer now can be divided into volatile memory and nonvolatile memory, volatile memory wherein, dynamic RAM (DRAM for example, Dynamic Random Access Memory), its advantage is that operation access speed is fast, yet only in the situation of power initiation, volatile memory could access data.On the other hand, nonvolatile memory, flash memory (flash memory) for example, although its operation access speed is slow than volatile memory, even under the situation of outage, the data of its internal reservoir can keep long time.
General flash memory, needs the specific voltage value with charge injection or draws floating boom (floating gate) when the operation that writes or erase in operating aspect.So, usually have a booster circuit (charge-pump circuit), or voltage generation circuit, provide voltage to operate.Therefore, the voltage generation circuit of flash memory has been played the part of an important role in flash disk operation.
Summary of the invention
Accordingly, the invention provides a kind of flash memory device, and a kind of flash memory device with characteristic of low input and low power consuming further is provided.
The present invention proposes a kind of flash memory device, comprises a plurality of storage unit and a plurality of control voltage generator that writes.Wherein each storage unit receives by the control end points and writes control voltage, and controls the operation that voltage writes with executing data according to writing.And a plurality of control voltage generators that write couple respectively those storage unit.Wherein respectively write the control voltage generator and comprise pre-charge pressure forwarder and boost capacitor.The pre-charge pressure forwarder is coupled to the control end points of each storage unit, and these pre-charge pressure forwarders also drive signal according to preliminary filling and provide the control end points of pre-charge pressure to corresponding storage unit in the cycle very first time.In addition, boost capacitor is coupled in the control end points of each storage unit and raises between voltage, raises voltage and is provided to boost capacitor in the second time cycle, and write control voltage in the control end points generation of these storage unit.
In one embodiment of this invention, above-mentioned flash memory device also comprises a plurality of control voltage generators of erasing.A plurality of control voltage generators of erasing couple respectively a plurality of storage unit.The control voltage generator of wherein respectively erasing comprises erase pre-charge pressure forwarder and the boost capacitor of erasing.The pre-charge pressure forwarder of erasing is coupled to the end points of erasing of each storage unit, and these pre-charge pressure forwarders of erasing also drive signal according to the preliminary filling of erasing and transmit the erase end points of pre-charge pressure to the storage unit of correspondence of erasing in the 3rd time cycle.The end points and erasing of erasing that the boost capacitor of erasing is coupled in each storage unit raises between voltage, erases to raise voltage and be provided to the boost capacitor of erasing in the 4th time cycle, produces the control voltage of erasing that is applied to erase.
Based on above-mentioned, the present invention proposes a kind of flash memory device, flash memory device transmits external voltage to the control of storage unit or the end points of erasing by the pre-charge pressure forwarder, and the pre-charge pressure that the control of storage unit or the end points of erasing receive is promoted to can be for the control voltage that writes or erase of flash memory device operation.The outside required voltage that provides of device will be lowered, also the therefore power consumption of the pre-charge pressure that provides of reducing apparatus outside.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Figure 1A illustrates the synoptic diagram of the flash memory device 100 of one embodiment of the invention.
Figure 1B illustrates the synoptic diagram that writes control voltage generator 110 of one embodiment of the invention.
Fig. 2 A illustrates the synoptic diagram of the pre-charge pressure forwarder 111 of one embodiment of the invention.
Fig. 2 B illustrates the operation waveform diagram of the pre-charge pressure forwarder 111 of this bright embodiment.
Fig. 2 C, Fig. 3 A and Fig. 3 B illustrate respectively the synoptic diagram of different embodiments of the pre-charge pressure forwarder 111 of one embodiment of the invention.
Fig. 4 illustrates the synoptic diagram of the flash memory device 400 of another embodiment of the present invention.
Fig. 5 A illustrates the partial circuit synoptic diagram of the flash memory device 500 of yet another embodiment of the invention.
Fig. 5 B～Fig. 5 E illustrates respectively the synoptic diagram of different embodiments of the pre-charge pressure forwarder 531 of erasing of the embodiment of the invention.
Fig. 6 illustrates the synoptic diagram of the flash memory device 600 of one embodiment of the invention.
[main element label declaration]
100,400,500,600: flash memory device
110,410,510: write the control voltage generator
111: pre-charge pressure forwarder 120,420,520,620: storage unit
113,115,117: the preliminary filling write switch
201,203,205,207,211,217: curve
530,630: the control voltage generator of erasing
531: the pre-charge pressure forwarder 533,535,537 of erasing: the preliminary filling switch of erasing
CL: control end points EL: the end points of erasing
Cp, Cf, Cpe, Cfe: electric capacity Vpu: raise voltage
PREN, PREN1, PREN2, PRENE, PRENE1, PRENE2: drive signal
Vc, Vce, Vpr, Vpr1, Vpr2, Vpre, Vpue, Vpre1, Vpre2: voltage
M1, M2, M3, M4, MF, MS, MO: transistor
T1, T2: time cycle CTLS, CTLS1, CTLS2: control signal
WL: word line BL: bit line
SL: source electrode line SG: select signal
Embodiment
Figure 1A illustrates the synoptic diagram of the flash memory device 100 of one embodiment of the invention.Please refer to Figure 1A, flash memory device 100 comprises a plurality of storage unit 120 and a plurality of control voltage generator 110 that writes.Storage unit 120 is arranged in the mode of array, and, respectively write the control end points CL that control voltage generator 110 is coupled to corresponding each storage unit 120.Generally speaking, the storage unit 120 of flash memory 100 comprises transistor MF, similarly is stacking-type floating boom transistor, single polycrystalline silicon floating gate transistor or dielectric medium storage transistor.The two ends of each storage unit 120 are coupled to respectively source electrode line SL and bit line BL.Storage unit 120 receives by writing writing of control voltage generator 110 generations by its control end points CL and controls voltage Vc, with indivedual executing data write operations.
Figure 1B illustrates the synoptic diagram that writes control voltage generator 110 of one embodiment of the invention.Please refer to Figure 1B, write control voltage generator 110 and comprise pre-charge pressure forwarder 111 and boost capacitor Cp.Pre-charge pressure forwarder 111 wherein is coupled to the control end points CL of storage unit 120.About the operation of pre-charge pressure forwarder 111, at first, in the cycle very first time, provide preliminary filling to drive signal PREN to pre-charge pressure forwarder 111, so that the 111 corresponding conductings of pre-charge pressure forwarder.At the same time, pre-charge pressure Vpr can be by the pre-charge pressure forwarder 111 of conducting, and is provided to the control end points CL of corresponding storage unit 120.At this moment, write the magnitude of voltage that the magnitude of voltage of controlling voltage Vc equals pre-charge pressure Vpr.In addition on the one hand, boost capacitor Cp is coupled in the control end points CL of storage unit 120 and raises between voltage Vpu, and at very first time week after date, raise voltage Vpu in the second time cycle and be provided on the end points that boost capacitor Cp do not couple pre-charge pressure forwarder 111.Thus, the control voltage Vc that writes on the control end points CL of storage unit 120 will be raised.Specifically, the magnitude of voltage that writes control voltage Vc of this moment approaches the magnitude of voltage that the magnitude of voltage that equals to raise voltage Vpu adds pre-charge pressure Vpr.
Then please refer to Fig. 2 A, Fig. 2 A illustrates the synoptic diagram of an embodiment of the pre-charge pressure forwarder 111 of one embodiment of the invention.In the present embodiment, pre-charge pressure forwarder 111 comprises preliminary filling write switch 113, and it is by the construction of transistor M1 institute.Preliminary filling write switch 113 has first end, the second end and control end, the first end of preliminary filling write switch 113 couples the control end points CL of corresponding storage unit 120, the second termination of preliminary filling write switch 113 is received pre-charge pressure Vpr, and the control end of preliminary filling write switch 113 receives preliminary filling driving signal PREN.
In order to illustrate further, please cooperate with reference to Fig. 2 A and 2B.Wherein, Fig. 2 B illustrates the applied waveforms figure of the pre-charge pressure forwarder 111 of this bright embodiment.In present embodiment, applied waveforms figure illustrates a plurality of control voltage generators 110 that write and how to come to carry out simultaneously optionally that data write and the data erase operation for use.When to control end points CL charging, please refer to the curve 201,203,205 and 207 of Fig. 2 B.When period of time T 1, the second termination of transistor M1 is received pre-charge pressure Vpr, for example 5 volts (curve 201).In addition, the preliminary filling that is received by the control end of transistor M1 drives signal PREN and is biased into for example 7.5 volts (curve 203), and the corresponding conducting of transistor M1.In this simultaneously, the initial value that raises voltage Vpu for example is 0 volt (curve 205), and pre-charge pressure Vpr is sent to the control end CL of corresponding storage unit 120, and writes the value (curve 207) that the value of controlling voltage Vc is equal to pre-charge pressure Vpr.Then, when the second period of time T 2, raise voltage Vpu and be biased into for example 5 volts (curves 205), write control voltage Vc and raised to for example 9.5 volts (curves 207), its value approximates pre-charge pressure Vpr and raises voltage Vpu sum.Next, but 120 executing data write operations of storage unit.
In another embodiment of the present invention, when to control end points CL discharge, please refer to curve 203,205,211 and 217.In the present embodiment, preliminary filling drives signal PREN and the curve 203 and 205 that raises voltage Vpu performance as above-mentioned embodiment.In addition, in very first time during cycle T 1, it for example is 5 volts (curves 211) that transistor M1 receives pre-charge pressure Vpr, and the value that writes control voltage Vc is equal to the value (curve 217) of pre-charge pressure Vpr.When period of time T 2, pre-charge pressure Vpr is driven to be down to for example 0 volt (curve 211), and writes control voltage Vc and be discharged to for example 0 volt (curve 217).Then, but storage unit 120 executing datas are smeared money operation.
It should be noted that preliminary filling drove signal PREN before entry time cycle T 2, voltage level can slightly drop to identical with pre-charge pressure Vpr, for example is down to 5 volts (curves 203) from 7.5 volts.Transistor M1 will end and become the form of diode this moment, and reverse bias is in pre-charge pressure Vpr and write and control between the voltage Vc.Thus, writing control voltage Vc when the second period of time T 2 is raised, the unlikely quilt that writes control voltage Vc that has influence on of pre-charge pressure Vpr raises operation.
Below please refer to Fig. 2 C, Fig. 2 C illustrates another embodiment of the pre-charge pressure forwarder 111 of the embodiment of the invention.Please refer to Fig. 2 C, not identical with a upper embodiment is that in the present embodiment, the preliminary filling write switch 113 in the pre-charge pressure forwarder 111 also comprises transistor M2 and transistor M1.Transistor M1 and transistor M2 distinctly comprise first end, the second end and control end.Transistor M2 is connected in series with transistor M1, and transistor M2 is coupled between the path of control end points CL that transistor M1 couples corresponding storage unit 120.Illustrate that more specifically the first end of transistor M2 is coupled to the control end points CL of corresponding storage unit 120, the second end of transistor M2 is coupled to the first end of transistor M1, the control end reception control signal CTLS of transistor M2.By this, by the serial connection of transistor M1 and transistor M2, just can allow the voltage difference of the maximum possible that writes control voltage Vc and pre-charge pressure Vpr, share on transistor M1 and transistor M2.
Please refer to Fig. 3 A, Fig. 3 A illustrates the synoptic diagram of another embodiment of the pre-charge pressure forwarder 111 of the embodiment of the invention.In the present embodiment, pre-charge pressure forwarder 111 comprises preliminary filling write switch 115 and preliminary filling write switch 117.Preliminary filling write switch 115 is serially connected between the control end points CL of the first pre-charge pressure Vpr1 and corresponding storage unit 120, and preliminary filling write switch 117 is serially connected between the control end points CL of the second pre-charge pressure Vpr2 and corresponding storage unit 120.Preliminary filling write switch 115 and 117 comprises respectively transistor M1 and M2, transistor M1 is coupled between the control end points CL of the first pre-charge pressure Vpr1 and corresponding storage unit 120, and transistor M2 is coupled between the control end points CL of the second pre-charge pressure Vpr2 and corresponding storage unit 120.Drive signal PREN1 or the second preliminary filling driving signal PREN2 according to the first preliminary filling respectively, the first or second pre-charge pressure Vpr1 or Vpr2 are reached storage unit 120.
Note that in the present embodiment, can transmit by preliminary filling write switch 115 or 117 pre-charge pressure of different magnitudes of voltage, for example is the first or second pre-charge pressure Vpr1 or Vpr2, to meet the voltage requirements of different operating.For instance, when the operation that executing data writes, can provide data to write needed the second pre-charge pressure Vpr2, for example 5 volts by preliminary filling write switch 117.On the other hand, if will carry out different operation (for example read operation), also can provide the first pre-charge pressure Vpr1 by preliminary filling write switch 115, for example 0 volt.By this, can via different switches, transmit different magnitudes of voltage to the control end points CL of corresponding storage unit 120.
Please refer to Fig. 3 B, the pre-charge pressure forwarder 111 that Fig. 3 B illustrates the embodiment of the invention comprises the again synoptic diagram of an embodiment of preliminary filling write switch 115 and 117.The preliminary filling write switch 115 of present embodiment and 117 can form with two transistor series connections respectively.Preliminary filling write switch 115 comprises transistor M1 and M3, is serially connected with between the control end points CL of the first pre-charge pressure Vpr1 and corresponding storage unit 120.Similarly, preliminary filling write switch 117 comprises transistor M2 and M4, is serially connected with between the control end points CL of the second pre-charge pressure Vpr2 and corresponding storage unit 120.The two select one be, in the present embodiment, the first pre-charge pressure Vpr1 can be by providing the first preliminary filling to drive signal PREN1 to the control end of transistor M1 and the control end of the first control signal CTLS1 to transistor M3 being provided, be passed to the control end points CL of corresponding storage unit 120, or, the second pre-charge pressure Vpr2 can by providing the second preliminary filling to drive signal PREN2 to the control end of transistor M2 and the control end of the second control signal CTLS2 to transistor M4 being provided, be passed to the control end points CL of corresponding storage unit 120.
It is worth mentioning that in embodiments of the present invention, transistor M1 and the transistor M3 of preliminary filling write switch 115 can be the N-type transistor.Relatively, the transistor M2 of preliminary filling write switch 117 and transistor M4 can be the P transistor npn npn.The P transistor npn npn is suitable for transmitting high voltage, and for example 5 volts, and the N-type transistor is suitable for transmitting low-voltage, for example 0 volt.Thus, the pre-charge pressure forwarder 111 of present embodiment is applicable to the on a large scale voltage transmission of operating flash memory.
Fig. 4 illustrates the synoptic diagram of the flash memory device 400 of another embodiment of the present invention.Please refer to Fig. 4, flash memory device 400 comprises a plurality of storage unit 420 and a plurality of control voltage generators 410 that write.Each storage unit 420 that is coupled between source electrode line SL and the bit line BL comprises single polycrystalline silicon floating gate transistor MF, selects transistor MS, operate transistor MO and gate pole capacitor C f.Single polycrystalline silicon floating gate transistor MF, selection transistor MS and operate transistor MO respectively comprise first end, the second end and control end.The first end of single polycrystalline silicon floating gate transistor MF couples source electrode line SL, and the second end of single polycrystalline silicon floating gate transistor MF couples bit line BL, and the reception of the control end of single polycrystalline silicon floating gate transistor MF writes control voltage Vc in order to operation.Select transistor MS to be coupled on the path that source electrode line SL couples single polycrystalline silicon floating gate transistor MF.In detail, select the first end of transistor MS to couple source electrode line SL, select the second end of transistor MS to couple the first end of single-polysilicon gridistor MF, and select the control end of transistor MS to receive selection signal SG.Operate transistor MO is coupled on the path that bit line BL couples single polycrystalline silicon floating gate transistor MF.More specifically, the first end of operate transistor MO couples the second end of single-polysilicon gridistor MF, and the second end of operate transistor MO couples bit line BL, and the control end of operate transistor MO couples word line drive signal WL.In addition, grid capacitance Cf is coupled between the control end that writes control voltage Vc and single polycrystalline silicon floating gate transistor MF.
Fig. 5 A illustrates the partial circuit synoptic diagram of the flash memory device 500 of yet another embodiment of the invention.Please refer to Fig. 5 A, except the operation that data write, flash memory device 500 also needs voltage generation circuit to carry out erase operation for use.Therefore, in the flash memory device 500 of present embodiment, the end points EL that erases of storage unit 520 couples the control voltage generator 530 of erasing, and the pre-charge pressure Vpre that erases is passed to the end points EL that erases of storage unit 520 according to the preliminary filling driving signal PRENE that erases.And then, raise voltage Vpue to the erasing of boost capacitor Cpe of erasing and produce according to providing in order to the control voltage Vce that erases that erases.Wherein, storage unit 520 comprises transistor MF, similarly is stacking-type floating boom transistor, single polycrystalline silicon floating gate transistor or dielectric medium storage transistor.
Fig. 5 B illustrates the synoptic diagram of the pre-charge pressure forwarder 531 of erasing of one embodiment of the invention.Please refer to Fig. 5 B, the pre-charge pressure forwarder 531 of erasing comprises the preliminary filling switch 533 of erasing, in present embodiment, the preliminary filling switch 533 of wherein erasing can be transistor M1, be coupled to erasing between the end points EL of erase pre-charge pressure Vpre and corresponding storage unit 520, and drive signal PRENE according to the preliminary filling of erasing, with transistor M1 conducting.
The pre-charge pressure forwarder 531 of erasing that Fig. 5 C illustrates one embodiment of the invention comprises another embodiment of the preliminary filling switch 533 of erasing.Please refer to Fig. 5 C, the preliminary filling switch 533 of erasing also can comprise two transistor M1 and M2, be serially connected with erasing between the end points EL of erase pre-charge pressure Vpre and corresponding storage unit 520, and drive signal PRENE and control signal CTLS driving transistors M1 and transistor M2 according to preliminary filling respectively.
Fig. 5 D illustrates another embodiment of the pre-charge pressure forwarder 531 of erasing of one embodiment of the invention.Please refer to Fig. 5 D, the pre-charge pressure forwarder 531 of erasing comprises erase preliminary filling switch 535 and 537.The preliminary filling switch 535 and 537 of erasing can be transistor M1 and M2, be respectively coupled to the first erase the erasing between the end points EL of pre-charge pressure Vpre1 and corresponding storage unit 520, and between the second erase the erasing between the end points EL of pre-charge pressure Vpre2 and corresponding storage unit 520.By providing respectively first preliminary filling of erasing to drive signal PRENE1 to transistor M1, or provide second preliminary filling of erasing to drive signal PRENE2 to transistor M2, operate erase preliminary filling switch 535 and 537.
The pre-charge pressure forwarder 531 of erasing that Fig. 5 E illustrates one embodiment of the invention comprises another embodiment of erase preliminary filling switch 535 and 537.Please refer to Fig. 5 E, the preliminary filling switch 535 and 537 of erasing can be realized with two transistor series connections respectively.The preliminary filling switch 535 of erasing comprises that transistor M1 and M3 are serially connected with the first erase the erasing between the end points EL of pre-charge pressure Vpre1 and corresponding storage unit 520, and the preliminary filling switch 537 of erasing comprises that transistor M2 and M4 are serially connected with the second erase the erasing between the end points of pre-charge pressure Vpre2 and corresponding storage unit 520.The two select one be, can drive signal PRENE1 and first erase control signal CTLS1 turn-on transistor M1 and M3 according to first preliminary filling of erasing, or, drive signal PRENE2 and second erase control signal CTLS2 turn-on transistor M2 and M4 according to second preliminary filling of erasing.By above-mentioned process, respectively the preliminary filling switch 535 or 537 of erasing is operated.
Fig. 6 illustrates the synoptic diagram of the flash memory device 600 of one embodiment of the invention.Please refer to Fig. 6, present embodiment is roughly identical with Fig. 4 embodiment, represents same or analogous element in the identical reference number of Fig. 6.Compared to the storage arrangement 400 of Fig. 4 embodiment, flash memory device 600 also comprises a plurality of storage unit 620 and a plurality of control voltage generator 630 of erasing.More specifically, each storage unit 620 that is coupled between source electrode line SL and bit line BL comprises single polycrystalline silicon floating gate transistor MF, selects transistor MS, operate transistor MO, grid capacitance Cf and the grid capacitance Cfe that erases.
In addition, generally speaking, when data are erased, the operation that can erase simultaneously for the storage unit of a whole block.Therefore, by the arrange in pairs or groups design of a plurality of storage unit of the pre-charge pressure forwarder of erasing, can reduce the quantity of the pre-charge pressure forwarder of erasing.
In sum, the present invention proposes a kind of flash memory device, according to the operation of this flash memory device booster tension, can reduce the outside required voltage that provides of device, so the power consumption that produces when voltage is provided of reducing apparatus outside.In addition, provide the design of multiple voltage input, to enlarge the scope of voltage input, be beneficial to flash memory device and under different voltages, carry out various operations.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (21)
1. flash memory device comprises:
A plurality of storage unit, wherein respectively this storage unit receives by the control end points and writes control voltage, and writes the operation that control voltage executing data writes according to this; And
A plurality of control voltage generators that write couple respectively this a plurality of storage unit, wherein respectively this write control voltage generator comprise:
The pre-charge pressure forwarder is coupled to the respectively control end points of this storage unit, and those pre-charge pressure forwarders drive signal when the cycle very first time according to preliminary filling, and the control end points of pre-charge pressure to corresponding storage unit is provided; And
Boost capacitor is coupled in the control end points of this storage unit respectively and raises between voltage, and this raises voltage and is provided to this boost capacitor in the second time cycle, and produces this at the control end points of these a plurality of storage unit and write control voltage.
2. flash memory device according to claim 1, wherein this pre-charge pressure forwarder comprises:
The preliminary filling write switch is coupled between the control end points of this pre-charge pressure and corresponding this storage unit, this preliminary filling write switch and drive signal with conducting, this pre-charge pressure is sent to this control end points according to this preliminary filling in this cycle very first time.
3. flash memory device according to claim 2, wherein this preliminary filling write switch comprises:
The first transistor, have first end, the second end and control end, wherein the first end of this first transistor and the second end are coupled to respectively control end points and this pre-charge pressure of this corresponding storage unit, and the control end of this first transistor receives this preliminary filling driving signal.
4. flash memory device according to claim 3, wherein this preliminary filling write switch also comprises:
Transistor seconds, be coupled between the path of control end points that this first transistor couples this corresponding storage unit, this transistor seconds has first end, the second end and control end, wherein the first end of this transistor seconds is coupled to the control end points of this corresponding storage unit, the second end of this transistor seconds is coupled to the first end of this first transistor, and the control end of this transistor seconds receives a control signal.
5. flash memory device according to claim 1, wherein this pre-charge pressure forwarder comprises:
The first preliminary filling write switch is coupled between the control end points of the first pre-charge pressure and corresponding this storage unit; And
The second preliminary filling write switch is coupled between the control end points of the second pre-charge pressure and corresponding this storage unit,
Wherein, this the first preliminary filling write switch and this second preliminary filling write switch are controlled by respectively the first preliminary filling and drive signal and the second preliminary filling driving signal, this the first preliminary filling write switch transmits this first pre-charge pressure to the control end points of this corresponding storage unit, or this second preliminary filling write switch transmits this second pre-charge pressure to the control end points of this corresponding storage unit.
6. flash memory device according to claim 5, wherein this first preliminary filling write switch comprises:
The first transistor, have first end, the second end and control end, wherein the first end of this first transistor and the second end are coupled to respectively control end points and this first pre-charge pressure of this corresponding storage unit, and the control end of this first transistor receives this first preliminary filling driving signal; And
This second preliminary filling write switch comprises:
Transistor seconds, have first end, the second end and control end, wherein the first end of this transistor seconds and the second end are coupled to respectively control end points and this second pre-charge pressure of this corresponding storage unit, and the control end of this transistor seconds receives this second preliminary filling driving signal.
7. flash memory device according to claim 6, wherein this first preliminary filling write switch also comprises:
The 3rd transistor, be coupled between the path of control end points that this first transistor couples this corresponding storage unit, the 3rd transistor has first end, the second end and control end, wherein the 3rd transistorized first end is coupled to the control end points of this corresponding storage unit, the 3rd transistorized the second end is coupled to the first end of this first transistor, and the 3rd transistorized control end receives the first control signal; And
This second preliminary filling write switch also comprises:
The 4th transistor, be coupled between the path of control end points that this transistor seconds couples this corresponding storage unit, the 4th transistor has first end, the second end and control end, wherein the 4th transistorized first end is coupled to the control end points of this corresponding storage unit, the 4th transistorized the second end is coupled to the first end of this transistor seconds, and the 4th transistorized control end receives the second control signal.
8. flash memory device according to claim 7, wherein this transistor seconds and the 4th transistor are the P transistor npn npn, this first transistor and the 3rd transistor are the N-type transistor.
9. flash memory device according to claim 1, wherein respectively this storage unit comprises:
Floating grid transistor.
10. flash memory device according to claim 9, wherein the manufacturing of this floating grid transistor is passed through:
Single polycrystalline silicium complementary metal oxide semiconductor transistor processing procedure.
11. flash memory device according to claim 1, wherein respectively this storage unit comprises:
The dielectric medium storage transistor.
12. flash memory device according to claim 1, wherein respectively this storage unit is coupled to source electrode line and bit line, and respectively this storage unit comprises:
Storage transistor has first end, the second end and control end, and wherein the first end of this storage transistor couples this source electrode line, and the second end of this storage transistor couples this bit line;
Select transistor, be coupled on the path that this source electrode line couples this storage transistor, this selection transistor has first end, the second end and control end, wherein the transistorized first end of this selection couples this source electrode line, this selects transistorized the second end to couple the first end of this storage transistor, and should select transistorized control end to receive and select signal;
Operate transistor, be coupled on the path that this bit line couples this storage transistor, this operate transistor has first end, the second end and control end, wherein the first end of this operate transistor couples the second end of this storage transistor, the second end of this operate transistor couples this bit line, and the control end of this operate transistor receives word line drive signal; And
Grid capacitance is coupled between this control end that writes control voltage and this storage transistor.
13. flash memory device according to claim 12, wherein this storage transistor is the floating boom transistor.
14. flash memory device according to claim 1 also comprises:
A plurality of control voltage generators of erasing couple respectively this a plurality of storage unit, and wherein respectively this control voltage generator of erasing comprises:
The pre-charge pressure forwarder of erasing is coupled to the respectively end points of erasing of this storage unit, those pre-charge pressure forwarders and drive signal according to the preliminary filling of erasing and transmit the erase end points of pre-charge pressure to this corresponding storage unit of erasing in the 3rd time cycle of erasing; And
The end points and erasing of erasing that the boost capacitor of erasing, this boost capacitor of erasing are coupled in this storage unit respectively raises between voltage, and this is erased and raises voltage and be provided to this boost capacitor of erasing in the 4th time cycle, produces this control voltage of erasing that is applied to erase.
15. flash memory device according to claim 14, wherein this pre-charge pressure forwarder of erasing comprises:
The preliminary filling switch of erasing is coupled in this erasing between end points of pre-charge pressure and corresponding this storage unit of erasing, and this preliminary filling switch of erasing drives signal conduction to transmit this pre-charge pressure of erasing to this end points of erasing according to this preliminary filling of erasing.
16. flash memory device according to claim 15, wherein this preliminary filling switch of erasing comprises:
The first transistor, have first end, the second end and control end, wherein the first end of this first transistor and the second end couple respectively erase end points and this pre-charge pressure of erasing of this corresponding storage unit, and the control end of this first transistor receives this preliminary filling driving signal of erasing.
17. flash memory device according to claim 16, wherein this preliminary filling switch of erasing also comprises:
Transistor seconds, be coupled between the path of the end points of erasing that this first transistor couples this corresponding storage unit, this transistor seconds has first end, the second end and control end, wherein the first end of this transistor seconds is coupled to the end points of erasing of this corresponding storage unit, the second end of this transistor seconds is coupled to the first end of this first transistor, the control end reception control signal of this transistor seconds.
18. flash memory device according to claim 14, wherein this pre-charge pressure forwarder of erasing comprises:
The first preliminary filling switch of erasing is coupled in the first erase the erasing between end points of pre-charge pressure and corresponding this storage unit; And
The second preliminary filling switch of erasing is coupled in the second erase the erasing between end points of pre-charge pressure and corresponding this storage unit,
Wherein, this first preliminary filling switch and this second preliminary filling switch of erasing of erasing is controlled by respectively this preliminary filling and drives first of the signal preliminary filling of erasing and drive signal and second preliminary filling of erasing and drive signal, and transmits this first pre-charge pressure or this second the erase end points of pre-charge pressure to this corresponding storage unit of erasing of erasing.
19. flash memory device according to claim 18, wherein this first preliminary filling switch of erasing comprises:
The first transistor, have first end, the second end and control end, the wherein first end of this first transistor and the second end end points and this first of erasing that be coupled to respectively this corresponding storage unit pre-charge pressure of erasing, and the control end of this first transistor receives this first preliminary filling of erasing and drives signal; And
This second preliminary filling switch of erasing comprises:
Transistor seconds, have first end, the second end and control end, the wherein first end of this transistor seconds and the second end end points and this second of erasing that be coupled to respectively this corresponding storage unit pre-charge pressure of erasing, and the control end of this transistor seconds receives this second preliminary filling of erasing and drives signal.
20. flash memory device according to claim 19, wherein this first preliminary filling write switch also comprises:
The 3rd transistor, be coupled between the path of the end points of erasing that this first transistor couples this corresponding storage unit, the 3rd transistor has first end, the second end and control end, wherein the 3rd transistorized first end is coupled to the end points of erasing of this corresponding storage unit, the 3rd transistorized the second end is coupled to the first end of this first transistor, and the 3rd transistorized control end receives first control signal of erasing; And
This second preliminary filling switch of erasing also comprises
The 4th transistor, be coupled between the path of the end points of erasing that this transistor seconds couples this corresponding storage unit, the 4th transistor has first end, the second end and control end, wherein the 4th transistorized first end is coupled to the end points of erasing of this corresponding storage unit, the 4th transistorized the second end is coupled to the first end of this transistor seconds, and the 4th transistorized control end receives second control signal of erasing.
21. flash memory device according to claim 20, wherein this transistor seconds and the 4th transistor are the P transistor npn npn, and this first transistor and the 3rd transistor are the N-type transistor.
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| JP5380576B2 (en) | 2014-01-08 |
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