CN104838486B - Semiconductor devices and the self adaptive patterned method for board-like encapsulation - Google Patents

Semiconductor devices and the self adaptive patterned method for board-like encapsulation Download PDF

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Publication number
CN104838486B
CN104838486B CN201380064057.1A CN201380064057A CN104838486B CN 104838486 B CN104838486 B CN 104838486B CN 201380064057 A CN201380064057 A CN 201380064057A CN 104838486 B CN104838486 B CN 104838486B
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semiconductor chip
chip
panel
semiconductor
layer
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CN104838486A (en
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C.M.斯坎伦
T.L.奥尔森
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Decca Technology Inc
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Deca Technologies Inc
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Priority claimed from US13/891,006 external-priority patent/US9196509B2/en
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A kind of self adaptive patterning method and system for encapsulating structure of the manufacture based on panel of present invention description.Multiple semiconductor chips are provided, the semiconductor chip includes being arranged in the copper post above the active surface of each semiconductor chip.Embedded chip panel is formed by surrounding each arrangement sealant in the multiple semiconductor chip.Measure actual position and the rotation of each semiconductor chip in the embedded chip panel.Unit specific pattern is formed to be aligned with the actual position of each semiconductor chip in the embedded chip panel.The unit specific pattern is arranged in the semiconductor chip top, sealant top as fan-out structure and is coupled to the copper post.Fan-in redistributing layer (RDL) can extend above the active surface of each semiconductor chip, so that forming the copper post above the fan-in RDL.The unit specific pattern may be coupled directly to the copper post.

Description

Semiconductor devices and the self adaptive patterned method for board-like encapsulation
Technical field
The disclosure relates generally to semiconductor devices, is more particularly to being used to form the encapsulation of fan-out wafer grade (FOWLP) the self adaptive patterning in the field of board-like encapsulation.
Background technology
Semiconductor devices is prevalent in modern electronic product.Semiconductor devices is in the quantity of electric component and density side There is difference in face.Discrete-semiconductor device generally comprises a type of electric component, such as light emitting diode (LED), small-signal Transistor, resistor, capacitor, inductor and power metal oxide semiconductor field-effect transistor (MOSFET).It is integrated Semiconductor devices generally comprises hundreds of to millions of a electric components.The example of integrated-semiconductor device includes microcontroller, micro- Processor, charge coupling device (CCD), solar cell and Digital Micromirror Device (DMD).
Semiconductor devices performs the function of broad range, such as signal processing, supercomputing, transmitting and reception electromagnetism letter Number, control electronic device, convert sunlight into electric power and for television indicator create visual projection.Semiconductor devices exists In the field of amusement, communication, power conversion, network, computer and the consumer goods.Semiconductor devices exist in Military Application, In aviation, automobile, industrial control unit (ICU) and office equipment.
Semiconductor devices makes full use of the electrical properties of semi-conducting material.The atomic structure of semi-conducting material allows by applying Added electric field or base current manipulate its conductivity by doping process.The step of doping, adds impurities to semiconductor material To manipulate and control the conductivity of semiconductor devices in material.
Semiconductor devices includes active and passive electric structure.Including ambipolar and field-effect transistor active structure control The flowing of electric current processed.By changing the application of doped level and electric field or base current, transistor is conducive to or limits electric current Flowing.Voltage necessary to passive structures including resistor, capacitor and inductor generate the various electric functions of execution and electricity Relationship between stream.Passive and active structure is electrically connected to form circuit, and the circuit makes semiconductor devices be able to carry out height Speed calculates and other useful functions.
Semiconductor devices is usually to be made using two complicated manufacturing process (that is, front end manufacture and back-end manufacturing) It makes, each manufacturing process may relate to hundreds of steps.Front end manufacture is related to forming multiple half on the surface of semiconductor wafer Conductor chip.Each semiconductor chip is usually identical and includes the electricity formed by being electrically connected active and passive component Road.Back-end manufacturing be related to dividing individual semiconductor chip from finished product chip and encapsulate the chip with provide structure support and It is environmentally isolated.Term " semiconductor chip " as used herein refers to the word of both odd number and plural number form, and therefore can be with Refer to both single semiconductor devices and multiple semiconductor devices.
One target of semiconductor manufacturing is to generate smaller semiconductor devices.Smaller device usually consumes less work( Rate has higher performance, and can be produced more efficiently.In addition, smaller semiconductor devices has smaller occupy-place Area, this is desired for smaller end product.Smaller semiconductor chip size can pass through front-end process Improve to realize that there is smaller, more highdensity active and passive component so as to cause semiconductor chip.Backend process can be with Lead to the semiconductor packages with smaller footprints by the way that the improvement with encapsulating material is electrically interconnected.
A kind of method for more effectively producing the back-end processing of the semiconductor devices of encapsulation is using board-like encapsulation, wherein being permitted Multiple semiconductor chip is formed into panel and is handled simultaneously under the level of recombination chip or panel.For encapsulating semiconductor A form of board-like encapsulation of chip is FOWLP.FOWLP is related to " face-down " placement of multiple semiconductor chips or makes partly to lead The active surface of body chip is towards temporary carrier or substrate, such as interim tape carrier.Semiconductor chip and substrate or carrier lead to It crosses sealant (such as epoxy molding compounds) and uses such as compression moulding molded.After molding, carrier glue is removed Band is formed as recombinating with exposure the active surface of multiple semiconductor chips of chip together.Then, on the top of recombination chip Form wafer level chip pantographic encapsulation (WLCSP) accumulation interconnection structure.Then, conductive stud is formed above accumulation interconnection structure Block is attached to recombination chip as ball grid array (BGA), BGA.After BGA is formed, segmentation recombinates chip to be formed individually partly Conductor device or encapsulation.Sometimes, semiconductor chip is shifted during substrate is installed to and also in molded process Period is shifted.The displacement (rotation including semiconductor chip) of semiconductor chip may lead to defective semiconductor packages, The defective semiconductor packages reduces package quality and reliability and also increases encapsulation yield loss.
Invention content
From the point of view of specification, drawings and the claims book, above-mentioned aspect and other aspects, features and advantages are for this The those of ordinary skill in field will be apparent.
Therefore, in one aspect, the present invention is a kind of method for manufacturing semiconductor devices, the method may include：It carries For multiple semiconductor chips, the semiconductor chip includes being arranged in the copper above each active surface in semiconductor chip Column；Embedded chip panel is formed by surrounding each arrangement sealant in semiconductor chip；Measure embedded chip face The actual position of each semiconductor chip in plate；And formed unit specific pattern with it is each in embedded chip panel The actual position alignment of semiconductor chip.
The method for manufacturing semiconductor devices can also include forming embedded chip panel by following operation：It provides and carries Body；Multiple semiconductor chips are mounted on carrier down；And it each in multiple semiconductor chips and surrounds Each copper post arrangement sealant.Method can also include forming embedded chip panel by following operation：Carrier is provided；To be more A semiconductor chip is mounted on carrier up；And each in multiple semiconductor chips and around each copper post Arrange sealant.Method can also include removing carrier with the back side of each semiconductor chip of exposure.Method can also include shape It the fan-in redistributing layer (RDL) that extends above into the active surface in each semiconductor chip and is formed above fan-in RDL Copper post.Method can also be arranged in multiple semiconductor chips tops, sealant top simultaneously including forming the conduct of unit specific pattern And it is coupled to the fan-out structure of copper post.Method can also be used as directly on sealant including forming unit specific pattern and coupling Close the conductive layer of copper post.
On the other hand, the present invention is a kind of method for manufacturing semiconductor devices, the method may include：It provides multiple Semiconductor chip, the semiconductor chip include being arranged in the interconnection structure above the active surface of each semiconductor chip；It is logical It crosses and each arranges sealant in multiple semiconductor chips to form embedded chip panel；Measure embedded chip panel The actual position of interior each semiconductor chip；And formed unit specific pattern with each half in embedded chip panel The actual position alignment of conductor chip.
The method for manufacturing semiconductor devices, which can also include being used as copper post by forming interconnection structure, provides interconnection structure. Method, which can also be included in above each copper post, forms convex block, so that the respective profile pair of convex block and each semiconductor devices It is accurate.Method, which can also include being formed, include each in the semiconductor chip of contact pad and in respective semiconductor chip In each contact pad above form copper post.Method can also be included in each formation in multiple semiconductor chips Before sealant, back coating is formed in the back side of the semiconductor chip.Method can also be included in multiple semiconductors Each back side in chip and arrange the back side in the surface for the sealant arranged around multiple semiconductor chips Coating.Method can also include measuring actual position of each semiconductor chip relative to whole plate benchmark.
On the other hand, the present invention is a kind of method for manufacturing semiconductor devices, the method may include：Offer includes The chip panel of multiple semiconductor chips, the semiconductor chip are included in interconnection structure and embedding sealing agent；Measure chip The actual position of each semiconductor chip in panel；And form the unit spy being aligned with the actual position of each interconnection structure Determine pattern.
The method for manufacturing semiconductor devices can also include forming sealant around semiconductor chip, without in semiconductor core The back side of piece forms sealant, so that the back side of semiconductor chip is exposed relative to sealant.Method can be with Including by from many scheduled unit specific patterns designs selection with it is each true in multiple semiconductor chips The unit specific pattern of position best fit forms unit specific pattern with true with each semiconductor chip in chip panel Real position alignment.Method, which can also be included in above each unit specific pattern, forms convex block, so that convex block is with each partly leading The respective profile alignment of body device.Method, which can also include being used as copper post by forming interconnection structure, provides interconnection structure. Method can also include forming unit specific pattern as conductive layer；Polybenzoxazoles is formed above unit specific pattern, is gathered The insulating layer of acid imide or epoxy solder mask；Opening is formed in the insulating layer above unit specific pattern to limit bank face grid Lattice array pad；And a lower height of convex block is formed above Land Grid Array pad.
Description of the drawings
Figure 1A shows the top view of recombination chip according to the embodiment.
Figure 1B to Fig. 1 D shows the multiple encapsulation or module according to an embodiment of the present disclosure for being arranged in and recombinating in chip Top view.
Fig. 2A shows the top view of FOWLP according to an embodiment of the present disclosure.
Fig. 2 B show the cross-sectional side view of FOWLP according to an embodiment of the present disclosure.
Fig. 3 A show the encapsulation chip according to an embodiment of the present disclosure with the x-y position different from nominal reference position Physical location top view.
Fig. 3 B show the encapsulation chip according to an embodiment of the present disclosure with the orientation different from nominal reference orientation The top view of physical location.
Fig. 4 shows RDL patterns according to an embodiment of the present disclosure.
Fig. 5 A show a part for panel design according to an embodiment of the present disclosure.
Fig. 5 B show the chip unit of misalignment according to an embodiment of the present disclosure.
Fig. 6 shows multiple discrete different designs options according to an embodiment of the present disclosure.
Fig. 7 shows self adaptive patterning system according to an embodiment of the present disclosure.
Fig. 8 shows the method figure of the embodiment of self adaptive patterning method.
Fig. 9 shows the method figure of the embodiment of self adaptive patterning method.
Figure 10 A to Figure 10 C show multiple semiconductor chips according to an embodiment of the present disclosure in FOWLP.
Figure 11 A to Figure 11 H show that the cross-sectional side according to an embodiment of the present disclosure being used to form in the method for FOWLP regards Figure.
Figure 12 A to figure 12 C shows multiple semiconductor chips according to an embodiment of the present disclosure in FOWLP.
Figure 13 A to Figure 13 H show that the cross-sectional side according to an embodiment of the present disclosure being used to form in the method for FOWLP regards Figure.
Figure 14 shows the embodiment of FOWLP according to an embodiment of the present disclosure.
Figure 15 shows the embodiment of FOWLP according to an embodiment of the present disclosure.
Figure 16 shows the embodiment of FOWLP according to an embodiment of the present disclosure.
Figure 17 shows the embodiment of FOWLP according to an embodiment of the present disclosure.
Figure 18 shows the embodiment of FOWLP according to an embodiment of the present disclosure.
Figure 19 shows the embodiment of FOWLP according to an embodiment of the present disclosure.
Figure 20 shows the embodiment of FOWLP according to an embodiment of the present disclosure.
Figure 21 shows the embodiment of FOWLP according to an embodiment of the present disclosure.
Figure 22 shows the embodiment of FOWLP according to an embodiment of the present disclosure.
Specific embodiment
Embodiment of the disclosure discloses the method and system for improving board-like encapsulation.In accordance with an embodiment of the present disclosure, face The misalignment of individual device cell in plate or netted chip can be adjusted by the following method：It measures each individual The misalignment of device cell, and adjusted using maskless patterning techniques for the stack layer of each respective device cell In feature position or design.
In the following description, many specific details, specific configuration, composition and technique etc. are set forth, in order to provide Thorough understanding of the disclosure.In other instances, well-known technique and manufacturing technology are not yet described in particular detail, with Exempt from unnecessarily to obscure the disclosure.In addition, various embodiments shown in figure are illustrative expressions and are not necessarily drawn to scale.
As used herein term " ... top ", " ... between ", " ... on " refer to one layer relative to other layers Relative position.Depositing or be arranged in one above or below another layer layer directly can contact or can have with this another layer One or more middle layers.One layer for depositing or being arranged in interlayer can be contacted directly with this two layers or can be had in one or more Interbed.In comparison, the second layer " on " first layer contacted with the second layer.
In accordance with an embodiment of the present disclosure, it can assemble and mold multiple device cells to generate panel or netted chip.Device Part unit can be active device unit such as tube core, and can also be passive device unit such as integrating passive network or discrete Passive device unit such as capacitor, resistor or inductor.Do not require pre-packaged although having no, device cell can be into Row is pre-packaged.According to an embodiment of the invention, pre-packaged part can include single or multiple device cells and other component.It checks Panel is to measure the actual position of each device cell in panel.For example, absolute fix can be included from each device list Member at least one feature relative to the whole plate benchmark on panel x-y position and/or orientation.Then, based on for each each From individual device cell absolute fix create for the unit specific pattern of each individual device cell, and by institute Unit specific pattern is stated to be supplied to laser, write direct imaging system or other maskless patterning systems.Then, multiple Each top in device cell forms unit specific pattern, so that each unit specific pattern and respective device cell pair It is accurate.
In one embodiment, the step of creating pattern is related to adjusting in chip pantographic encapsulation (CSP) packed structures The position of unit minutiae patterns is designed to be aligned with the absolute fix of each device cell in panel.In one embodiment In, unit minutiae patterns for can it is associated with RDL or can not first through hole pattern associated with RDL, capture pad or Interconnection traces pattern.For example, the position of first through hole pattern can be adjusted, so that first through hole pattern is formed and panel In each device cell absolute fix alignment.In addition, the RDL layer of at least one capture pad including being used for first through hole It can be adjusted or designed to maintain to be aligned with the actual position of each device cell in panel.It can be relative to device list (UBM) metallurgical under final convex block and BGA balls are formed in the case of the absolute fix misalignment of member.Therefore, UBM pads and BGA balls It can be aligned always relative to the encapsulation profile of each device cell, so as to maintain and encapsulate the consistency of profile.
Self adaptive patterning can also be utilized to create multiple module specific patterns on entire panel.According to the disclosure Embodiment, can assemble and mold multiple device cells and optionally other component to generate panel or netted chip.Other portions Part can be that optical element, connector (for example, for being connected to the outside of module) and other electronic units, these components also may be used With pre-packaged.In one embodiment, module includes multiple device cells.Module can also include at least one device cell With another component.It checks and includes the multiple of multiple device cells or at least one device cell and at least one additional component The panel of arrangement, to measure the actual position of each device cell and optional other component in panel.For example, absolute fix It can be including each device cell in module and at least one feature of optional other component relative on panel The x-y position and/or orientation of whole plate benchmark.Then, based on to each respective individual device cell in respective module The module specific pattern for each module is created with optional other component absolute fix, and by the module specific pattern Case is supplied to laser, writes direct imaging system or other maskless patterning systems.Then, in multiple device cells Module specific pattern is formed above each and optional other component, so that each module specific pattern and respective module device Part unit and the alignment of optional other component.
As previously discussed with respect to described by individual devices unit encapsulation embodiment, the step of creation module specific pattern, can be related to Adjust CSP packed structures in unit or component detail pattern position or design so as to each device cell in panel or The absolute fix alignment of component.In the presence of multiple devices and optional other component, it is understood that there may be can be with RDL phases Association can not device interconnection trace associated with RDL.Multilayer packed structures can be used for module and individual devices Both encapsulation.
Referring to figure Figure 1A, in one embodiment, technique is started with panel 102, and panel 102 is included with encapsulating material 106 Multiple device cells 104 of (such as epoxy resin) molded.Although Figure 1A shows round panel 102, can also make With replacement panel-form, such as rectangle or rectangular.As shown in Figure 13 D, the active surfaces of multiple device cells 104 substantially with Encapsulating material 106 flushes.In one embodiment, panel 102 can be the panel for being known as recombinating chip in the art, recombinate Chip is formed by WLP technologies, in the art, multiple device cells is placed in downwards in interim tape carrier, are then passed through Epoxy molding plastic is overmolded using compressing and forming process, then removes interim tape carrier with the multiple tube core unit of exposure Active surface.
Then, can form packed structures on the top of shown structure in figure 1A, and device cell be divided with Form encapsulation or module.For example, as shown in fig. 1b, panel can be divided into multiple single-chip packages 150, each wrapper Include single semiconductor chip unit 152.Referring to Fig. 1 C, multiple chip units 152,154 can be mounted in molded plate, and The chip unit is divided to form multi-chip package or module 150.Referring to Fig. 1 D, can by one single chip unit 152 or Multiple chip units 152,154 are mounted in molded plate, which is added to passive device 156 (such as capacitor, inductor Or resistor) and/or other component 158 (such as optical element, connector or other electronic units), and by the chip list Member is divided to form encapsulation or the module 150 including active device and passive device and/or other component.According to the reality of the disclosure Apply example, it is contemplated that the multiple combinations of active and passive device and optionally other component in encapsulation or module.Therefore, Figure 1B It is illustrative and unrestricted to the specific configuration meaning shown in Fig. 1 D.
In the following discussion, some embodiments are described with reference to the formation of single-chip FOWLP, but embodiment of the disclosure It is without being limited thereto.Embodiment of the disclosure can be used for any board-like package application, including single-chip application, multi-chip module, mould In block certain of chip and passive component combination or module in certain of device cell and other component combination.A side Face, embodiment of the disclosure can be eliminated or reduce during the jigsaw caused by the misalignment of device cell or other component Encapsulation or the yield loss of module.On the other hand, embodiment of the disclosure can be maintained and be encapsulated or module wheel It is wide consistent, and do not need to change the position of UBM pads or BGA balls.Remain permissible with the step encapsulated or module profile is consistent It consistently realizes in the final product, for example, as final products encapsulation, socket for inspection etc..On the other hand, this public affairs The embodiment opened can allow the bond pad openings smaller on device cell.
Referring now to Fig. 2A to Fig. 2 B, ball grid array (BGA) ball 108 is attached, and independent to be formed with saw segmentation panel Encapsulation.CSP layer reinforced structures 110 can be formed on the active surface of each tube core unit before it is split.Although by Fig. 2 B In packed structures 110 be shown as including single dielectric layer 115, but it is to be understood that can using multiple layers come be formed accumulation Structure 110.Packed structures 110 can be formed by dielectric material 115, include in the packed structures connecing with chip unit 152 Close the first through hole 112 that pad 105 is in electrical contact.RDL 114 is formed, which can cross in bond pad 105, first Below through-hole 112 and above UBM through-holes 116, UBM pads 119 and BGA balls 108.BGA balls 108 are shown as welding in fig. 2b Ball, but not limited to this.It in other embodiments, may or may not be relevant more with RDL according to the principles described herein formation A dielectric layer and device interconnection trace.Such multilayer layer reinforced structure, which can be not only used for single die package application, can be used for Multi-core Module.
It has been observed that chip unit is placed and molded may cause in multiple chip units 152 that any one is facing When tape carrier on orientation be subjected to displacement and/or rotate.This is attributable to tube core unit and is not attached to interim adhesive tape load strictly Body and moulding compound are shunk during mold compound curing.Therefore, multiple chip units 152 on panel 102 may compress It is not at after molding in its nominal reference position.As shown in Figure 13 D, the physical location of chip unit 152 can have and core X-y positions different the nominal reference position 152' of blade unit.As shown in Figure 13 D, the physical location of chip unit 152 can be with Rotation, so that it has the orientation θ different from the nominal reference of nominal reference position 152' orientation θ '.Although in Fig. 3 A extremely X-y position and orientation are shown relative to the nominal reference position of the chip unit in the encapsulation profile individually divided in Fig. 3 B Difference, it should be appreciated that the difference of x-y position and orientation can essentially be measured about the whole plate benchmark in panel or netted chip It is different.
The packaging part that each tube core unit misalignment can cause some then to divide from panel is defective.For in panel Formed CSP packed structures conventional method utilize based on the patterning techniques of mask with simultaneously on multiple chip units of panel Exposure pattern.Mask includes the fixed pattern to UBM interconnection pieces for chip bonding pad, and therefore lacks each chip of adjustment and exist The ability of movement in board-like form.The influence of conventional method is attributed to caused by the misalignment of first through hole and bond pad Yield loss or the addition with certain intermediate form of the chip bonding pad of primary wafer format change circuit (before jigsaw), So that larger chip pad ensures that although chip is mobile and first through hole still provides for connecting as target.Therefore, at conventional Reason technology needs bond pad on chip unit to be more than to avoid bond pad necessary to the yield loss from panel, by This reduces the application space for WLP technologies.
In accordance with an embodiment of the present disclosure, by using self adaptive patterning techniques to the misalignment of individual chip unit into Row adjustment, in addition which implements maskless lithography, so that the pattern features of packed structures 110.Laser Ablation and direct write exposure are the examples of suitable maskless patterning techniques according to an embodiment of the present disclosure.
In one embodiment, as shown in Figure 1A, the panel for including multiple chip units is provided.Measure the multiple of panel Each actual position in chip unit 152.It can be the specific spy formed on each chip unit of panel to measure The measurement of sign.For example, the position of at least one bond pad 105 on each in multiple chip units on panel can be measured It puts.Specific position can be a variety of positions, such as the corner of bond pad 105, the center of bond pad, bond pad profile Deng.It can include the x-y position and/or orientation relative to the whole plate benchmark on panel in position measurement.It can utilize any suitable The checking tool (such as optical inspection tools) of conjunction measures true first position.In one embodiment, single feature is measured To obtain the x-y position of chip unit.In one embodiment, multiple features are measured to obtain the orientation of chip unit.
Packed structures 110 are formed in above the panel including multiple chip units.Referring again to Fig. 2 B, with the accumulation of completion Structure 110 shows segmented encapsulation.Although packed structures 110 are shown as being formed in above single package in fig. 2b, It should be understood that packed structures 110 are to be formed before it is split, and the shape on entire panel 102 of multiple packed structures 110 Into, and each top being formed in respective multiple chip units 152 on the panel 102 shown in Figure 1A.
In one embodiment, packed structures 110 are formed by dielectric material 115, and the feature of the dielectric material is by pattern Change.Packed structures 110 can include multiple layers.For example, individual dielectric layer can be formed, wherein independently forming first through hole 112nd, RDL patterns 114 and UBM through-holes 116 and/or UBM pads 119.In one embodiment, there may be multiple through-holes and The patterned layers of RDL.Dielectric material 115 can be that opaque or translucent and different material can be used for individually Dielectric layer.In the case where dielectric material 115 is opaque, surveyed before dielectric material 115 can be formed above low-level image feature The optical measurement of measure feature.Translucent in dielectric material 115, it is possible to above panel formed dielectric material it Position that is preceding or measuring the feature below dielectric material 115 later.
Based on each true absolute fix in respective chip unit, for each establishment in multiple chip units Specific pattern.For each in respective chip unit, pattern is that unit is specific, and therefore for each respective core Blade unit, unit specific pattern can different (for example, x-y position, orientation, designs) so that each unit specific pattern with Each respective chip unit alignment, thereby compensates for the misalignment of individual chip unit.Each unit specific pattern can be The common patterns being aligned with respective chip unit.In accordance with an embodiment of the present disclosure, each chip unit uniqueness can also be directed to Ground creates each unit specific pattern.
Then, each top in multiple chip units forms pattern.In one embodiment, pattern is is formed in heap Bond pad 105 is such as connected to first through hole 112, the RDL of RDL patterns 114 by the unit minutiae patterns in product structure 110 Pattern 114 or UBM welding disk patterns 119.As shown in Figure 4, the RDL patterns 114 of Fig. 2 B can include being aligned with first through hole 112 First through hole capture pad 118, be directed at UBM through-holes 116 UBM through-holes capture pad 120 and connect capture pad 121st, 120 trace parts 122.The patterned spy in packed structures 110 can be formed using maskless patterning system Sign.For example, can by write direct by the exposure of photosensitive type polymer or photoresist come generate first through hole 112 or RDL patterns 114.Can also first through hole 112 or RDL patterns 114 be generated by the laser ablation of dielectric material 115.
Based on each absolute fix in respective chip unit, it is contemplated that for creating in multiple chip units Many methods of each pattern.In one embodiment, this situation can be by will be each in multiple chip units Absolute fix and the nominal reference position of many definition are compared to realize.It for example, can be relative to the whole plate on panel 102 Benchmark defines the nominal reference position of at least one feature on each in multiple chip units.Certain nominal reference position Can be a variety of positions, such as corner of bond pad 105, the center of bond pad, the profile of bond pad, alignment characteristics Deng.Certain nominal reference position can also be encapsulation profile, and chip unit will be encapsulated in the encapsulation profile.It can make With multiple features of each unit, so as to the orientation of the chip in determination unit.In nominal reference position can include relative to The x-y position and/or orientation of whole plate benchmark on panel.In one embodiment, the step of defining nominal reference position includes Generate electronic panel figure.For example, the nominal reference position of each chip unit that can be defined in electronic panel figure in panel (x-y position and/or orientation).However, embodiment is not required for panel figure, and nominal reference position can be provided elsewhere.
In one embodiment, adjust the pattern of each chip unit position or design so as to it is respective in panel The absolute fix alignment of chip unit.Based on each absolute fix in the chip unit in panel, design software can be created It builds for each design in multiple chip units.Then, this design can be stored in panel design document In, the x-y position and/or orientation of adjustment pattern in the panel design document.Pattern can also be changed and be used for each with optimizing The design of chip unit.Panel design document can be transmitted to maskless patterning system to form at least unit specific pattern Case.
Fig. 5 A show a part for panel design according to an embodiment of the present disclosure.Explanation provided in Fig. 5 A means It is the demonstration of panel design according to an embodiment of the present disclosure, and is not intended to limit.As shown in the figure, show individual envelope The upper left corner of piece installing profile, it being understood, however, that panel design may include the additional or less letter of single tube core packaging part Breath, and panel design may include the analog information of each tube core unit in multiple tube core units of panel.
Panel design can define the nominal reference position of each chip in panel and wait the mark of feature to be formed Claim reference position.In one embodiment, the nominal reference position of chip 152' and bond pad 105' are defined.Not yet The feature formed above panel can include first through hole 112', chip through-hole capture pad 118', UBM through-hole 116', UBM Through-hole captures pad 120', RDL pattern traces 122', UBM pad 119' and needs the encapsulation wheel for the encapsulation divided from panel The nominal reference position of wide 130'.
Fig. 5 B show the chip unit of misalignment according to an embodiment of the present disclosure.As shown in the figure, chip unit 152 is shown Go out for relative to the whole plate benchmark misalignment on nominal reference chip unit position 152' or panel (not shown).Similarly, The chip bonding pad 105 of formation is shown as relative to the whole plate on nominal reference chip unit position 105' or panel (not shown) Benchmark misalignment.
In one embodiment, the nominal reference position of at least one feature on each in multiple chip units is defined It puts.For example, nominal reference position can be chip bonding pad 105'.For each in multiple chip units on panel, measurement The actual position of die bond pad 105.In accordance with an embodiment of the present disclosure, when the absolute fix of die bond pad 105 has When the x-y position different from the reference position of die bond pad 105' or orientation, the misalignment of individual chip unit is determined.
In one embodiment, formed in CSP packed structures 110 patterned feature (for example, first through hole 112, Chip through-hole capture pad 118, UBM through-holes 116, UBM through-holes capture pad 120, RDL pattern traces 122) position have with For the different x-y position in the nominal reference position of the feature of at least one of multiple chip units or orientation.In a reality Apply in example, compared with for the reference position of the first through hole 112' of at least one of multiple chip units, formed One through-hole 112 has different x-y positions.In one embodiment, with the RDL at least one of multiple chip units The reference position of pattern 114' is compared, and the RDL patterns 114 formed have different x-y positions.In one embodiment, with Reference position for the RDL patterns 114' of at least one of multiple chip units is compared, and the RDL patterns 114 formed have There are different x-y positions and orientation.
In one embodiment, misalignment of the chip unit in terms of x-y directions and/or orientation is measured by checking tool Amount, and at least one of multiple chip units are directed to, between the nominal reference position of computing chip unit and absolute fix δ values.Based on δ values, pattern to be formed is created by the way that pattern is adjusted identical δ values from its reference position.However, root According to embodiment of the disclosure, it is contemplated that patterned feature may may not must be formed with identical δ values.
The other embodiment of the disclosure can maintain the opposite alignment of certain features in final encapsulation.It is shown in figure 5B In embodiment, it is illustrated in being aligned relatively and institute in Fig. 5 A between first through hole 112 and bond pad 105 and chip unit 152 Show nominal reference post-11.2 ', opposite between 105', 152' be aligned it is identical.In one embodiment, RDL patterns 114 Part 118,122,120 in any one or entire RDL patterns 114 in figure 5B can be true the of bond pad 105 Identical δ values are displaced between one position and reference bondpads position 105'.
In one embodiment, each top that can be in multiple chip units forms additional feature, without considering Each absolute fix in respective multiple chip units.In accordance with an embodiment of the present disclosure, UBM pads 119 are formed in nominally At the 119' of reference position, without considering each absolute fix in respective multiple chip units.Shown reality in figure 5B It applies in example, the position of the physical location of UBM pads 119 and encapsulation profile 130 and corresponding nominal reference position 108', 130' phase Together.As shown in the figure, physical location UBM through-holes 116 can also be in the position as nominal reference position 116'.
The position of unit minutiae patterns formed in CSP packed structures is adjusted with the actual measurement with each chip in panel The step of position alignment, can also include changing RDL designs.In one embodiment, the step of changing RDL designs Including selecting best fit RDL designs from multiple discrete different designs options.There is provided in figure 6 it is multiple it is discrete not With the diagram of design option.6. for example, each quadrant I-IX represents the absolute fix and reference bondpads in bond pad 105 A series of δ values between the 105' of position.For example, if δ values correspond to the point 240 in Fig. 6, selection is used for the RDL of quadrant VI Design.If δ values correspond to the point 142 in Fig. 6, selection is used for the RDL patterns of quadrant IX.In this way, it designs Tool can automatically generate the given best fit for this certain chip based on the corresponding δ values of each individual chip Pattern.For example, from quadrant dependence connection different designs pattern in each can have for RDL patterns different sizes, Shape and/or orientation.Although Fig. 6 shows nine different designs options, it should be appreciated that any number can be used discrete not Same design option.
In one embodiment, adjust the position of unit minutiae patterns that is formed in CSP packed structures with in panel Each chip absolute fix alignment the step of include with dynamic design approach change RDL designs.For example, based on each The corresponding δ values of certain chip unit can dynamically generate the customization RDL patterns for each certain chip unit.
In the application, in accordance with an embodiment of the present disclosure, it is contemplated that several variations.For example, adjustment is in CSP packed structures The mode of the unit minutiae patterns of middle formation can depend on that unit minutiae patterns is made to be directed at institute with the respective chip in panel The adjustment amount needed.In first order operation in the case where δ values are minimum, it is contemplated that the adjustment of 112 position of first through hole may foot With the misalignment of compensation chips 152.In the first variation, if the first through hole capture pad 118' of reference no longer with after adjustment 112 position of first through hole be fully overlapped, then may need to make all or part of adjustment and first of 114 position of RDL patterns 112 position of through-hole is adjusted identical δ values.In the second variation, the adjustment in 114 position of RDL patterns is inadequate, The design of RDL patterns 114 can be changed, so that first through hole capture pad 118 is aligned, and UBM leads to first through hole 112 Hole capture pad 120 is aligned with UBM through-holes 116.This can be selected by the position based on the δ values in the quadrant shown in Fig. 6 It selects and is designed for the best fit of each RDL patterns 114 in respective chip unit to realize or by dynamically setting Meter is realized for the customization RDL patterns 114 of each chip unit.
As described above, packed structures can be made using self adaptive patterning techniques according to an embodiment of the present disclosure Feature (such as first through hole 112 and RDL patterns 114) patterning in 100.In one embodiment, self adaptive patterning skill Art can be used for any structure in packed structures.For example, packed structures can include multiple layers, through-hole and RDL patterns.One In a embodiment, self adaptive patterning techniques can include the measurement of the first actual position, be first through hole and RDL-1 later Self adaptive patterning, followed by the measurement of the second actual position, are through-hole -2 and the self adaptive patterning of RDL-2 later, then It is the measurement of actual position ' n ', is the self adaptive patterning of through-hole-n and RDL-n later.
In accordance with an embodiment of the present disclosure, many chip packages can be divided from panel or netted chip.Many chips Encapsulation can be characterized by unique scope of statistics of relative orientation.In common process, multiple chips on entire panel not In the case of alignment, the first through hole 112 of many chip packages is relative to the misalignment of respective 152 profile of chip whole Assembly average on a many chip packages is with chip 152 relative to the statistical average of the misalignment of encapsulation profile 130 It is worth directly proportional.These relationships can be expressed as below：
Δ(avg,lot)(112,152)≈Δ(avg,lot)(152,130)
In accordance with an embodiment of the present disclosure, it is respective to compensate that each individually chip adjustment first through hole 112 can be directed to The misalignment of chip 152.Therefore, first through hole 112 relative to the misalignment of respective 152 profile of chip in the entire many Assembly average on chip package is significantly less than chip 152 relative to the assembly average of the misalignment of encapsulation profile 130.This A little relationships can be expressed as below：
Δ(avg,lot)(112,152)<<Δ(avg,lot)(152,130)
In one embodiment, first through hole 112 is permitted relative to the misalignment of respective 152 profile of chip entirely described Assembly average on multi-chip package is zero.
Δ(avg,lot)(112,152)=0
Some embodiments may be implemented as computer program product, and the computer program product can include being stored in Instruction on permanent machine readable media.These instructions can be used for being programmed to carry out the behaviour to general or specialized processor Make.Machine readable media includes the information for storage or transmission machine (for example, computer) readable form (for example, software, place Ought to use) any mechanism.Machine readable media can include but is not limited to magnetic-based storage media (for example, floppy disk)；Optics Storage medium (for example, CD-ROM)；Magnetic-optical storage medium；Read-only memory (ROM)；Random access memory (RAM)；It is erasable Programmable storage (for example, EPROM and EEPROM)；Flash memory；Or it is suitable for storing another type of e-command Medium.
In addition, some embodiments can be implemented in distributed computer environment, wherein machine readable media is stored in not Only performed in a computer system and/or by more than one computer system.Furthermore it is possible in the whole of connection computer system The information transmitted between computer systems is pulled or pushed on a communication media.
Digital processing device described herein can include one or more general-purpose processing devices, such as microprocessor or Central processing unit, controller etc..Alternatively, Digital processing device can include one or more dedicated processes devices, it is all in full Word signal processor (DSP), application-specific integrated circuit (ASIC), field programmable gate array (FPGA) etc..In alternative embodiments, For example, Digital processing device can be network processing unit, which, which has, includes core cell and multiple micro engines Multiple processors.In addition, Digital processing device can include any combinations of general-purpose processing device and dedicated processes device.
Embodiment of the disclosure can be performed with self adaptive patterning system 160 as shown in Figure 7.Operation can be by Hardware component, software, firmware or combination perform.Appoint whichever in the signal provided by a variety of buses 162 as described herein It can be transmitted together with other signals by time-division multiplex and pass through one or more common buses and provided.As shown in the figure, it can incite somebody to action Panel or netted chip 164 are supplied to checking tool 166, and checking tool 166 measures the position of multiple device cells on panel And create the file 168 for including each absolute fix in multiple device cells.Subsequently, based in multiple device cells Each absolute fix is stored in the design software on server 176 and creates for each pattern in multiple device cells Design document 170.It patterns the input design of machine 172 and each top in multiple device cells is formed through pattern The feature of change.Patterning machine 172 is supplied to from checking tool 166 by panel or netted chip.It can be from patterning machine 172 The panel 174 of output pattern.
In one embodiment, design software also creates at least one layer of the new figure for design, which is adjusted So that first through hole and/or RDL patterns are aligned with each absolute fix in multiple device cells.In one embodiment, Software is included for self adaptive patterned algorithm.For example, algorithm can adjust the x-y position or orientation of feature based on δ values. In one embodiment, algorithm can select characteristic pattern based on δ values from several discrete design options.In one embodiment In, algorithm can be based on δ values dynamically design feature.
Schematic diagram provided in Fig. 7 indicates the order of technique according to an embodiment of the present disclosure, however, physical device is not Must as described as arrangement.As shown in the figure, design software is stored on individual server 176, individual server 176 also may be used Include the panel figure of the nominal reference position of multiple device cells on panel with storage.It is not required for design software and is stored in list On only server 176.For example, design software can be stored on checking tool 166 or patterning machine 172.It it is possible that will All components are integrated into individual system.
Any part of self adaptive patterning system 160 or entire self adaptive pattern can be controlled using server 176 Change system 160.In one embodiment, server 176 includes being stored with the memory 179 of instruction above, described instruction by Processor 178 perform when make processor instruction checking tool 166 come measure each position in multiple device cells of panel, It is created based on each absolute fix in respective device cell for each list in respective multiple device cells First specific pattern, and indicate that each top of the patterned tool 172 in multiple device cells forms unit specific pattern, In each unit specific pattern be aligned with respective device cell.In one embodiment, based in respective device cell Each absolute fix can wrap to create for the step of each unit specific pattern in respective multiple device cells The x-y position for adjusting at least one unit specific pattern and/or orientation are included, selects or moves from several discrete design options Generate to state unit specific pattern.
Method provided in Fig. 9 illustrates the specific embodiment of self adaptive patterning method 180, the method includes： Measure each position (step 182) in multiple device cells of panel；It defines on each in multiple device cells extremely The reference position of a few feature, wherein compared with the reference position of at least one of multiple device cells, absolute fix tool There are different x-y positions or orientation (step 186)；By processor based on each absolute fix in respective device cell It creates for each unit specific pattern in respective multiple device cells, the unit specific pattern includes through-hole figure Case, capture at least one of pad and interconnection traces pattern (step 188), the foundation step are come real by following operation It is existing：It calculates the δ values between each absolute fix and reference position in respective multiple device cells and makes unit specific The position of pattern adjusts identical δ from the reference position of the unit specific pattern at least one of multiple device cells Value；The position of the unit specific pattern of each top in respective device cell is defined on, wherein with respective device cell In each reference position compare, the unit specific pattern created have different x-y positions or orientation (step 190)； And each top in respective device cell forms unit specific pattern, wherein each unit specific pattern with it is respective Device cell is directed at (step 192).In particular implementation, create for each unit specific pattern in respective device cell The step of case, based on each absolute fix in respective device cell including being created for respective multiple device cells In each module specific pattern；And each top in multiple device cells the step of forming unit specific pattern, wraps The each top included in multiple device cells forms module specific pattern, wherein each module specific pattern and respective module Interior respective at least two device cell alignment.In particular implementation, method can optionally include measuring the multiple of panel Each position in other component, other component are selected from by optical element, connector and electronic unit (step 184).Method It may be implemented as with the permanent computer readable storage medium for being stored in instruction above, described instruction is by processor Processor is made to perform self adaptive patterning method operation during execution.
Method provided in Fig. 9 illustrates the specific embodiment of self adaptive patterning method 200, the method includes： Generate the nominal semiconductor chip panel design (step 201) for being used to form FOWLP；Semiconductor chip of the manufacture with exposure connects Touch the embedded semiconductor chip panel (step 202) of pad；Measure each semiconductor in embedded semiconductor chip panel The actual position of chip and orientation (step 204)；Position of semiconductor chip data are input to self adaptive pattern automatic router In (step 206)；Create for each semiconductor chip on embedded semiconductor chip panel self adaptive through-hole and/or RDL pattern (steps 208)；Output includes the panel design (step 210) of each self adaptive through-hole and/or RDL patterns；It and will Self adaptive through-hole and/or RDL patterns are applied to embedded semiconductor chip panel (step 212).Method may be implemented as having There is the permanent computer readable storage medium for being stored in instruction above, described instruction makes processor when executed by the processor Perform self adaptive patterning method operation.
Figure 10 A show with for structure support basal substrate material 222 (such as, but not limited to silicon, germanium, GaAs, Indium phosphide or silicon carbide) semiconductor wafer 220.Multiple semiconductor chips or component 224 are formed on the wafer 220, are stablized , the wafer area of chip chamber or saw street 226 separate, as described above.Saw street 226 provides cutting region will partly lead Body chip 220 is divided into individual semiconductor chip 224.
Figure 10 B show the cross-sectional view of a part for semiconductor wafer 220.Each semiconductor chip 224 have the back side or Back surface 228 and the active surface 230 opposite with the back side.Active surface 230 includes analog or digital circuit, and the circuit is by reality It applies and forms the active device, passive device, the conductive layer that in the chip and are electrically interconnected for the electrical design according to chip and function And dielectric layer.For example, circuit can include one or more transistors, diode and other being formed in active surface 230 Circuit element is to implement analog circuit or digital circuit, such as DSP, ASIC, memory or other signal processing circuits.Semiconductor Chip 224 can also include the integrated passive devices (IPD) for RF signal processings, such as inductor, capacitor and resistor. In one embodiment, semiconductor chip 224 is flip-chip-type device.
Using PVD, CVD, electrolysis plating, electrodeless plating technique or other suitable metal deposition process in active surface 230 tops form conductive layer 232.Conductive layer 232 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other are suitable Conductive material.Contact pad or bond pad of the operation of conductive layer 232 to be electrically connected to the circuit on active surface 230.It is conductive Layer 232 can be formed as the contact pad being arranged side by side with a distance from the edge of semiconductor chip 224 first, as shown in figure 12a. Alternatively, conductive layer 232 can be formed as contact pad, the contact pad is deviated with multirow so that the first row contact pad The edge for being arranged to off-chip piece is the first distance, and be arranged to off-chip piece with the alternate second row contact pad of the first row Edge be second distance.
In fig 1 oc, semiconductor wafer 220 is subjected to carrying out optional grinding operation so that surface is put down using grinder 234 Face and the thickness for reducing semiconductor wafer.Chemical etching can be used for removing semiconductor wafer 220 and make its flat Change.Using saw blade or laser cutting tool 236, by saw street 226, semiconductor wafer 220 is divided into and is individually partly led Body chip 224.
Figure 11 A show comprising for structure support interim or sacrificial substrate material (such as silicon, polymer, beryllium oxide or Other suitable low cost, rigid materials) carrier or substrate 240.Optional boundary layer or double faced adhesive tape 242 are used as temporary bond Film or etching stopping layer are formed in 240 top of carrier.In one embodiment, boundary layer 242 is permanently attached to semiconductor core Piece 224 and the part for forming final FOWLP, are such as more fully described in U.S. Patent Publication No.2011/0198762, Disclosure disclosed in the patent is hereby incorporated herein by.Many fiducial alignment marks 243 be located in substrate 240 or 242 top of boundary layer is attached to substrate 240 or boundary layer 242.Alternatively, a part for substrate 240 or boundary layer 242 is removed Or it indicates to form benchmark 243.Benchmark 243 allows the orientation of the subsequent installation progress substrate 240 relative to semiconductor chip 224 And processing.
Figure 11 A, which are also illustrated, to be installed to carrier 240 and boundary layer 242 by the semiconductor chip 224 of Figure 10 C and makes active surface 230 are orientated towards substrate.Semiconductor is positioned relative to benchmark 243 according to the nominal or scheduled position of semiconductor chip and spacing Chip 224.Nominal position for the selection of each semiconductor chip 224 is confirmed as advantageously forming each semiconductor chip 224 FOWLP nominal or scheduled panel design a part.Nominal panel is designed as being formed the fan of each semiconductor chip 224 Go out to accumulate the segmentation in interconnection structure and final FOWLP and enough spaces are provided.Therefore, Figure 11 A are shown such as from benchmark 243 240 top of substrate is installed or be arranged in the first semiconductor chip 224 at the reference point R1 of measurement, reference point R1 corresponds to nominal The position of the first semiconductor chip in panel design.Similarly, in the reference point R2 such as measured from one or more benchmark 243 The top of substrate 240 is installed or be arranged in second semiconductor chip 224 by place, and reference point R2 corresponds to the in the design of nominal panel The position of two semiconductor chips.
Semiconductor chip 224 is separated when above substrate 240 by space or gap 244.Gap 244 provides and is used for What is subsequently formed is fanned out to the region of interconnection structure.The size in gap 244 is to design to be determined according to nominal panel, and will The FOWLP formed around each semiconductor 224 provides enough spaces.Gap 244 further includes optionally to install semiconductor Enough regions of device or component 246.Semiconductor devices 246 is mounted to the boundary layer 242 between semiconductor chip 224 With carrier 240, and by for from recombination the subsequent dividing semiconductor 224 of chip enough spaces are provided in a manner of be positioned in gap In 244.Semiconductor devices 246 includes discrete device, distributed elements or with the passive device 156 shown in Fig. 1 D (including electricity Sensor, capacitor and resistor) similar passive device.
Figure 11 B are shown using creme printing, compression molding, transfer modling, fluid sealant molding, vacuum lamination, spin coating Or other suitable applicators deposit sealant 250.Specifically, Figure 11 B show the mould with multiple imports 254 and 256 Tool 252, makes the mold flock together with carrier 240 and boundary layer 242 and is used so that semiconductor chip 224 is enclosed in mold In subsequent encapsulation.It is moved moulds by surrounding semiconductor chip 224 and 252 or is moved to alternatively by by semiconductor chip In mold, mold 252 is made to flock together.Mold 252 includes flock together with carrier 240 and boundary layer 242 only first Part or top section, without the second mould part or bottom mold portion.Carrier 240 and boundary layer 242 serve as with The bottom mold portion of packaging technology afterwards.Alternatively, semiconductor chip 224, carrier 240 and boundary layer 242 can be arranged in packet In the mold for including multiple portions (such as top and bottom part).
Figure 11 B also illustrate that the cavity of mold 252 or open space 258 close semiconductor chip 224.Cavity 258 is in mold Extend between 252 and semiconductor chip 224 and boundary layer 242.At high temperature and pressure by import 254 by the close of certain volume Agent 250 is sealed to inject in cavity 258 and above semiconductor chip 224 and carrier 240 from distributor 260.Import 256 can be Exhaust outlet, the exhaust outlet have the optional vacuum aided facility 262 for extra sealant 250.Sealant 250 can be Polymer composites, such as epoxy resin with filler, the epoxy acrylate with filler or with properly filling out Fill the polymer of object.It is subtracted according to the space requirement of cavity 258 occupied by semiconductor chip 224 and semiconductor devices 246 Region measures the volume of sealant 250.Sealant 250 is evenly dispersed and is evenly distributed on around semiconductor core at high temperature In the cavity 258 of piece 224.The viscosity of sealant 250 is selected for uniform fold, for example, relatively low viscosity increases for mould The flowing of the sealant of modeling, creme printing and spin coating.Semiconductor chip 224 is embedded in together in sealant 250, sealant 366 is non-conductive, and protects semiconductor devices from outer member and pollutant effects in the environment.
In Figure 11 C, from 252 removing semiconductor chip 224 of mold.Pass through chemical etching, mechanical stripping, CMP, mechanical grinding Mill, hot bakings, UV light, laser scanning or wet stripping remove carrier 240 and boundary layer 242, to expose opposite with surface 268 The surface 266 of sealant 250.The surface 266 of sealant 250 and the active surface 230 of semiconductor chip 224 and contact pad 232 is substantially coplanar, wherein each being exposed by removing carrier 240 and boundary layer 242.Therefore, above with reference to Figure 10 A to figure The described techniques of 10C and Figure 11 A to Figure 11 C provide the additional details about the processing step 202 shown in Fig. 9.It is moving After carrier 240 and boundary layer 242, it is embedded to be formed around semiconductor chip 224 that Figure 11 C show that sealant 250 is arranged in Chip panel 270.Panel 270 includes the footprints or form factor of any shape and size, the footprints or waveform Factor allows and advantageously forms the subsequent processing needed for FOWLP, as described in more detail below.In one embodiment, Panel 270 includes the form factor similar with the form factor of 300 millimeters of (mm) semiconductor wafers, and including with a diameter of The round footprints of 300mm.
Figure 11 C also illustrate scanner 274, and the scanner 274 is for inspection panel 270 with partly leading in determining panel 270 The true or physical location of body chip 224.Scanner 274 using optical imagery, acoustics imaging, magnetic imaging, radio frequency, Infrared ray or other suitable processes determine the true or physical location of semiconductor chip 224 or other objects (including panel Optional semiconductor devices 246 in 270) true or physical location.Determine that each semiconductor chip 224 or other objects are opposite Actual position and rotation in the global reference point R3 on panel 270.Reference point R3 is included with forming sealant 250 and removing Many benchmark 243 that substrate 240 and boundary layer 242 transmit simultaneously from substrate 240.Reference point R3 further includes many new benchmark pair Fiducial mark remembers that the fiducial alignment mark is located in 270 top of panel or is attached to panel 270 or close by indicating or removing It seals a part for agent 250 and is formed.Alternatively, reference point R3 is not identified as a part for panel 270 physically, but with sweeping Retouching a part for device 274 or the attachment point of scanner 274 is associated.
Scanner 274 checks the feature on each semiconductor chip 224 to determine each semiconductor chip in panel 270 Physical location and rotation relative to reference point R3.Know another characteristic by the scanner 274 on each semiconductor chip 224 to include The position at edge or the corner of semiconductor chip, position (corner, center or wheel including contact pad of contact pad 232 It is wide) or semiconductor core on piece or any other feature associated with semiconductor chip.The reality or reality of semiconductor chip 224 Location is put including x-y position, which considers in semiconductor chip relative to the one or more of the reference point R3 in panel 270 Transverse direction or translation displacement on direction.Similarly, the reality of semiconductor chip 224 or absolute fix are further included relative to reference point Orientation or the angle rotation of R3.
As shown in Figure 13 D, the first semiconductor chip 224 is encapsulated in panel 270 and is located relative to reference point R3 is come at the reference point R4 that measures.Similarly, the second semiconductor chip 224 is in the reference point R5 measured relative to reference point R3 Place is encapsulated in panel 270.When semiconductor chip 224 is precisely and accurately placed at reference point R1 and R2 and half When conductor chip does not suffer from any movement or displacement in encapsulation process, R1 and R2 are respectively equal to R4 and R5.However, semiconductor core The movement for the nominal position that piece 124 is designed from predetermined panel causes reference point R4 and R5 to be different from reference point R1 and R2.Half Movement of the conductor chip 224 far from its nominal position and reference point R3 is by installing semiconductor chip not above substrate 240 Caused by accuracy.In addition, the movement of semiconductor chip 124 is also the position of the semiconductor chip by occurring in encapsulation process Displacement caused by.For example, 224 phase of semiconductor chip may be led to by contacting the power that semiconductor chip 224 generates by sealant 250 For reference point R3 shift, and relative to predetermined panel design in semiconductor chip nominal position (that is, reference point R1 and R2 it) shifts.Therefore, it is provided above with reference to the described techniques of Figure 11 C about the additional of the processing step 204 shown in Fig. 9 Details.
As indicated by the step 206 in Fig. 9, each semiconductor chip in panel 270 is being determined by scanner 274 After 224 actual position and orientation, by half in the actual position (such as R4 and R5) of semiconductor chip and the design of nominal panel The nominal position of conductor chip compares (see, for example, the step 201) in R1 and R2 and Fig. 9, to determine in processing procedure The change in location of each semiconductor chip 224 occurred or displacement.By the nominal or original design for determining semiconductor chip 224 The difference of position between position and the physical location of semiconductor chip can identify and avoid square on the semiconductor subsequently form It is fanned out to the potential problems of accumulation interconnection structure.If the actual position (such as R4 and R5) of semiconductor chip 224 shifted so as to So that the actual position of the contact pad 232 of semiconductor core on piece is fanned out to accumulation mutually by what is be no longer aligned with or provide and subsequently form Link the good electrical connection of structure, then there are potential problems.Accumulation interconnection structure is fanned out to as be initially designed to panel 270 It will not be aligned with certain semiconductor chips 224, because the accumulation interconnection structure as initial design is based in panel design The nominal position (such as R1 and R2) of semiconductor chip rather than the semiconductor chip after the part for having been formed as panel 270 224 reality or actual position (such as R4 and R5).Therefore, at least part for being fanned out to the original design of accumulation interconnection structure exists It is applied to and is modified to avoid misalignment between interconnection structure and semiconductor chip 224 before panel 270 and insufficient is electrically connected The problem of connecing.In one embodiment, self adaptive pattern will be input to about the position data of semiconductor chip 224 to route automatically In device, self adaptive pattern automatic router is shown as the part of self adaptive patterning system 160 in the step 166 of Fig. 7.Cause This, self adaptive patterning system 160 considers the true of semiconductor chip 224 or measures position and generate new design, adjusts Whole or selection is fanned out to the new position of at least part (for example, through-hole, RDL, pad and trace) of accumulation interconnection structure, with even It is connected to the contact pad 232 of semiconductor chip 224.Referring also to the step 168 in the step 208 in Fig. 9 and Fig. 7 and 170.Individually Encapsulation design be combined to form the drawing for needing each complete panel in the layer that adjusts.See, for example, in Fig. 9 Step 210.It is complete to be formed that the difference of displacement from nominal position to actual position indicates how to combine individually encapsulation design Panel design.In one embodiment, litho machine will be input to for the design document of each panel, the litho machine uses The self adaptive pattern of customization is dynamically applied to each panel by design data.See, for example, the step 212 in Fig. 9.
In Figure 11 D, by deposit and pattern insulation or passivation layer 280 will be fanned out to accumulation interconnection structure first part It is formed in 270 top of panel.Alternatively, as indicated above, after substrate 240 is removed, boundary layer 242 remains attached to panel 270 To serve as the first part for being fanned out to accumulation interconnection structure, and as a part of final FOWLP.Insulating layer 280 conformally applies Sealant 250 and semiconductor chip 224 are layed onto, and with the first of the profile for following sealant 250 and semiconductor chip 224 Surface.Insulating layer 280 has second flat surface opposite with first surface.Insulating layer 280 includes the photosensitive low of one or more layers Solidification temperature dielectric resist, photosensitive compounds resist, lamination compound film, insulation paste, solder with filler are covered Mould resist film, liquid molding compound, silica (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminium oxide (Al2O3) or the other materials with similar insulation and structural property.Using printing, spin coating, spraying, lamination or other are suitable Technique carry out depositing insulating layer 280.Insulating layer 280 is then patterned and optionally cures.
A part for insulating layer 280 is removed with shape by etching, laser drill, machine drilling or other suitable techniques Into opening 282.Opening 282 extends fully through the contact pad 232 of insulating layer 280 and exposure semiconductor chip 224.When half Conductor chip 224 relative to the variation of the position of reference point R3 it is smaller when, it may not be necessary to opening 282 position be adjusted with Opening is properly aligned with contact pad 232.Therefore, for the self adaptive patterned step of packaged semiconductor 224 Whether the displacement or movement of actual position and determining semiconductor chip including measurement semiconductor chip 224 need opening 282 Position variation.If the variation of the position of contact pad 232 is so that the nominal position of opening 282 does not provide and contact pad Come into full contact with, then by carry out to opening 282 position adjustment.
Self adaptive patterning can individually adjust the position of each opening 282 or adjust the position of many openings 282 simultaneously It puts.For example, many openings 282 form the unit pattern related with the single semiconductor chip 224 in panel 270, these openings It is typically adjusted together as unit.It is single by x-y shift or the rotation by the angle, θ relative to the reference point R3 on panel 270 Solely or in groups adjust the position of opening 282.For example, by x-y shift or by according to the semiconductor chip in panel 270 The rotation of the angle, θ of the actual position (such as being measured relative to reference point R3) of 224a, the first part of adjustment opening 282 (is scheming Opening 282a is designated as in 11D).Similarly, by x-y shift or by according to the semiconductor chip 224b in panel 270 Actual position (such as relative to reference point R3 measure) angle, θ rotation, the second part of adjustment opening 282 is (in Figure 11 D It is designated as opening 282b).As needed, for each semiconductor chip 224 in panel 270, the adaptive of opening 282 occurs Property patterning.In one embodiment, opening 282, the proprietary design tool modification are formed using proprietary design tool Or the fan out unit each encapsulated the design on adjustment panel, so that the conductive through hole being subsequently formed in opening 282 is with connecing Pad 232 is touched to be properly aligned with.When opening 282 is smaller relative to the variation of the position of reference point R3, it may not be necessary to accumulation Interconnection structure carries out additional adjustment.Alternatively, other than changing the position of opening 282, also change accumulation interconnection layer other Partial nominal position, as described in more detail below.
In Figure 11 E, using PVD, CVD, plating, electrodeless plating or other suitable techniques are electrolysed by conductive layer deposition To form conductive through hole 288 in opening 282.Conductive through hole 288 can be one or more layers Al, Cu, Sn, Ni, Au, Ag, Titanium (Ti), tungsten (W), polysilicon or other suitable conductive materials.Conductive through hole 288 formed accumulation interconnection structure part and Be electrically connected vertical with contact pad 232 is provided.
Figure 11 E also illustrate that conductive layer 290 is patterned and is deposited on insulating layer 280 and the top of conductive layer 288.Conductive layer 290 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials.The deposition of conductive layer 290 makes With PVD, CVD, electrolysis plating, electrodeless plating or other suitable techniques.In one embodiment, conductive layer 290 and conduction Layer 288 is formed together at the same time.Alternatively, conductive layer 288 and 290 is formed as a part for individual technique, and The different times are formed.Conductive layer 290 can be formed with 114 similar modes of RDL shown in Fig. 2 B and Fig. 4.Figure 11 F It is the plan view of a part for conductive layer 290, it is logical that conductive layer 290 includes first through hole capture pad 292, trace 294 and second Hole captures pad 296.First through hole capture pad 292 is similar to first through hole and captures pad 118, and be arranged in insulating layer 280 and the top of conductive through hole 288.Conductive layer 290 also includes the trace 294 similar to trace parts 122, and trace 294 is formed in The second through-hole capture pad 296, the capture of the second through-hole are extended to above insulating layer 280 and from first through hole capture pad 292 Pad 296 is similar to UBM through-holes and captures pad 120.Second through-hole captures the trace parts 294 of 296 contact conductive layer 290 of pad It is and opposite with first through hole capture pad 292.In one embodiment, trace 294 includes being respectively smaller than first through hole capture The width of the width of 292 and second through-hole of pad capture pad 296.
As indicated above, when semiconductor chip 224, opening 282 and conductive through hole 288 are relative to the position of reference point R3 Variation it is smaller when, it may not be necessary to additional adjustment is carried out to accumulation interconnection structure (including to conductive layer 290).Therefore, it is used for The self adaptive patterned step that encapsulation is formed in the semiconductor chip 224 in panel 270 includes measuring semiconductor chip 224 Actual position, the displacement for determining semiconductor chip mobile do not need to the pattern of conductive layer 290 or the variation of design and formerly At the preceding position determined relative to panel 270 and reference point R3 formed conductive layer 290, that is, not to semiconductor chip 224 relative to The variation of the position of reference point R3 is adjusted.Alternatively, if the variation of the position of opening 282 is so that first through hole capture weldering The nominal position of disk 292 does not provide to be come into full contact with conductive through hole 288, then conductive layer 290 will be adjusted.
In a particular embodiment, the region of first through hole capture pad 292 or footprints are extended, so that their cloth It puts above conductive through hole 288, is consequently adapted to the position of conductive through hole 288 relative to the displacement of static RDL patterns.In other words It says, the position of conductive layer 290 is formed according to the nominal or planned position relative to reference point R3, without the figure to conductive layer 290 Case or layout are translated or rotation displacement.Conductive through hole 288 is adjusted by increasing the region of first through hole capture pad 292 Actual position the step of mean first through hole capture pad 292 geometric center 298 position relative to reference point R3 come It is formed and is not dependent on conductive through hole 288 or the absolute fix of the geometric center 300 of conductive through hole 288.Therefore, in some feelings Under condition, the center 298 of first through hole capture pad 292 will deviate from the center 300 of through-hole 288.However, first through hole captures pad 292 increased size provides enough regions to contact the entirety on the surface of conductive through hole 288, and in conductive through hole and the Good electrical connection is provided between one through-hole capture pad.Increase the size of capture pad 292 or the method in region can be used for making In application with larger pad spacing.Larger pad pitch applications have foot between adjacent through-hole capture pad 292 Enough spaces, so that after increasing in the region of first through hole capture pad, there are enough skies between widened pad Between or gap to prevent contact, bridge joint or the short circuit between pad.At the center 298 for not adjusting first through hole capture pad 292 Position in the case of the step of expanding the region of the pad be not suitable for fine pad pitch applications, this can cause first logical Contact, bridge joint or short circuit between eyelet welding disk.
In another embodiment, the self adaptive patterned step of conductive layer 290 does not need to increase first through hole capture weldering 292 and second through-hole of disk captures the size of pad 296.On the contrary, the size of conductive layer 290, spacing and design are (including the first contact The size of 292 and second contact pad 296 of pad) it remains unchanged, and according to before the displacement for measuring semiconductor chip 224 The original or nominal design of determining conductive layer 290 is formed.By using x-y shift or the angle, θ relative to reference point R3 Rotation adjust the actual position of semiconductor chip 224 so that with each 224 associated conductive layer 290 of semiconductor chip Integral shift, for each actual position of semiconductor chip 224, the size, spacing and design for making conductive layer 290 are self adaptive Pattern.As needed, the conduction of the self adaptive patterning of conductive layer 290 and each semiconductor chip 224 in panel 270 Through-hole 288 occurs together.For example, by x-y shift or pass through the actual position according to the semiconductor chip 224a in panel 270 The rotation of the angle, θ of (such as being measured relative to reference point R3), the first part of adjustment conductive layer 290 (are designated as in Figure 11 E Conductive layer 290a).Similarly, by x-y shift or pass through the actual position according to the semiconductor chip 224b in panel 270 The rotation of the angle, θ of (such as being measured relative to reference point R3), the second part of adjustment conductive layer 290 (are designated as in Figure 11 E Conductive layer 290b).Therefore, by adjusting the position of the conductive layer 290 of each semiconductor chip 224, conductive layer 290 and panel The true or physical location alignment of semiconductor chip 224 in 270.Further it is provided that contact pad 232, conductive through hole 288 and leading Therefore good connection between electric layer 290 is suitable for fine pitch applications without increasing the region of through-hole capture pad.
Due to the orientation or displacement of the conductive layer 290 that cause each semiconductor chip 224, by semiconductor chip 224 The offset generated relative to the difference between the outer peripheral nominal position and actual position of the FOWLP of completion is transferred or shifts To the second through-hole capture pad 296 and the interconnection (such as the second through-hole, UBM or another suitable interconnection structure) subsequently formed Between interface or interconnection.It is desirable that the position of UBM patterns or other suitable interconnection structures remains unchanged, and not opposite In the edge displacement of encapsulation.Therefore, if entire RDL patterns or conductive layer 290 are relative to fixed UBM or interconnection pattern Displacement then can capture the size of pad by increasing the bottom on RDL layer or UBM is connected to the logical of RDL layer by reducing The diameter in hole adapts to the displacement of conductive layer 290.However so that the orientation of the conductive layer 290 of each semiconductor chip 224 or position The step of putting displacement is not suited well for multi-chip module, and plurality of semiconductor chip or component are relative to each other same Unit designs internal shift, and including the different rotation relative to panel 270 and reference point R3 and/or x-y shift.For only With single RDL, fan-in or the FOWLP for being fanned out to routing layer, the alignment for accumulating covering problem and layer in interconnection structure is moved To next via layer in UBM bottoms.Advantageously, covering problem can be displaced to by the accumulation interconnection structure with multiple RDL Additional RDL layer or region in encapsulation with larger spacing and less strict pitch requirements, are thus more easily adapted to conform to The displacement of the position of semiconductor chip 224.
As set forth above, it is possible to using for adjust the position of conductive layer 290 with the semiconductor chip 224 in panel 270 The alignment of true or physical location different methods.In a preferred embodiment, position and base based on semiconductor element 224 It is associated with each semiconductor element 224 in the position of the final interconnection structure of each FOWLP (position of such as conductive bump) Each unit specific pattern of conductive layer 290 can be unique and individually designed.By calculating for 290 He of conductive layer For the unique or complete customization RDL patterns of each semiconductor chip 224 in panel 270, can realize lead The position of electric layer 290 and the increased flexibility of each semiconductor chip 224 and the location matches of final interconnection structure.This side Method is it is possible that solve semiconductor chip 224, the company of conductive layer 290 and the final interconnection structure or UBM that subsequently form between the two It connects, without influencing covering design rule.When the position for conductive layer 290 creates complete customization RDL layer or design, for true Determining the algorithm completely designed of each semiconductor chip 224 in panel 270 may become complicated and may increase reliable Replicate the difficulty of conductive layer 290 in ground.The complexity of conductive layer 290 is with the complete formation for customizing RDL patterns and passes through figure Case (including such as feature of inductor, high-power planar and big ground plane) and increase.
For adjusting the position of conductive layer 290 so as to the true or physical location with the semiconductor chip 224 in panel 270 Another method of alignment, which is included in initial design process, generates several general patterns of discrete fixation.Each general pattern The subset shifted suitable for the possible chip limited by the processing capacity of board-splicing process.Therefore, based on every in panel 270 The true or absolute fix of a semiconductor chip 224 can select " best fit " from several general patterns of discrete fixation Pattern and it is made to be matched with the particular semiconductor chip in panel.See, for example, Fig. 6 and related text.In this way, face The best fit pattern of each semiconductor chip 224 in plate 270 can be rotated based on the actual measurement of each semiconductor chip 224 And/or x-y shift (δ values), the RDL patterns without calculating the unique of each semiconductor chip or customization.
Figure shows the cross-sectional view of insulation or passivation layer 304, insulation or passivation layer from Figure 11 E and Figure 11 F Figure 11 G continued 304 are conformally coated to insulating layer 280 and conductive layer 290, and with the profile for following insulating layer 280 and conductive layer 290 First surface.Insulating layer 304 has second flat surface opposite with first surface.Insulating layer 304 includes one or more layers light Quick low solidification temperature dielectric resist, photosensitive compounds resist, lamination compound film, the insulation paste with filler, weldering Expect mask resist film, liquid molding compound, SiO2, Si3N4, SiON, Al2O3 or there is similar insulation and structural property Other materials.Carry out depositing insulating layer 304 using printing, spin coating, spraying, lamination or other suitable techniques.Insulating layer 304 with After be patterned and optionally cure.
A part for insulating layer 304 is removed with shape by etching, laser drill, machine drilling or other suitable techniques Into opening, the opening extends fully through a part for insulating layer 304 and exposure conductive layer 290, and such as the second through-hole is caught Obtain pad 296.Using PVD, CVD, electrolysis plating, electrodeless plating or other suitable techniques by conductive layer deposition in insulating layer To form conductive through hole 306 in opening in 304.Conductive through hole 306 can be one or more layers Al, Cu, Sn, Ni, Au, Ag, Ti, W, polysilicon or other suitable conductive materials.Conductive through hole 306 forms the part of accumulation interconnection structure and offer Relative to the vertical electrical connection of contact pad 232, conductive through hole 288 and conductive layer 290.
In one embodiment, the position of conductive through hole 306 is formed in it relative to the nominal of reference point R3 and panel 270 At position, and it is aligned with the second through-hole capture pad 296.It is right that conductive through hole 306 can capture pad 296 with the second through-hole Standard, this is because semiconductor chip 224 and conductive layer 290 are smaller or because most relative to the displacement of reference point R3 and panel 270 Pipe conductive layer 290 is shifted to match semiconductor chip 224, but through-hole capture pad 296 is extended so that conductive through hole 306 Good electrical contact is carried out with the second through-hole capture pad 296.Alternatively, the position of conductive through hole 306 can be from its nominal position By the self adaptive new or actual position adjusted to match 290 and second through-hole of conductive layer capture pad 296.Conductive through hole 306 Self adaptive patterning can also include adjust or reduce conductive through hole diameter, therefore ensure that conductive through hole 306 and conductive layer Good and complete connection between 290 and the UBM layer or interconnection structure that subsequently form.The reduction of conductive through hole 306 it is straight Diameter allows more movements of the position of 290 and second through-hole of conductive layer capture pad 296, while ensures conductive through hole 306 Footprints are completely in the footprints of 290 or second through-hole of conductive layer capture pad 296.
Figure 11 H are shown similar to the UBM 310 of the UBM pads 119 in Fig. 2 B, and UBM 310 is formed in 306 He of conductive through hole 304 top of insulating layer.UBM 310 can be multiple metal laminated, including adhesive layer, barrier layer, Seed Layer and wetting layer.UBM 310 layer can be Ti, titanium nitride (TiN), TiW, Al, Cu, chromium (Cr), chromium-copper (CrCu), Ni, nickel vanadium (NiV), Pd, platinum (Pt), Au and Ag.In one embodiment, UBM 310 includes TiW Seed Layers, Cu Seed Layers and Cu UBM layers.TiW Seed Layers Conformally it is coated in 306 top of insulating layer 304 and conductive through hole.Cu Seed Layers are conformally coated in above TiW Seed Layers.Cu UBM layer is conformally coated in above TiW Seed Layers and Cu Seed Layers.UBM 310 serves as conductive through hole 306 and the weldering subsequently formed Expect the intermediate conductive layer between convex block or other I/O interconnection structures.UBM 310 can provide the low resistance with conductive through hole 306 It interconnects, to the blocking of solder diffusion and the increase of solder wettability.
Using evaporation, plating, electrodeless plating, globule (ball drop) or silk-screen printing technique are electrolysed by conductive bump Material is deposited on 306 top of UBM 310 and conductive through hole.Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder And a combination thereof, together with optional flux solution.For example, bump material can be eutectic Sn/Pb, high kupper solder or Pb-free coating Material.Bump material is attached to UBM 310 using suitable attachment or bonding process.In one embodiment, by by convex block Material is heated to that bump material reflux more than its fusing point is made to form spherical ball or convex block 312.In some applications, convex block 312 by secondary back to be improved to the electrical contact of UBM 310.Convex block can also be attached to UBM 310 by compression.312 table of convex block The a type of interconnection structure of 310 tops of UBM can be formed in by showing.Interconnection structure can also use conductive paste, cylindricality convex Block, dimpling block or other electrical interconnections.
Figure 11 H are also shown in be formed after convex block 312, divide panel or recombination using saw blade or laser cutting tool 316 Chip 270 is to form individual FOWLP 318.Because for the semiconductor chip 224 in panel 270 movement not to convex block 312 carry out self adaptive adjustment and convex block 312 according to its nominal design location come formed (see, for example, the step 201) in Fig. 9, So convex block 312 is aligned with the periphery of FOWLP 318 or outer package profile.
Therefore, the method that Figure 11 A to Figure 11 H show manufacture FOWLP 318, wherein making first through hole layer and RDL routing layer At least part from it, nominal position is shifted and is aligned with the actual position with each semiconductor chip on the wafer.Pass through this Sample is done, and is at least encapsulated I/O interconnection and is kept being aligned to meet encapsulation profile diagram with the edge of final package, is conducive to packaging and testing, And eliminate yield loss of the jigsaw in the process caused by the misalignment of semiconductor chip.Self adaptive patterned implementation Can using programmable direct write exposure and laser ablation methods with allow the position of adjustment through-hole and RDL layer and orientation come with panel Each individual semiconductor chip alignment in 270.Other than increasing yield rate, the technique proposed also corrects for chip solid Movement during change, and therefore realize the geometry of smaller die bond pad and increased density.
Figure 12 A are shown similar to the cross section of a part for the semiconductor wafer 330 of the semiconductor wafer 220 in Figure 11 A Figure.Semiconductor wafer 330 includes the basal substrate material 332 for structure support, such as silicon, germanium, GaAs, indium phosphide or carbon SiClx.Multiple semiconductor chips or component 334 are formed on chip 330, by stable, chip chamber wafer area or scribing street Area 336 separates, as described above.Saw street 336 provides cutting region so that semiconductor wafer 330 is divided into individual semiconductor Chip 334.Similar to the semiconductor chip 224 shown in Figure 10 A and the device cell 104 shown in Figure 1A is similar to, half Conductor chip 334 is disposed on entire semiconductor wafer 330.
Figure 12 A also illustrate that each semiconductor chip 334 has the back side or back surface 338 and the active surface opposite with the back side 340.Active surface 340 includes analog or digital circuit, and the circuit is implemented as according to the electrical design of chip and function shape Into in the chip and be electrically interconnected active device, passive device, conductive layer and dielectric layer.For example, circuit can include one Or multiple transistors, diode and other circuit elements for being formed in active surface 340 are to implement analog circuit or number electricity Road, such as DSP, ASIC, memory or other signal processing circuits.Semiconductor chip 334 can also be included at RF signals The IPD of reason, such as inductor, capacitor and resistor.
Using PVD, CVD, electrolysis plating, electrodeless plating technique or other suitable metal deposition process in active surface 340 tops form conductive layer 342.Conductive layer 342 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other are suitable Conductive material.Contact pad or bond pad of the operation of conductive layer 342 to be electrically connected to the circuit on active surface 340.It is conductive Layer 342 can be formed as the contact pad being arranged side by side with a distance from the edge of semiconductor chip 334 first, as shown in figure 12a. Alternatively, conductive layer 342 can be formed as contact pad, the contact pad is deviated with multirow so that the first row contact pad The edge for being arranged to off-chip piece is the first distance, and be arranged to off-chip piece with the alternate second row contact pad of the first row Edge be second distance.
Semiconductor wafer 330 can also be subjected to optional grinding operation so that back surface planarizes and reduces semiconductor The thickness of chip.Similarly, optional chemical etching can be used for removing semiconductor wafer 330 and make semiconductor wafer 330 Planarization.Since chip 330 includes required thickness, optional back side painting is formed above the back side of semiconductor chip 334 338 Layer 344.Back coating 344 is polymeric layer, dielectric film, epoxy resin film or has its of similar insulation and structural property His suitable material, the back coating can include one or more layers SiO2, Si3N4, SiON, tantalum pentoxide (Ta2O5), Al2O3, polyimides, benzocyclobutene (BCB) and polybenzoxazoles (PBO).Back coating 344 can pass through layer Pressure technique, moulding technology or other suitable techniques are formed.Alternatively, optional back coating 344 is omitted, so that the back side 338 keep exposure as a part for final encapsulation or keep exposing subsequently to encapsulate.In another embodiment, the back side applies Layer 344 be one or more layers Heat Conduction Material, such as Al, Cu, Ni, Cu and Ni or by such as printing, PVD, CVD, sputtering, Be electrolysed the technique formation of plating, electrodeless plating, metal evaporation, metal sputtering or other suitable techniques has high thermal conductivity Other suitable materials of rate.Heat conductive backside coating 344 forms thermally conductive pathways, which helps to be distributed and dissipate by half The hot property of FOWLP that the heat and increase that conductor chip 332 generates subsequently form.Although back coating 344 shows in fig. 12 Go out to be formed on the back side 338 of the chip before semiconductor wafer 330 is divided into individual semiconductor chip, still Back coating 344 can also be formed in upon splitting on individual semiconductor chip 334.
Figure 12 B are shown without the semiconductor wafer 330 of optional back coating 344, however can also be there are back side paintings It is performed in the case of layer 344 in subsequent process and structure shown in figure.Figure 12 B, which are also illustrated, is conformally coated in active surface The insulation of 342 top of 340 tops and conductive layer or passivation layer 346.Insulating layer 346 includes the use of PVD, CVD, silk-screen printing, rotation It applies, spray, one or more layers that sintering or thermal oxide coat.Insulating layer 346 include one or more layers SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimides, BCB, PBO or the other materials with similar insulation and structural property.At one In embodiment, passivation layer 346 includes being formed in the passivation layer of 340 top of active surface and is formed in passivation layer top and conductive layer The optional polymeric layer of 342 tops.Opening is formed completely through insulating layer 346, to expose conductive layer 342 at least A part is for subsequent electrical connection.Alternatively, because insulating layer 346 is optional, in the feelings for not forming insulating layer Exposure conductive layer 342 is for subsequent electrical interconnection under condition.
It is electrically interconnected or copper post, pillar or column 348 is formed in 342 top of conductive layer, and be connected to conductive layer 342.Make With patterning and metal deposition process, such as printing, PVD, CVD, sputtering, electrolysis plating, electrodeless plating, metal evaporation, gold Belong to sputtering or other suitable metal deposition process, interconnection 348 can be formed directly on conductive layer 342.Being electrically interconnected 348 can To be one or more layers Al, Cu, Sn, Ni, Au, Ag, palladium (Pd) or other suitable conductive materials, and one can be included Or multiple UBM layers.In one embodiment, photoresist layer is deposited on 342 top of semiconductor chip 334 and conductive layer.Light A part for resist layer is caused to be exposed and removed by etching developing process.It will be electrically interconnected using selective electroplating technique 348 are formed as copper pillar, column or the column in the part of the removal of photoresist and are formed in 342 top of conductive layer.It is photic Resist layer is removed, and leaves interconnection 348, which provides subsequent electrical interconnection and relative to active surface 340 and insulating layer The bearing of 346 (if present)s.Preferably, interconnection 348 is included in the height H1 in the range of 10-40 microns (μm).More preferably Ground, interconnection 348 are included in the height in the range of 15-25 μm.Most preferably, interconnection 348 includes about 20 μm of height.
After interconnection 348 is formed, using saw blade or laser cutting tool 350, by saw street 336, by semiconductor Chip 330 is divided into individual semiconductor chip 334.
Figure 12 C are shown without optional back coating 344 but with similar to the optional insulation of Figure 12 B or passivation layers 346 semiconductor wafer 330.The difference lies in be added to conductive layer 354 with Figure 12 B by Figure 12 C.Use patterning and metal Depositing operation, such as printing, PVD, CVD, sputtering, electrolysis plating, electrodeless plating, metal evaporation, metal sputtering or other conjunctions Conductive layer or RDL 354 are formed in 342 top of insulating layer 346 and conductive layer by suitable metal deposition process.Conductive layer 354 can To be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials.In one embodiment, conductive layer 354 be RDL, including titanium tungsten (TiW) Seed Layer, Cu Seed Layers and the Cu being formed in above TiW Seed Layers and Cu Seed Layers Layer.Conductive layer 354 follows conductive layer 342 and the profile of insulating layer 346 or semiconductor chip 334.Conductive layer 354 is in conductive layer Power path is provided between 342 part and electrical interconnection or copper post, pillar or column 356.Depending on the semiconductor core installed later The Design and Features of piece, the part of conductive layer 354 can be electric common or be electrically isolated.The operation of conductive layer 354 is fan-in RDL, Fan-in RDL provides additional flexibility when determining and 356 position being electrically interconnected.
Figure 12 C also illustrate electrical interconnection or copper pillar, column or column 356, they are similar to described above for Figure 12 B Interconnection 348.Interconnection 356 and interconnection 348 the difference lies in being formed in conductive layer 354 rather than the top of conductive layer 342, and It is directly connected to conductive layer 354 rather than conductive layer 342.After interconnection 356 is formed, saw blade or laser cutting tool are used 358, by saw street 336, semiconductor wafer 330 is divided into individual semiconductor chip 334.
Figure 13 A show comprising for structure support interim or sacrificial substrate material (such as silicon, polymer, beryllium oxide or Other suitable low cost, rigid materials) carrier or substrate 360.Optional boundary layer or double faced adhesive tape 362 are used as temporary bond Film or etching stopping layer are formed in 360 top of carrier.Many fiducial alignment marks 364 are located on carrier 360 or boundary layer 362 Side is attached to carrier 360 or boundary layer 362.Alternatively, a part for carrier 360 or boundary layer 362 is removed or indicates with shape Into benchmark 364.Benchmark 364 allows the subsequent installation relative to semiconductor chip 334 to be orientated and handled carrier 360.
Figure 13 A are also illustrated to be installed to carrier 360 and boundary layer 362 by the semiconductor chip 334 of Figure 12 C and makes to have down Source surface 340 is orientated towards substrate.Alternatively, the semiconductor chip 334 of Figure 12 B can also be installed to carrier 360 and boundary down Face layer 362 and is subjected to about the described processing of Figure 13 A to Figure 13 H.According to the nominal or scheduled position of semiconductor chip With spacing semiconductor chip 334 is positioned relative to benchmark 364.Nominal position for the selection of each semiconductor chip 334 is true It is set to a part for the nominal or scheduled panel design for the FOWLP for advantageously forming each semiconductor chip 334.Nominal panel The segmentation being fanned out in accumulation interconnection structure and final FOWLP for being designed as being formed each semiconductor chip 334 provides enough Space.Therefore, Figure 13 A show that the first semiconductor chip 334 is installed or arranged at the reference point R6 such as measured from benchmark 364 Above carrier 360, reference point R6 corresponds to the position of the first semiconductor chip in the design of nominal panel.Similarly, such as The second semiconductor chip 334 is installed or is arranged on carrier 360 at the reference point R7 measured from one or more benchmark 364 Side, reference point R7 correspond to the position of the second semiconductor chip in the design of nominal panel.Semiconductor chip 334 is mounted on load It is separated during 360 top of body by space or gap, the space or gap provide region for the interconnection structure that is fanned out to subsequently formed.Between The size of gap is included for optionally enough regions of mounting semiconductor or component in the FOWLP subsequently formed, such as Shown in Figure 11 A.
Figure 13 A also show that printed using creme, compression molding, transfer modling, fluid sealant molding, vacuum lamination, rotation It applies or other suitable applicators deposits sealant 366.Specifically, Figure 13 A show there is multiple imports 370 and 372 Mold 368 makes the mold flock together semiconductor chip 334 being enclosed in mold with carrier 360 and boundary layer 362 For subsequent encapsulation.It is moved moulds by surrounding semiconductor chip 334 and 368 or moved alternatively by by semiconductor chip Into mold, mold 368 is made to flock together.Mold 368 can include what is flocked together with carrier 360 and boundary layer 362 Only first part or top section, without the second mould part or bottom mold portion.In one embodiment, carrier 360 It is served as with boundary layer 362 for the bottom mold portion of subsequent packaging technology.Alternatively, semiconductor chip 334,360 and of carrier Boundary layer 362 can be arranged in the mold including multiple portions (such as top and bottom part).
Figure 13 A also illustrate that the cavity of mold 368 or open space 374 close semiconductor chip 334.Cavity 374 is in mold Extend between 368 and semiconductor chip 334 and boundary layer 362.At high temperature and pressure by import 370 by the close of certain volume Agent 366 is sealed to inject in cavity 374 and above semiconductor chip 334 and carrier 360 from distributor 376.Import 372 can be Exhaust outlet, the exhaust outlet have the optional vacuum aided facility 378 for extra sealant 366.Sealant 366 can be Polymer composites, such as epoxy resin with filler, the epoxy acrylate with filler or with properly filling out Fill the polymer of object.It is subtracted according to the space requirement of cavity 374 by semiconductor chip 334 and that may be present any additional half Conductor device occupied region measures the volume of sealant 366.Sealant 366 is evenly dispersed and uniformly divides at high temperature Cloth is in the cavity 374 around semiconductor chip 334.The viscosity of sealant 366 is selected for uniform fold, for example, relatively low Viscosity increase for molding, creme printing and spin coating sealant flowing.Semiconductor chip 334 is embedded in sealing together In agent 366, sealant 366 is non-conductive, and protects semiconductor devices from outer member and pollutant effects in the environment.
In Figure 13 B, it is shown similar to the packaging technology about the described techniques of Figure 13 A.Figure 13 B and Figure 13 A are not It is orientation of the semiconductor chip 334 relative to carrier 360 and boundary layer 362 with part.Figure 13 B show to install up and partly lead Body chip 334 simultaneously makes embodiment rather than installation is partly led down as shown in FIG. 13A that the back side 338 is orientated towards carrier 360 Body chip 334 simultaneously makes active surface 340 be orientated towards carrier 360.In addition, it although is exemplified with reference to the implementation shown in Figure 13 B The processing then discussed about the encapsulation of semiconductor chip 334, but subsequent processing is equally applicable to shown in Figure 13 A Embodiment.
In Figure 13 C, from 368 removing semiconductor chip 334 of mold.Pass through chemical etching, mechanical stripping, CMP, mechanical grinding Mill, hot baking, UV light, laser scanning or wet stripping remove carrier 360 and boundary layer 362, to expose sealant 366.Sealing The surface of agent 366 can be substantially coplanar with the back side 338, and the back side 338 is exposed by removing carrier 360 and boundary layer 362.Cause This, provides above with reference to figure 12 A to figure 12 C and the described techniques of Figure 13 A to Figure 13 C about similar to the work shown in Fig. 9 The details of the technique of skill.After carrier 360 and boundary layer 362 is removed, Figure 13 C show that sealant 366 is arranged in semiconductor chip To form embedded chip panel 380 around 334.Panel 380 includes the footprints or form factor of any shape and size, The footprints or form factor allow and advantageously form the subsequent processing needed for FOWLP, such as retouch in further detail below It states.In one embodiment, panel 380 includes the form factor similar with the form factor of 300mm semiconductor wafers, and wraps Include the round footprints with a diameter of 300mm.
Figure 13 C also illustrate panel 380 be subjected to carrying out optional grinding operation using grinder 382 so that surface planeization simultaneously And reduce the thickness of panel.Chemical etching can be used for removing a part for sealant 366 and make the part planar.Cause This, interconnects 356 surface and is exposed to semiconductor chip 334 being electrically connected to relative to the sealant 366 in 380 periphery of panel What is subsequently formed is fanned out to interconnection structure.
In Figure 13 C, semiconductor core is formed in similar to the optional back coating 384 of the back coating 344 in Figure 12 A 338 top of the back side of piece 334 and the surface of the sealant 366 substantially coplanar with the back side 338.Back coating 384 is polymerization Nitride layer, dielectric film, epoxy resin film or other suitable materials with similar insulation and structural property, the back side apply Layer can include one or more layers SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimides, BCB and PBO.Back coating 384 can be formed by laminating technology, moulding technology or other suitable techniques.In one embodiment, back coating 384 For optically transparent material, be conducive to object (such as semiconductor chip 334, interconnection 356 and benchmark 364) in panel 380 Optical scanner.In another embodiment, back coating 384 be one or more layers Heat Conduction Material, such as Al, Cu, Ni, Cu and Ni or by such as printing, PVD, CVD, sputtering, electrolysis plating, electrodeless plating, metal evaporation, metal sputtering or other close Other suitable materials with high thermal conductivity that the technique of suitable technique is formed.Heat conductive backside coating 384 forms heat conduction road Diameter, the thermally conductive pathways help to be distributed and dissipate the heat generated by semiconductor chip 334 and FOWLP that increase subsequently forms Hot property.Alternatively, optional back coating 384 is omitted, so that the back side 338 keeps exposing one as final encapsulation Point.Before or after the part for removing sealant 366 from panel, back coating 384 can be formed on panel 380.
Figure 13 D show scanner 386, and the scanner 386 is for inspection panel 380 with the semiconductor in determining panel 380 The true or physical location of chip 334.Scanner 386 uses optical imagery, acoustics imaging, magnetic imaging, radio frequency, red Outside line or other suitable processes determine semiconductor chip 334 or other objects (including being similar to Figure 11 A in panel 380 In semiconductor devices 246 optional semiconductor devices) true or physical location.Determine each semiconductor chip 334 or its His actual position and rotation of the object relative to the global reference point R8 on panel 380.Reference point R8 can include close with formation It seals agent 366 and removes carrier 360 and boundary layer 362 while many benchmark 364 transmitted from carrier 360.Reference point R8 is also wrapped Include many new fiducial alignment marks, the fiducial alignment mark be located in 380 top of panel or be attached to panel 380 or It is formed by indicating or removing a part for panel 380.Alternatively, reference point R8 is not identified as panel 380 physically A part, but the attachment point between a part for scanner 386 or panel 380 and scanner 386 is associated.
Scanner 386 checks the feature on each semiconductor chip 334 to determine each semiconductor chip on panel 380 334 physical location and rotation relative to reference point R8.The spy identified by the scanner 386 on each semiconductor chip 334 Sign include edge position or semiconductor chip corner, interconnection 356 position (corner, center or profile including interconnection), Or semiconductor core on piece or any other feature associated with semiconductor chip.The reality of semiconductor chip 334 or actual measurement position It puts including x-y position, which considers in semiconductor chip relative to one or more directions of the reference point R8 in panel 380 On transverse direction or translation displacement.Similarly, the reality of semiconductor chip 334 or absolute fix also include relative to reference point R8's Orientation or angle rotation.
As shown in Figure 13 D, the first semiconductor chip 334 is encapsulated in panel 380 and is located relative to reference point R8 is come at the reference point R9 that measures.Similarly, the second semiconductor chip 334 is in the reference point measured relative to reference point R8 It is encapsulated at R10 in panel 380.Precisely and accurately be placed at reference point R6 and R7 when semiconductor chip 334 and When semiconductor chip does not suffer from any movement or displacement in encapsulation process, R6 and R7 are respectively equal to R9 and R10.However, it partly leads The movement for the nominal position that body chip 334 is designed from predetermined panel cause reference point R9 and R10 be different from reference point R6 and R7.Movement of the semiconductor chip 334 far from its nominal position and reference point R8 is by installing semiconductor chip above carrier 360 Inaccuracy caused by.In addition, the movement of semiconductor chip 334 is also the semiconductor chip by occurring in encapsulation process Caused by the displacement of position.For example, semiconductor chip may be led to by contacting the power that semiconductor chip 334 generates by sealant 366 334 shift with interconnection 356 relative to reference point R8, and relative to the nominal position of the semiconductor chip in the design of predetermined panel (that is, reference point R6 and R7) is shifted.
Determined by scanner 386 each semiconductor chip 334 in panel 380 and interconnection 356 actual position and After orientation, by the nominal of the semiconductor chip in the design of the actual position (such as R9 and R10) of semiconductor chip and nominal panel (such as R6 and R7) compares for position, to determine the position of each semiconductor chip 334 occurred in processing procedure and interconnection 356 Put variation or displacement.By determining the nominal or original design position of semiconductor chip 334 and semiconductor chip and the reality of interconnection The difference of position between the position of border can be identified and be avoided just to subsequently form on the semiconductor to be fanned out to and accumulate the latent of interconnection structure In problem.If the actual position (such as R9 and R10) of semiconductor chip 334 has been shifted so that interconnecting 356 true position It puts to be no longer aligned with or provide and be electrically connected with accumulation the good of interconnection structure that be fanned out to subsequently formed, then there are potential problems. It will not be with 356 pairs of certain semiconductor chips 334 or interconnection as the accumulation interconnection structure that is fanned out to for being initially designed to panel 380 Standard because the accumulation interconnection structure as initial design be based on panel design in semiconductor chip nominal position (such as R6 and R7) rather than reality or true position of the semiconductor chip 334 with interconnection 356 after the part for having been formed as panel 380 It puts (such as R9 and R10).Therefore, be fanned out to accumulation interconnection structure original design at least part be applied to panel 380 it Before be modified to avoid the problem that misalignment between interconnection structure and semiconductor chip 334 and insufficient be electrically connected.At one In embodiment, the position data of semiconductor chip 334 and interconnection 356 is input in self adaptive pattern automatic router, it is described Self adaptive pattern automatic router considers the true or absolute fix of semiconductor chip 334 and generates new design, described new Design adjustment or select at least part (for example, through-hole, RDL, pad and trace) for being fanned out to accumulation interconnection structure New position, to be connected to the interconnection 356 of semiconductor chip 334.Individually encapsulation design, which is combined to form, needs what is adjusted The drawing of each complete panel in layer.The difference of displacement from nominal position to actual position indicates how that combination is independent Encapsulation design and designed with forming complete panel.In one embodiment, it will be input to for the design document of each panel The self adaptive pattern of customization is dynamically applied to each panel by litho machine, the litho machine using design data.
Figure 13 E show conformally to be coated in the insulation of 356 top of panel 380 and interconnection or passivation layer 388.Insulating layer 388 Include the use of one or more layers of PVD, CVD, silk-screen printing, spin coating, spraying, sintering or thermal oxide coating.Insulating layer 388 includes One or more layers SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimides, BCB, PBO or with similar insulation and knot The other materials of structure property.In one embodiment, passivation layer 388 is optional polymeric layer.Opening is formed fully Across insulating layer 388, to expose at least part of conductive layer 342 for subsequent electrical connection.Alternatively, because insulating layer 388 be optional, so exposure conductive layer 342 is for subsequent electrical interconnection in the case where not forming insulating layer.
In Figure 13 E, insulating layer 388 is removed by etching, laser drill, machine drilling or other suitable techniques A part passes completely through opening of the insulating layer 388 so as to exposure interconnection 356 to be formed.When 356 phases of semiconductor chip 334 and interconnection For the variation of the position of reference point R8 it is smaller when, it may not be necessary to the position of the opening in insulating layer 388 is adjusted with will Opening is properly aligned with interconnection 356.Therefore, include measuring for the self adaptive patterning of packaged semiconductor 334 and partly lead Whether the displacement or movement of body chip 334 or the actual position and determining semiconductor chip of interconnection 356 need insulating layer 388 In opening precalculated position variation.If the variation of the position of interconnection 356 is so that the nominal position of the opening in insulating layer 388 The abundant exposure that interconnection is not provided is put, then the adjustment that will carry out position to the opening in insulating layer.
Self adaptive patterning can individually adjust the position being each open in insulating layer 388 or can adjust simultaneously The position of many openings.For example, many opening formation are related with the interconnection 356 of the single semiconductor chip 334 in panel 380 Unit pattern, these openings are typically adjusted together as unit.As discussed above concerning described by the opening 282 shown in Figure 11 D, individually Ground or the position for adjusting the opening in insulating layer 388 in groups.For example, by x-y shift or by relative on panel 380 The rotation of the angle, θ of reference point R8 adjusts the opening in insulating layer 388.
Figure 13 E also illustrate that conductive layer or RDL 390 are patterned and are deposited on insulating layer 388 and interconnect 356 top conducts It is fanned out to RDL.Conductive layer 390 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials.It is conductive The deposition of layer 390 uses PVD, CVD, electrolysis plating, electrodeless plating or other suitable techniques.In one embodiment, it leads Electric layer 390 is RDL, including TiW Seed Layers, Cu Seed Layers and the Cu being formed in above TiW Seed Layers and Cu Seed Layers Layer.Conductive layer 390 provides electrical interconnection between the convex block or encapsulation interconnection for being electrically interconnected 356 and subsequently forming, described to subsequently form Convex block or encapsulation be interconnected between the point outside semiconductor chip 334 and FOWLP provide electric signal transmission.Work as semiconductor core When piece 334 and interconnection 356 smaller relative to the variation of the position of reference point R8, conductive layer is formed according to nominal or original design 390 may be enough to provide between interconnection 356 and the convex block subsequently formed or encapsulation interconnection to be electrically connected, without additional adjustment Or self adaptive patterning.On the contrary, change enough from nominal position when the absolute fix of semiconductor chip 334 and interconnection 356 so that Forming conductive layer 390 according to its nominal design may cause between interconnection 356 and the convex block subsequently formed or encapsulation interconnection not During good electrical connection, the additional adjustment of conductive layer 390 or self adaptive patterning are needed.
It can be using for adjusting the position of conductive layer 390 with true or real with the semiconductor chip 334 in panel 380 The different methods of border position alignment.First, position based on semiconductor element 334 and based on each FOWLP it is final mutually Link the position (position of such as conductive bump) of structure, each list with each 334 associated conductive layer 390 of semiconductor element First specific pattern can be unique and individually designed.By calculating for each semiconductor chip 334 in panel 380 Unique or complete customization RDL patterns, can realize for by the position of conductive layer 390 and each semiconductor chip 334 and The increased flexibility of the location matches of final interconnection structure.
For adjusting the position of conductive layer 390 with the true or physical location pair with the semiconductor chip 334 in panel 380 Accurate second method includes, by conductive layer of the formation with the first fixed part and the second adaptive part, making conductive layer 390 each unit specific pattern is associated with each semiconductor chip 334.The first part of conductive layer is (also referred to as fixed Local pattern or default layer (prestratum)) relative to the profile of each FOWLP and BGA arrays it is fixed.Conductive layer 390 First part can include for subsequent pattern layer (such as UBM structures) capture pad.After forming the first portion, and And the physical location of semiconductor chip 334 or interconnection 356 and orientation are for example being measured by witness mark R9 and R10 Afterwards, the second part of conductive layer 390 is formed.Formed conductive layer 390 second part, so as to complete the first part of conductive layer with Interconnection 356 and conductive layer 390 are connected to the connection between the position of encapsulation or final interconnection structure (such as solder projection).One In a embodiment, the second part of conductive layer 390 is less than the first part of conductive layer.Preferably dynamically change conductive layer 390 To adapt to the second part of the conductive layer 390 of the variation between the nominal position of semiconductor chip 334 and physical location or adaptive It is typically about 100 μm to 200 μm to answer region.
For adjusting the position of conductive layer 390 with the true or physical location pair with the semiconductor chip 334 in panel 380 The third accurate method is included in several discrete fixation standard drawings generated in initial design process for conductive layer 390 Case.Each general pattern is suitable for the subset shifted by the possible chip that the processing capacity of board-splicing process is limited.Therefore, base It, can be from several discrete fixations in each semiconductor chip 334 in panel 380 and the true or absolute fix of interconnection 356 " best fit " pattern is selected in general pattern and it is made to be matched with the particular semiconductor chip in panel.
Figure 13 E show conformally to be coated in the insulation of 390 top of panel 380 and conductive layer or passivation layer 392.Insulating layer 392 include the use of one or more layers of PVD, CVD, silk-screen printing, spin coating, spraying, sintering or thermal oxide coating.Insulating layer 392 Comprising one or more layers SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimides, BCB, PBO or there is similar insulation With the other materials of structural property.In one embodiment, passivation layer 392 is polymeric layer.
In Figure 13 E, insulating layer 392 is removed by etching, laser drill, machine drilling or other suitable techniques A part with formed pass completely through insulating layer 392 be open and exposure conductive layer 390 at least part for subsequent It is electrically interconnected.The position of opening in insulating layer 392 is formed in relative at the nominal position of outer profile or package edge.It is formed in Opening in insulating layer 392 be not intended to adjustment insulating layer 388 in opening position or adjust conductive layer 390 position from The patterned part of adaptive.It is adjusted in insulating layer 392 by the absolute fix for being not based on semiconductor chip 334 and interconnection 356 The position of opening, encapsulation interconnection (such as solder projection) position remained fixed relative to the outer edge or profile of FOWLP and Do not change with the movement or displacement of semiconductor chip 334.
Figure 13 F are the plan views of a part of embedded chip panel 380 of Figure 13 E before insulating layer 392 is formed.Figure 13F shows the semiconductor chip being embedded in sealant 366 334 and interconnection 356.Insulating layer 388 is optionally formed at semiconductor Chip 334 and the top of sealant 366, wherein opening is formed in 356 top of interconnection, with the design according to semiconductor chip 334 and Function carries out subsequent mechanically and electrically interconnection.As discussed above for Figure 13 E, conductive layer 390 one or many can be formed In one or more parts.Figure 13 F show that the first part of conductive layer 390 or default layer 390a are shown as being arranged in and partly lead The embodiment of 388 top of body chip 334, sealant 366 and insulating layer.The first part 390a of conductive layer 390 can be formed as It is fanned out to RDL layer, and is formed according to the nominal position (such as reference point R6 or R7) of semiconductor chip 334.In an implementation In example, first part 390a is created in traditional layout tool (such as Cadence).Each portion including first part 390a Point position and the optimal design of spacing ensure that interconnection 356 then can be connected to the with enough spaces and acceptable spacing A part of 390a, the problem of without causing such as electric short circuit.In one embodiment, determine that the best of first part 390a is set The step of meter, considers the routability of design using Monte Carlo analysis.The routability of design, which can be considered, to be possible to Semiconductor chip displacement or consider the desired extent as caused by jigsaw process chip displacement.In one embodiment, consider Up to +/- 80 μm in the x and y direction and the semiconductor chip displacement for rotating up to +/- 0.5 degree.Accordingly, it is possible to occurred Design is in violation of rules and regulations or routing error can quickly be characterized in design environment and by adjusting default layer before Prototyping It designs to correct.
Figure shows that the second part 390b of conductive layer 390, second part 390b are arranged in half from Figure 13 F Figure 13 G continued Conductor chip 334,388 top of interconnection 356, sealant 366 and insulating layer.According to semiconductor chip 334 and the reality of interconnection 356 Position forms the second part 390b of conductive layer 390, and the second of conductive layer 390 using such as actual measurement reference point R9 and R10 Part 390b is also connected to the first part 390a of conductive layer 390.In one embodiment, after first part 390a is formed Form second part 390b.Alternatively, it is formed simultaneously part 390 and 390b.Therefore, consider, first part 390a and second Part 390b forms complete RDL designs, wherein default layer pattern is connected to interconnection 356 and semiconductor chip 334.Although first The design or pattern of part 390a remains unchanged, but the step of pattern or design of adaptation second part 390b ensures and interconnect 356 are contacted, although the position of semiconductor chip 334 changes or shifts.
Figure 13 H show to be formed in the UBM 394 of 392 top of conductive layer 390 and insulating layer.UBM394 can be multiple metals Lamination, including adhesive layer, barrier layer, Seed Layer and wetting layer.The layer of UBM394 can be Ti, TiN, TiW, Al, Cu, Cr, CrCu, Ni, NiV, Pd, Pt, Au and Ag.In one embodiment, UBM 394 includes TiW Seed Layers, Cu Seed Layers and Cu UBM Layer.TiW Seed Layers are conformally coated in 392 top of insulating layer and extend in the opening being formed in insulating layer 392, and The conformally part top coated in conductive layer 390.Cu Seed Layers are conformally coated in above TiW Seed Layers.Cu UBM layers Conformally it is coated in above TiW Seed Layers and Cu Seed Layers.UBM 394 serves as conductive layer 390 and the solder projection subsequently formed Or the intermediate conductive layer between other I/O interconnection structures.UBM 394 can be provided and the interconnection of the low resistance of conductive layer 390, butt welding Expect the blocking of diffusion and the increase of solder wettability.
Conductive bump material is existed using evaporation, electrolysis plating, electrodeless plating, globule or silk-screen printing technique 390 top of UBM 394 and conductive layer.Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and a combination thereof, connect With optional flux solution together.For example, bump material can be eutectic Sn/Pb, high kupper solder or lead-free solder.Using suitable Attachment or bonding process bump material is attached to UBM 394.In one embodiment, by the way that bump material is heated to it Bump material reflux more than fusing point is made to form spherical ball or convex block 396.In some applications, convex block 396 is by secondary back To be improved to the electrical contact of UBM 394.Convex block can also be attached to UBM 394 by compression.The expression of convex block 396 can be formed in The a type of interconnection structure of 394 tops of UBM.Interconnection structure can also use conductive paste, stud bumps, dimpling block or its He is electrically interconnected.
After convex block 396 is formed, using saw blade or laser cutting tool 398, by panel 380 in semiconductor chip 334 Between be divided into individual FOWLP 400.
The FOWLP 400 that figure shows to complete from Figure 13 H Figure 14 continued.FOWLP 400 includes semiconductor chip 334, should Semiconductor chip has the optional insulating layer 346 (such as polymer) for 340 top of active surface for being arranged in semiconductor chip. Conductive layer 354 is formed as fan-in interconnection structure, which is connected to contact pad 342 and interconnection or copper pillar 356. Because before segmented semiconductor chip 334, conductive layer 354 and interconnection structure or copper pillar 356 are formed on a wafer level, so Conductive layer and interconnection structure or copper pillar are formed without self adaptive patterning, this is because forming recombination chip or embedded It is not displaced during chip panel.With 366 packaged semiconductor 334 of sealant, conductive layer or fan-in RDL 354 and interconnection Structure 356.Back coating 384 is arranged in the back side 338 of semiconductor chip 334 and is formed around the periphery of semiconductor chip 334 The top of sealant 366, and contact the back side 338 and sealant 366.Back coating 384 includes the occupy-place equal to FOWLP 400 The footprints or area of area or area.Insulating layer 388 is formed in FOWLP 400 top opposite with back coating 384.It leads Electric layer 390 be formed as from FOWLP 400 extend centrally out be fanned out to RDL, and be also formed as and each semiconductor chip 334 or interconnection structure 356 actual position alignment unit specific pattern.Insulating layer 392 is formed in conductive layer 390 and insulating layer 388 tops.Opening in insulating layer 392 is formed in the part top of conductive layer 390.UBM 394, which is conformally formed, to insulate The upper of layer 392 and conductive layer 390.One or more UBM 394 can partially or completely accounting in semiconductor chip 334 In plane product.Alternatively, one or more UBM 394 may be formed entirely in the outside of the footprints of semiconductor chip 334.It is convex Block 396 is formed in above UBM394 to provide encapsulation input/output (I/O) interconnection for FOWLP 400.In one embodiment In, multiple convex blocks 396 form the bump array being aligned with the periphery of FOWLP 400 or outer profile or Land Grid Array (LGA).
Figure 15 is shown similar to the FOWLP 404 of the FOWLP 400 of Figure 14.FOWLP 404 it is different from FOWLP's 400 it It is in back coating 344 rather than back coating 384 including Figure 12 A.By before sealant 366 is formed in semiconductor 338 top of the back side of chip 334 forms back coating 344, and the surface 406 of sealant 366 is formed in the opposite of insulating layer 388 simultaneously And the surface 408 of the back coating 344 with being formed in 334 top of semiconductor chip is substantially coplanar.In addition, sealant 366 contacts The overleaf side surface 410 of the back coating 344 between 338 and surface 408, side surface 410 are different from the back of the body in FOWLP 400 The similar side surface of finishing coat 384, the similar side surface keep exposure relative to the sealant 366 in FOWLP 400.
Figure 16 is shown similar to the FOWLP 414 of the FOWLP 400 of Figure 14.FOWLP 414 it is different from FOWLP's 400 it It is in omission back coating 384 and forms sealant 366.Sealant 366 in Figure 16 is arranged in semiconductor chip 334 338 top of the back side, and the encapsulation of semiconductor can be by installing semiconductor chip 334 come complete in encapsulation process down Into as discussed above concerning described by Figure 13 A.
Figure 17 is shown similar to the FOWLP 418 of the FOWLP 414 of Figure 16.FOWLP 418 it is different from FOWLP's 414 it It is in omission insulating layer 388 and is formed directly on sealant 366 using conductive layer 420 as RDL is fanned out to.As conductive layer As 390, conductive layer 420 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials.It is conductive The deposition of layer 420 uses PVD, CVD, electrolysis plating, electrodeless plating or other suitable techniques.In one embodiment, it leads Electric layer 420 is RDL, including TiW Seed Layers, Cu Seed Layers and the Cu being formed in above TiW Seed Layers and Cu Seed Layers Layer.Conductive layer 420 provides electrical interconnection between electrical interconnection 356 and UBM 394 and convex block 396.As above referring for example to Figure 13 E In conductive layer 390 discussed, can use for adjusting the position of conductive layer 420 so as to true with semiconductor chip 334 Or the different methods of physical location alignment.Sealant 366 in Figure 16 is arranged in 338 top of the back side of semiconductor chip 334, And the encapsulation of semiconductor chip can be by installing semiconductor chip 334 to complete, as above down in encapsulation process Text is with reference to described by Figure 13 A.
Figure 18 is shown similar to the FOWLP 424 of the FOWLP 414 of Figure 16.FOWLP 424 it is different from FOWLP's 414 it It is in omission conductive layer 354.In addition, interconnection structure or copper pillar 348 are formed directly into contact pad 342 in figure 21 On rather than interconnection structure 356 is formed on fan-in RDL as shown in Figure 16.As shown in Figure 12B, in dividing semiconductor Before chip 330, interconnection structure 348 is preferably formed on a wafer level, so that the formation of interconnection structure does not need to self adaptive figure Case.On the contrary, the formation or the conductive layer 390 that is aligned with interconnection structure 348 of self adaptive patterning for unit specific pattern It places.
Figure 19 is shown similar to the FOWLP 428 of the FOWLP 400 of Figure 14.FOWLP 428 it is different from FOWLP's 400 it It is in omission conductive layer 354.In addition, interconnection structure or copper pillar 348 are formed directly into contact pad 342 in figure 21 On rather than interconnection structure 356 is formed on fan-in RDL as shown in Figure 14.As shown in Figure 12B, in dividing semiconductor Before chip 330, interconnection structure 348 is preferably formed on a wafer level, so that the formation of interconnection structure does not need to self adaptive figure Case.On the contrary, the formation or the conductive layer 390 that is aligned with interconnection structure 348 of self adaptive patterning for unit specific pattern It places.
Figure 20 is shown similar to the FOWLP 432 of the FOWLP 404 of Figure 15.FOWLP 432 it is different from FOWLP's 404 it It is in omission conductive layer 354.In addition, interconnection structure or copper pillar 348 are formed directly into contact pad 342 in figure 21 On rather than interconnection structure 356 is formed on fan-in RDL as shown in Figure 15.As shown in Figure 12B, in dividing semiconductor Before chip 330, interconnection structure 348 is preferably formed on a wafer level, so that the formation of interconnection structure does not need to self adaptive figure Case.On the contrary, the formation or the conductive layer 390 that is aligned with interconnection structure 348 of self adaptive patterning for unit specific pattern It places.
Figure 21 is shown similar to the FOWLP 436 of the FOWLP 418 of Figure 17.FOWLP 436 it is different from FOWLP's 418 it It is in omission conductive layer 354.In addition, interconnection structure or copper pillar 348 are formed directly into contact pad 342 in figure 21 On rather than interconnection structure 356 is formed on fan-in RDL as shown in Figure 17.As shown in Figure 12B, in dividing semiconductor Before chip 330, interconnection structure 348 is preferably formed on a wafer level, so that the formation of interconnection structure does not need to self adaptive figure Case.On the contrary, the formation or the conductive layer 440 that is aligned with interconnection structure 348 of self adaptive patterning for unit specific pattern It places.Conductive layer 440 is similar to the conductive layer 420 of Figure 17, and is formed directly into insulation on sealant 366 rather than additional On layer (such as insulating layer 388).
Figure 22 is shown similar to the FOWLP 444 of the FOWLP 436 of Figure 21.FOWLP 444 it is different from FOWLP's 436 it It is in omission UBM 394 and a lower height of convex block 446 is formed directly on conductive layer 440.In one embodiment, Multiple a lower height of convex blocks 446 form the bump array or LGA being aligned with the periphery of FOWLP 444 or outer profile.Preferably, The height H2 of a lower height of convex block 446 is in the range of 20 μm to 125 μm.
In the foregoing specification, it has been described that the various embodiments of the disclosure.However, it will be apparent that, do not depart from as Under the premise of the wider spirit and scope of the present invention stated in the appended claims, the present invention can be carry out various modifications And change.Therefore, the specification and drawings can be considered illustrative sense meaning and not restrictive.

Claims (20)

1. a kind of method for manufacturing multiple semiconductor packages, including：
There is provided multiple semiconductor chips, what the multiple semiconductor chip included being arranged in the semiconductor chip each has The copper post of source surface；
By the way that single sealant arrangement is partly led for each in the semiconductor chip and with described in a single step The side surface of the copper post arranged above each active surface in body chip contacts to form embedded chip face Plate；
The copper post being arranged in by identification above each active surface in the semiconductor chip, uses up and studies Actual position as measuring each semiconductor chip in the embedded chip panel；And
Using maskless patterning system above the multiple semiconductor chip and the surface of the embedded chip panel It is upper formed multiple unit specific patterns so as to by one of the multiple unit specific pattern in the embedded chip panel The actual position alignment of each semiconductor chip；And
The embedded chip panel is divided to form the unit including semiconductor chip and above the semiconductor chip Multiple semiconductor packages of specific pattern.
2. the embedded chip panel is formed by following operation according to the method described in claim 1, further including：
Carrier is provided；
The multiple semiconductor chip is installed on the carrier down；And
Each in the multiple semiconductor chip and arrange the sealant around each copper post.
3. the embedded chip panel is formed by following operation according to the method described in claim 1, further including：
Carrier is provided；
The multiple semiconductor chip is installed on the carrier up；And
Each in the multiple semiconductor chip and arrange the sealant around each copper post.
4. the carrier is removed with the back side of each semiconductor chip of exposure according to the method described in claim 3, further including.
5. it according to the method described in claim 1, further includes：
It is formed in the fan-in redistributing layer (RDL) extended above the active surface of each semiconductor chip；And
The copper post is formed above the fan-in redistributing layer (RDL).
It is 6. described to be fanned out to according to the method described in claim 1, further include to form the unit specific pattern as fan-out structure Structure is arranged in the multiple semiconductor chip top, sealant top and is coupled to the copper post.
7. the unit specific pattern is formed as partly leading for the multiple according to the method described in claim 1, further including Each unique unit specific pattern in body chip, the wherein unique unit specific pattern include being formed in the sealing Agent top and the conductive layer for being coupled to the copper post.
8. a kind of method for manufacturing multiple semiconductor packages, including：
Multiple semiconductor chips are provided, the multiple semiconductor chip includes being arranged on the active surface of each semiconductor chip The conductive column of side；
By in a single step by single sealant arrangement for each in the multiple semiconductor chip and with it is described The side surface of the conductive column contact arranged above each active surface in semiconductor chip is embedded to be formed Chip panel；
Measure the actual position of each semiconductor chip in the embedded chip panel；And
Unit specific pattern is formed so as to by described in each top of the semiconductor chip using maskless patterning system The actual position of each respective semiconductor chip in each and embedded chip panel of unit specific pattern Alignment；And
The embedded chip panel is divided to form multiple semiconductor packages.
9. according to the method described in claim 8, the step of conductive column is wherein provided further include by the conductive stud into For copper post.
10. convex block is formed according to the method described in claim 8, being additionally included in above each conductive column, so that the convex block It is aligned with the respective profile of each semiconductor packages.
11. it according to the method described in claim 9, further includes：
It is formed each in the semiconductor chip for including contact pad；And
The copper post is formed above each contact pad in the respective semiconductor chip.
12. according to the method described in claim 8, before being additionally included in and forming the sealant around the semiconductor chip, Each back side in the multiple semiconductor chip forms back coating.
13. according to the method described in claim 8, each back side being additionally included in the multiple semiconductor chip is simultaneously And arrange back coating in the surface for the sealant arranged around the multiple semiconductor chip.
14. each semiconductor chip is measured relative to the described true of whole plate benchmark according to the method described in claim 8, further including Real position.
15. a kind of method for manufacturing semiconductor packages, including：
Offer includes being embedded in semiconductor chip in the encapsulant and with the active surface for being coupled to the semiconductor chip The chip panel of interconnection structure；
It is arranged in by identification above each active surface in the semiconductor chip and from the semiconductor chip In each active surface offset the interconnection structure end, described in Optical imaging measurement in chip panel The actual position of the interconnection structure；And
Unit specific pattern is formed so that the unit is specific above the semiconductor chip using maskless patterning system Pattern is aligned with the actual position of the interconnection structure.
16. according to the method for claim 15, further include and form the sealant around the semiconductor chip, without The back side of the semiconductor chip forms the sealant so that the back side of the semiconductor chip is relative to described Sealant is exposed.
17. it according to the method for claim 15, further includes by selecting tool from the design of many scheduled unit specific patterns There is the unit specific pattern with each actual position best fit in the semiconductor chip, it is special to form the unit Pattern is determined to be aligned with the actual position of each semiconductor chip in the chip panel.
Convex block is formed 18. according to the method for claim 15, being additionally included in above the unit specific pattern, so that institute The profile that convex block is stated with the semiconductor packages is aligned.
19. according to the method for claim 15, wherein the step of providing the interconnection structure further includes to form the interconnection Structure is as copper post.
20. it according to the method for claim 19, further includes：
The unit specific pattern is formed as conductive layer；
The insulating layer of polybenzoxazoles, polyimides or epoxy solder mask is formed above the unit specific pattern；
Opening is formed in the insulating layer above the unit specific pattern to limit Land Grid Array pad；And
A lower height of convex block is formed above the Land Grid Array pad.
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