CN108307661A - The micro-miniaturized semiconductor module moulded entirely - Google Patents

The micro-miniaturized semiconductor module moulded entirely Download PDF

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Publication number
CN108307661A
CN108307661A CN201680067827.1A CN201680067827A CN108307661A CN 108307661 A CN108307661 A CN 108307661A CN 201680067827 A CN201680067827 A CN 201680067827A CN 108307661 A CN108307661 A CN 108307661A
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China
Prior art keywords
smd
semiconductor
pad
grain
coupled
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Granted
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CN201680067827.1A
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Chinese (zh)
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CN108307661B (en
Inventor
克里斯多佛·M·斯坎伦
提莫泽·L·奥森
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Cypress Semiconductor Corp
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Cypress Semiconductor Corp
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Priority claimed from US15/354,447 external-priority patent/US9831170B2/en
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a kind of semiconductor modules, the semiconductor module may include full molded substrate part, the full molded substrate part includes flat surfaces, the full molded substrate part further includes semiconductor grain, conductive column and encapsulation object, the semiconductor grain includes engagement pad, the conductive column is coupled to engagement pad and extends to the flat surfaces, and the encapsulation object is set on the active surface, on four side surfaces and around the conductive column, and the wherein end of the conductive column exposes at the flat surfaces of the full molded substrate part from the encapsulation object.It includes the wiring layer that may be disposed on the full molded substrate part to accumulate interconnection structure.Photoimageable solder mask material may be disposed on the wiring layer and include opening, and the semiconductor grain and surface-mount devices (SMD) platform pad of the conductive column are electrically coupled to be formed.SMD components can be electrically coupled to the SMD platform pads with surface mounting technique (SMT).

Description

The micro-miniaturized semiconductor module moulded entirely
Cross reference to related applications
Present patent application is advocated in application on November 20th, 2015 and entitled full molding microneedle semiconductor module The U.S. provisional patent application cases the 62/258th of (Fully Molded Miniaturized Semiconductor Module), No. 040 right (including date of application), the disclosure of the case are hereby incorporated herein with this way of reference.Present patent application is also It is entitled semiconductor device and its method (Semiconductor including redistribution layer filed in 2 days November in 2015 Device and Method Comprising Redistribution Layers) US application case the 14/930,514th Continuation in part application case, US application case the 14/930th, 514 be filed in 9 days March in 2015 it is entitled include thicken Semiconductor device and its method (the Semiconductor Device and Method Comprising of redistribution layer Thickened Redistribution Layers) US application case the 14/642nd, 531 continuation in part application case, it is beautiful State's application case the 14/642,531st advocates the entitled wafer with thick and heavy distribution layer trace filed in 10 days March in 2014 Grade chip scale package (Wafer-Level-Chip-Scale-Packages with Thick Redistribution Layer Traces) US provisional patent the 61/950th, 743 right, and further or on December 29th, 2014 Shen Entitled full molding fan-out wafer grade please encapsulates (Die Up Fully Molded Fan-Out Wafer Level Packaging the continuation in part application case of US application case the 14/584th, 978), US application case the 14/584th, 978 It is entitled full molding fan-out wafer grade encapsulation (Die Up Fully Molded Fan-Out filed in September in 2013 12 days Wafer Level Packaging) US application case the 14/024th, 928 continuation application, US application case the 14/th 024, No. 928 is issued as patent the 8th, 922,021 now, is entitled full molding fan filed in September in 2012 30 days Go out the US application case of wafer-level packaging (Die Up Fully Molded Fan-Out Wafer Level Packaging) 13/632, No. 062 continuation application, US application case the 13/632nd, 062 are issued as patent the 8th, 535,978 now, It is the US application case that entitled full molding filed in 30 days December in 2011 is fanned out to (Fully Molded Fan-Out) 13/341st, No. 654 continuation in part application case, US application case the 13/341st, 654 are issued as patent the 8th now, and 604, No. 600, and advocate entitled to be fanned out to semiconductor packages (Fan-Out Semiconductor filed in 18 days July in 2012 Package the right of the date of application of US provisional patent case the 61/672nd, 860), the disclosure of the case are quoted with this Mode is incorporated herein.
Technical field
This disclosure relates to full molded semiconductor package, and more specifically, it is related to moulding entirely and is fanned out to micromation module, complete Mould fan-out modular (FMFOM) or micromation module (hereinafter referred to " module " or " multiple modules ").Module may include being used for Wearable technology, for Internet of Things (IoT) device or both.
Background technology
Semiconductor device is common in modern electronic product.Semiconductor device has different electrical component quantity and electrical component Density.Discrete semiconductor device typically contains a type electrical component, for example, light emitting diode (LED), small signal transistor, Resistor, capacitor, inductor and power metal-oxide-semiconductor field effect transistor (MOSFET).Integrated semiconductor dress It sets in general to contain and has hundreds to millions of a electrical components.The example of integrated semiconductor device includes microcontroller, microprocessor Device, charge coupled device (CCD), solar cell and digital micro-mirror device (DMD).
Semiconductor device execution function of all kinds, such as signal processing, supercomputing, transmission and reception electromagnetic signal, Daylight is transformed into electric power and establishes the visual projection for television indicator by control electronic device.In amusement, communication, power Visible semiconductor device in conversion, network, computer and consumer products field.Military Application, aviation, automobile, industry control Semiconductor device is also shown in device and office equipment processed.
Semiconductor device utilizes the electrical property of semi-conducting material.The atomic structure of semi-conducting material allows by applying electric field Or base current or transmission adulterate program to manipulate its electric conductivity.Doping is introduced into impurity to semi-conducting material to manipulate and control The electric conductivity of semiconductor device.
Semiconductor device contains active and passive electric structure.Initiating structure (including bipolarity and field-effect transistor) control electricity The flowing of stream.The level applied by the level and electric field or base current that change doping, transistor promote or limit electric current Flowing.Passive structure (including resistor, capacitor and inductor) establish voltage necessary to executing Electricity Functional of all kinds with Relationship between electric current.Passive structure and initiating structure are electrically connected to form circuit, make it possible to semiconductor device execution Supercomputing and other practical functions.
Generally semiconductor device is manufactured using two complicated fabrication schedules, that is, front end manufactures and back-end manufacturing, respectively It may relate to hundreds of steps.Front end manufacture is related to being formed multiple semiconductor grains on the surface of semiconductor crystal wafer.It is every partly to lead Body crystal grain is generally designed to identical and contain the circuit that is formed by being electrically connected active and passive block.Back-end manufacturing relates to And from wafer finished product list singulation semiconductor grain and the crystal grain is encapsulated to provide structural support and be environmentally isolated.Such as institute herein It uses, term " semiconductor grain " refers to both singulative and plural form of words, and therefore can refer to single semiconductor dress It sets and both multiple semiconductor devices.
One purpose of semiconductor manufacturing is to produce more small-sized semiconductor device.Less electricity is generally consumed compared with midget plant Power has superior performance and can more efficiently produce.In addition, compared with small semiconductor device have the smaller area of coverage, this for Compared with being desired for Miniature Terminal product.Smaller semiconductor die particle size can be reached by improving front end of line, to Generate the semiconductor grain with smaller, higher density active and passive component.Back end of line can by improve be electrically interconnected and Encapsulating material and generate the semiconductor device packages with the smaller area of coverage.
The back-end processing of semiconductor grain includes a variety of surface mounting techniques (SMT), is used for semiconductor grain or collection Base material and the printed circuit board surface (PCB) are connected to without using the through-hole in PCB at circuit.Flat-four-side encapsulates (QFP) Using including from the SMT for the lead respectively extended out for encapsulating four sides, which is sometimes referred to as " gull wing lead ".QFP Lead provides the electric input/output (I/O) between the PCB or base material that the semiconductor grain in the encapsulation and the QFP are installed Interconnection.Other SMT encapsulations are made with no gage system, and frequently referred to Flat No Lead package.Flat No Lead package shows Example is that flat-four-side is encapsulated without lead (QFNs) encapsulation and double-side flat without lead (DFN).It includes with wire bonding that QFN, which encapsulates tradition, It is connected to the semiconductor grain of lead frame, I/O interconnection of the lead frame for encapsulation.
Invention content
The chance that semiconductor manufacturing is improved there are one.Therefore, in one aspect, a kind of semiconductor module may include：Entirely Molded substrate part, which includes flat surfaces, which further includes semiconductor grain, leads Electric column and encapsulation object, the semiconductor grain include engagement pad, which is coupled to the engagement pad and extends to the flat surfaces, The encapsulation object is set on the active surface, on four side surfaces and around the conductive column, the wherein end of the conductive column It is exposed from the encapsulation object at the flat surfaces of the full molded substrate part.Accumulation interconnection structure includes that may be disposed at the full mould Wiring layer on base part processed.Photoimageable solder mask material may be disposed on the wiring layer and include opening, with Formation is electrically coupled to the semiconductor grain and surface-mount devices (SMD) platform pad of the conductive column.It can use surface that skill is installed SMD components are electrically coupled to the SMD platform pads by art (SMT).
The semiconductor module can further include：The Photoimageable solder mask include epoxy resin solder resist, polyimides, At least one of PBO and organosilicon.The SMD components can be electrically coupled to the SMD platform pads, and wherein may include can for the SMD components The terminal of welding, the soldering paste may be disposed on the SMD platform pads, and when the welding terminal and the soldering paste contact, should Welding terminal may be provided on the SMD platform pads and be electrically coupled to the SMD platform pads.Under the SMD platform pads may include The solderable surface treatment of row：Nickel (Ni) and gold (Au)；Or Ni, palladium (Pd) and Au；Or tin (Sn)；Or solder；Or organic guarantor's weldering Agent (OSP).The SMD components can be coupled to the platform pad with solder projection.The accumulation interconnection structure may include that high density is more Layer wiring layer.The SMD components can part be in the area of coverage of the semiconductor grain and part is not in the covering of the semiconductor grain In area, and at least one of the SMD platform pads can be positioned at the area of coverage of the semiconductor grain in the full molded structure On edge.First out connector of the module can be adapted to be coupled to battery, and the second connector of the module can be through Adjustment is to be coupled to display.Before any SMD components are coupled to the SMD platform pads, can Complete test in the full molding base The semiconductor grain in bottom point.
In another aspect, a kind of semiconductor module may include：Full molded substrate part, which includes Flat surfaces, the base part further include semiconductor grain, conductive column and encapsulation object, which includes engagement pad, should Conductive column is coupled to the engagement pad and extends to the flat surfaces, which is set on the active surface, four side tables On face and surround the conductive column, wherein the end of the conductive column at the flat surfaces of the full molded substrate part from the packet Seal object exposure.Accumulation interconnection structure may include being set to the wiring layer on the full molded substrate part.SMD components can electric coupling To the wiring layer.
The semiconductor module can further include the SMD components through being electrically coupled to the wiring layer.The SMD components may include：It is solderable The terminal connect；Soldering paste may be disposed on the wiring layer；And when the welding terminal and the soldering paste contact, this is solderable The terminal connect may be provided on the wiring layer and be electrically coupled to the wiring layer.Solder projection can be used to couple the SMD components To the wiring layer.The SMD components can part in the area of coverage of the semiconductor grain and not the covering in the semiconductor grain of part In cover region.First out connector of the module can be adapted to be coupled to battery, and the second connector of the module can be through adjusting It fits to be coupled to display.Before any SMD components are coupled to the SMD platform pads, can Complete test in the full molded substrate The semiconductor grain in part.
In another aspect, a kind of method making semiconductor module may include：Electrical interconnection is formed in semiconductor grain On；And the semiconductor grain is sealed with encapsulation object, to form the first built-in part, the wherein electrical interconnection is from the encapsulation object Exposure.The accumulation interconnection structure including conductive RDL layer can be formed on first built-in part and be electrically connected to the electrical interconnection Part.Surface-mount devices (SMD) the platform pad for being electrically coupled to the conduction RDL layer can be formed.Surface mounting technique (SMT) can be used SMD components are coupled to the SMD platform pads, to be provided between the SMD components through the conductive column and the accumulation interconnection structure Being electrically connected between the semiconductor grain.
The method of the making semiconductor module can further include by following formation SMD platform pads：By Photoimageable solder Shielding material is set on the conduction RDL layer；It is formed in the Photoimageable solder mask material on the conduction RDL layer Opening；And apply following solderable surface treatment on the SMD platform pads：Ni and Au；Ni, Pd and Au；Sn；Solder；Or OSP.The SMD components, which are coupled to the SMD platforms pad, to further include：By soldering paste screen painting in each of the SMD platform pads it On；The welding terminal of the SMD components is positioned on first built-in part so that welding terminal contact is at this The soldering paste on SMD platform pads；And the reflow soldering paste by the SMD components to be coupled to the SMD platform pads.By the SMD groups Part appoints whichever to be coupled to before first built-in part, can semiconductor grain of the electrical testing in first built-in part.It should Method can further include that the SMD components are coupled to the SMD platform pads so that SMD components the covering in the semiconductor grain In cover region and part is not in the area of coverage of the semiconductor grain.
One of ordinary skill in the art can be had a clear understanding of from specific implementation mode and attached drawing and claims it is aforementioned and its His aspect, feature and advantage.
Description of the drawings
Figure 1A to Fig. 1 D shows as-grown wafers showed or base material comprising multiple semiconductor grains and is formed in multiple semiconductor Conductive interconnection part on crystal grain.
Fig. 2A to Fig. 2 K show semiconductor module, module or semiconductor grain module formation various aspects.
Fig. 3 shows the program circuit or flow chart that are used to form semiconductor module, module or semiconductor grain module.
Specific implementation mode
In the description which follows with reference to Figure of description, the disclosure includes one or more aspects or embodiment, wherein class As label represent same or analogous component.One of ordinary skill in the art will be appreciated that this explanation is intended to cover such as in the disclosure Spirit and scope in may include alternative solution, modification and equivalent, and the disclosure is by by following disclosure and diagram The appended claims supported and its effect person are limited.In the present note, it is proposed to provide fully understanding for the disclosure Many details, specific configuration, composition and program etc..In other cases, it in order not to obscure the disclosure, does not describe The detail of well known program and manufacturing technology.In addition, Various embodiments shown in figure are illustrative expressions and need not So show to scale.
The disclosure, its aspect and embodiment be not limited to particular device disclosed herein, material type or other be Examples of components of uniting or method.It is used for arranging in pairs or groups with the specific embodiment from the disclosure, has contemplated that and manufacture and seal Fill well known many add-on assembles, manufacture and assembly program in consistent technical field.Although thus, for example, open Specific embodiment, but the embodiment and the component of implementation may include be for this as known in technical field The group of any component, model, type, material, version, amount, and/or the fellow of system and the component implemented, the system and implementation Part is consistent with the operation of intention.
Words " exemplary " used herein, " example " or its various forms mean serving as example, case or figure Solution is illustrated.Be described herein " exemplary " or for " example " any aspect design not necessarily be considered as preferably or advantage be better than other Aspect or design.In addition, example provides only for purpose that is clear and understanding and is not intended to limit or limit in any way The relevant portion of fixed disclosed object or the disclosure.Will appreciate that can be presented countless additional with different range or replace For example, but omitted for simplicity purposes.
In following example, embodiment and specific implementation mode are with reference to example, it will be appreciated by a person skilled in the art that its The device and example that his manufacturing device and example can be mutually mixed with the device and example that are provided or substitution is provided.In above description With reference to the place of specific embodiment, it should be apparent that, can carry out it is several modification without departing from its spirit, and it is clear that this A little embodiments and embodiment can also be applied to other technologies.Therefore, disclosed object intention include all such changes, Modification and variation, they fall in the spirit and scope of the disclosure and the knowledge of one of ordinary skill in the art.
For generally, semiconductor device is manufactured using two complicated fabrication schedules：Front end manufactures and back-end manufacturing.Before End manufacture is related to being formed multiple crystal grain on the surface of semiconductor crystal wafer.Each crystal grain on the wafer, which contains, to be electrically connected to be formed The active electrical component and passive electrical component of functional circuit.Active electrical component (such as transistor and diode) has control electric current The ability of flowing.It is necessary that passive electrical component (such as capacitor, inductor, resistor and transformer) establishes execution circuit function institute Voltage and electric current between relationship.
Passive block and active block are formed on the surface of semiconductor crystal wafer by a series of program steps, including are mixed Miscellaneous, deposition, photoetching process, etching and planarization.Doping by such as be ion implanted or thermal diffusion technology by add impurities to In semi-conducting material.The electric conductivity for adulterating the semi-conducting material in modification of program active device, semi-conducting material is transformed into absolutely Edge body, conductor, or in response to electric field or base current and dynamic changes the electric conductivity of semi-conducting material.Transistor, which contains, to be configured At necessary different type and the area of doping level, with make it possible to when applying electric field or base current transistor promote or Limit the flowing of electric current.
Active block and passive block are formed by the layer of the material with different electrical properties.Deposition of all kinds can be passed through Technology carrys out forming layer, partly determines deposition technique according to the type of the material of deposition.For example, film deposition can relate to chemical gaseous phase Deposit (CVD), physical vapour deposition (PVD) (PVD), electrolysis plating and electroless plating program.For generally, each layer is patterned To form active block part, passive block part or the electrical connections between component.
It can be used photoetching process by pattern layers, photoetching process is related to depositing light-sensitive material (for example, photoresist) in waiting for figure On the layer of case.Pattern is transferred to photoresist from photomask using light.In one embodiment, light is removed using solvent The part through light of resist pattern is caused, and exposes the part of underlying layer to be patterned.In another embodiment, use is molten Agent removes the part (negative photoresist) without light of photoresist pattern, and exposes the portion of underlying layer to be patterned Point.The rest part for removing photoresist, leaves patterned layer.Alternatively, some types of material are by using such as Electroless plating and electrolysis plating technology by the material be deposited directly to by previously deposited/etching program be formed by area or It is patterned in gap.
Patterning is the basic operation for the part for removing the top layers on semiconductor wafer surface.Photoetching process, light can be used Mask, mask, oxide or metal removal, photography and mould printing and microetch remove the part of semiconductor crystal wafer. Photoetching process includes：Pattern is formed in light shield or photomask；And the pattern is shifted to the superficial layer of semiconductor crystal wafer.Photoetching process with Active and passive block horizontal size is formed on the surface of semiconductor crystal wafer by two step formula programs.First step, by light The pattern of cover or photomask is transferred in photoresist layer.Photoresist is that structure and property change are undergone when being exposed Light-sensitive material.The program of the structure and property that change photoresist acts on photoresist as minus or eurymeric is used up Cause resist.Photoresist layer is transferred in crystal column surface by second step.Transfer is happened at etching and removes semiconductor When the part of the top layers of wafer not covered by photoresist.The chemical property of photoresist makes the photoresist Substantially keep complete, and while the part not covered by photoresist for removing the top layers of semiconductor crystal wafer, Resistance is chemically etched solution removal.Can according to the specific photoresist and the desired result that use change formation, exposure and The program of photoresist is removed, and modification removes the program of a part for semiconductor crystal wafer.
In minus acts on photoresist, photoresist is exposed, and in the program of entitled polymerization from solvable shape Condition changes to insoluble situation.In polymerization, make unpolymerized material exposure or be exposed to energy source, and polymer forms crosslinking material Material, which is resist.In most of negative photoresists, polymer is polyisoprene.With chemical solvent or Developer removes soluble fraction (that is, not being exposed part) and is left in photoresist layer corresponding to the opaque figure on light shield The hole of case.The mask that pattern is present in opaque region is known as mask of clearing out a gathering place.
In eurymeric acts on photoresist, photoresist exposes and in the program of entitled light dissolvingization from relatively non- Solvable situation changes to more solvable situation.In light dissolvingization, relatively insoluble photoresist is exposed to luminous energy appropriate It measures and is converted into more solvable state.It, can be by solvent removal photoresist through light dissolvingization part in developing programs. Basic positive photoresist polymer is phenol-yuban, also known as phenol-formaldehyde phenolic resin.With chemical solvent or development Agent removes soluble fraction (that is, the part being exposed) and leaves the hole corresponding to the transparent pattern on light shield in photoresist layer Hole.The mask that pattern is present in clear area is known as dark-field mask.
After removing the top section of semiconductor crystal wafer not covered by photoresist, its of photoresist is removed Remaining part point, and leave patterned layer.Alternatively, some types of material are by using such as electroless plating and electrolysis electricity The technology of plating by the material be deposited directly to by previously deposited/etching program be formed by area or gap by pattern.
The film of material is deposited on existing pattern and will increase lower section pattern and establish non-homogeneous flat surfaces.Uniformly It may be advantageous or must for producing the active block and passive block of smaller and finer and close aggregation on flat surface Must.Planarization can be used to remove material from the surface of wafer and generate the surface of uniform flat.Planarization is related to polishing Pad the surface of wafer polishing.Grinding-material and eroding chemical are added to the surface of wafer during polishing.Alternatively, using Mechanical lapping is carried out at planarization without the use of eroding chemical.In some embodiments, it is purely mechanic grinding by using Belt grinder, standard wafer back grinder (backgrinder) or other similar machines are reached.The grinding machinery of combination is made With and chemical attack effect remove any irregular pattern, lead to the surface of uniform flat.
Back-end manufacturing, which refers to, cuts wafer finished product or is singly cut into single semiconductor grain, and then encapsulation semiconductor grain with For structural support and it is environmentally isolated.It, can be along the nonfunctional area of the referred to as wafer of saw lanes or scribing line in order to singly cut semiconductor grain Cutting crystal wafer.Wafer is cut using radium-shine cutting tool or saw sword list.After singly cutting, single semiconductor grain is installed to encapsulation Base material, the encapsulation base material include for connecing needle or engagement pad with what other systems component interconnected.Then, it is formed in semiconductor grain On engagement pad be connected to the engagement pad in encapsulation.Solder projection, stud bumps, conductive paste, redistribution layer or line can be used Electrical connection is realized in engagement.Encapsulation object or other molding materials are deposited on encapsulation to provide physical support and electric isolution.It connects It, final package is inserted in electric system, and the function of semiconductor device is made to be taken for other systems component.
Electric system can be the stand-alone system that one or more Electricity Functionals are executed using the semiconductor device.Alternatively, electric System can be the sub-component of relatively large system.For example, electric system can be mobile phone, personal digital assistant (PDA), digital video A part for video camera (DVC) or other electronic communication devices.Alternatively, electric system can be graphics adapter, network adapter, Or other signal processing cards in pluggable computer.Semiconductor packages may include that microprocessor, memory, special applications are integrated Circuit (ASIC), logic circuit, analog circuit, radio frequency (RF) circuit, discrete device or other semiconductor grains or electronics group Part.Micromation and weight saving may be advantageous or necessary for the market acceptance of product.Semiconductor must be reduced The distance between device is to realize more high density.
By combining one or more semiconductor packages on single base material, preproduction component can be included in by manufacturer Electronic device and system.Because the semiconductor packages includes accurate functionality, less expensive component can be used in electronic device And streaming production routine manufactures.Gained device is less more expensive than being less likely out of order and manufacturing, to reduce consumer Cost.
Figure 1A to Fig. 1 D shows multiple semiconductor grains, according to front end manufacturing method and program outlined above come It is formed.More specifically, Figure 1A shows semiconductor crystal wafer 10, has the base substrate material 12 for structural support, such as But it is not limited to silicon, germanium, GaAs, indium phosphide or silicon carbide.Pass through non-active intercrystalline wafer area as described above or saw lanes 16 Separated multiple semiconductor grains or component 14 are formed on wafer 10.Saw lanes 16 provide cutting region with by semiconductor crystal wafer 10 Singly it is cut into single semiconductor grain 14.
Figure 1B shows the drawing in side sectional elevation of multiple semiconductor grains 14, the original that multiple semiconductor grain is shown from Figure 1A Raw semiconductor crystal wafer 10.Each semiconductor grain 14 have back side or back surface 18 and with the opposed active surface of the back side 20. Active surface 20 contains analog circuit or digital circuit, and the analog circuit or digital circuit are embodied as being formed in active in crystal grain Device, passive device, conductive layer and dielectric layer, and be electrically interconnected according to the electricity design and function of crystal grain.For example, circuit can Including the one or more transistors, diode and other circuit units being formed in action face 20, with implementation analog circuit Or digital circuit, such as Digital Signal Processing (DSP), ASIC, memory or other signal processing circuits.Semiconductor grain 14 Also it can contain the integrated product development (IPD) for being useful for RF signal processings, such as inductor, capacitor and resistor.
It is led using PVD, CVD, electrolysis plating, electroless plating program or other suitable metal deposit programs to be formed Electric layer 22 is on active surface 20.Conductive layer 22 can be aluminium (Al), copper (Cu), tin (Sn), nickel (Ni), golden (Au), silver-colored (Ag), Or one or more layers of other suitable conductive materials.Conductive layer 22 act as engagement pad or joint sheet, electric coupling or company The circuit being connected on active surface 20.Conductive layer 22 can be formed for be arranged side by side into the edge first away from semiconductor grain 14 away from From engagement pad, as shown in Figure 1B.Conductive layer 22 also can be formed as the engagement pad in a plurality of columns through offset so that first row Edge first of the engagement pad away from crystal grain apart from setting, and with alternately arranged edge of the secondary series engagement pad away from crystal grain of the first row Second distance is arranged.In addition, conductive layer 22 is formed as engagement pad, which is configured as being distributed in semiconductor grain or core Full pad array on the active region of piece.In some cases, which can be configured to irregular or asymmetric array, wherein There are different spacing or a variety of spacing between the engagement pad.
Fig. 1 C show optional insulating layer or passivation layer 26, are conformably applied on active surface 20 and in conductive layer On 22.Insulating layer 26 may include using PVD, CVD, screen painting, rotary coating, spray coating, sintering, thermal oxide or its One or more layers that the program that he is suitble to applies.Insulating layer 26 contains the following one or more layers of (but not limited to)：Two Silica (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminium oxide (Al2O3), polymerization Object, polyimides, benzocyclobutene (BCB), polybenzoxazole (polybenzoxazoles, PBO) or other there is similar insulation And the material of structural property.Alternatively, semiconductor grain 14 is encapsulated without using any PBO layers, and insulating layer 26 can be by difference Material is formed or is omitted completely.In another embodiment, insulating layer 26 includes being formed on active surface 20 and not being arranged Passivation layer on conductive layer 22.When insulating layer 26 exists and when through being formed on conductive layer 22, is then formed and is passed completely through The opening of insulating layer 26, at least part to expose conductive layer 22 are interconnected and are electrically interconnected for subsequent mechanical.Or it is exhausted when omitting When edge layer 26, conductive layer 22 is exposed and is open for being subsequently electrically interconnected without being formed.
Fig. 1 C are also shown electric interconnection structure 28 and are formed as, by suitable conductive material, such as copper, being formed by tubing string (column), pillar (pillar), column (post), pillars (stud), convex block are arranged on conductive layer 22 and couple Or it is connected to conductive layer 22.Patterning and metal deposit program can be used that interconnection structure 28 is formed directly on conductive layer 22, The program such as prints, PVD, CVD, sputter, electrolysis plating, electroless plating, metal evaporation, metal sputtering or other are suitable Metal deposit program.Interconnection structure 28 can be Al, Cu, Sn, Ni, Au, Ag, palladium (Pd) or other suitable conductive materials one A or multiple layers and it may include metal (UBM) layer under one or more salient points.In one embodiment, photoresist layer is deposited on On semiconductor grain 14 and conductive layer 22.By etching developing programs exposure and removing a part for photoresist layer.Make With selective electroplating program, formed in the removed part of photoresist agent and on conductive layer 22 by electric interconnection structure 28 For copper post.It removes photoresist layer and leaves interconnection structure 28, the interconnection structure 28 offer is relative to active surface 20 and absolutely The subsequent mechanical and electrical interconnection and bearing (standoff) of 26 (if present) of edge layer.Interconnection structure 28 may include 10 to Height H1 in the range of 100 microns (μm) or height in the range of 20 μm to 50 μm or about 35 μm of height.
Fig. 1 C further show that wafer 10 is subjected to the optional polishing operation using sanding machine 30, so that back surface 18 planarizes And reduce wafer thickness.Chemical etching can also be used to remove and planarize a part for wafer 10.
Fig. 1 D are illustrated in be formed after interconnection structure 28 and optionally polishing wafer 10, by using saw blade or radium-shine cutting Wafer 10 is singly cut to single semiconductor grain 14 by tool 32 across saw lanes 16.
Fig. 2A displayings containing being useful for temporary or sacrificial base material the carrier or base material 36 of structural support, such as silicon, Polymer, stainless steel or other suitable inexpensive rigid materials.Optional interface layer or double faced adhesive tape 38 are formed in carrier 36 On using as temporarily sticking together junction film or etch stop layer.In one embodiment, carrier 36 is in 38 peripheral support glue of adhesive tape The annular membrane frame of band, which includes open center portion, as shown in Fig. 2 B.
Further semiconductor grains 14 of the displaying from Fig. 1 D of Fig. 2A, at upwardly or crystal grain upwards installation to carrier 36 And interface layer 38, wherein back side 18 is oriented with towards the base material, and active surface 20 is oriented with back to carrier 36.As herein Used in, upwardly or crystal grain to refer to upwards include active surface and the semiconductor die with the opposed back surface of the active surface Grain is positioned such that the back surface is coupled to the carrier.When the semiconductor grain is installed to the carrier, the semiconductor grain The active surface can be oriented with back to the carrier.As used herein, downwards or crystal grain to refer to downwards include active surface And it is positioned such that the active surface is coupled to the carrier and warp with the semiconductor grain of the opposed back surface of the active surface It is oriented towards the carrier, when the semiconductor grain is installed to the carrier, the back surface of the semiconductor grain is oriented with Back to the carrier.Loading or unloading operation or other suitable operations can be used that semiconductor grain 14 is placed on carrier 36.Optionally, Adhesive agent 41 is set between the back side 18 of semiconductor grain 14 and carrier 36.Adhesive agent 41 can be hot epoxides, asphalt mixtures modified by epoxy resin Fat, B-stage epoxy film, ultraviolet light (UV) B-stage film or other suitable materials with optional acrylate copolymer. In one embodiment, adhesive agent 41 can be set on back side 18 before semiconductor grain 14 is mounted on carrier 36.Or Adhesive agent 41 can be set on carrier 36 by person before semiconductor grain is installed to carrier.In other embodiments, such as Fig. 2 B Middle to be shown, semiconductor grain 14 can be directly mounted to interface layer or support tape 38, without using adhesive agent 41.
The installation of semiconductor grain 14 is to carrier 36 so that semiconductor grain it is spaced apart when being installed on carrier 36 or Gap 40, the interval or gap provide region and are fanned out between interconnection structure, including high-voltage line and bus for what is subsequently formed Connecting line.The size in gap 40 includes sufficient region for optionally in the fan-out-type wafer-level packaging subsequently formed (FOWLP) installation semiconductor device or component in.
Fig. 2 C displaying encapsulation objects or mold compound 42, can be formed by polymer composites, such as containing filler Epoxy resin, the epoxy acrylate containing filler, containing the polymer of suitable fillers or other suitable materials.Encapsulation object 42 can For it is non-conductive, provide physical support and in the environment protection semiconductor grain 14 from external elements and pollutant infringement.It can Using cream printing, compression molded, transfer molding, liquid envelope object molding, lamination, vacuum lamination, rotary coating or other are suitable Applicator deposit encapsulation object 42.Specifically, mold 44 of Fig. 2 C displayings with multiple side walls 46, the side wall and top section Or top plate 45, carrier 36 and boundary layer 38 fit together, and semiconductor grain 14 are sealed in mold, for subsequent Sealing.Mold 44 may also comprise bottom part, and carrier 36 is placed on the bottom part, and side wall 46 can contact the base portion Point.In one embodiment, carrier 36 and interface layer 38 are used as bottom mold portion, for follow-up sealing schedule.Alternatively, partly leading Body crystal grain 14, carrier 36 and interface layer 38 may be provided at the mold for including multiple portions (such as top section and bottom part) It is interior.Move moulds 44 by surrounding semiconductor grain 14, or alternatively by semiconductor grain is moved into mold and by mould Tool 44 fits together.
Fig. 2 C further show that mold 44 seals semiconductor grain 14 in chamber or open space 50.Chamber 50 extends In mold 44 between semiconductor grain 14 and interface layer 38.The encapsulation object 42 of volume is arranged in semiconductor grain 14 and carrier 36 On.Entrance 48 can be exhaust port, which has the optional vacuum assistant piece 54 for providing vacuum in chamber 50；So And entrance 48 does not provide the loss path for encapsulation object 42.Encapsulation object 42 can be polymer composites, such as containing filler Epoxy resin, the epoxy acrylate containing filler or the polymer containing suitable fillers.Half is subtracted according to the space requirement of chamber 50 Region occupied by semiconductor die 14 and any additional semiconductor device that may be present and measure 42 volume of encapsulation object.Encapsulation object 42 are set on semiconductor grain 14 and between side wall 46.The top section 45 of mold 44 is moved towards encapsulation object along side wall 46 42 and semiconductor grain 14, until top section contacts encapsulation object, make encapsulation object 42 in the chamber 50 around semiconductor grain 14 It is inside uniformly dispersed and is evenly distributed.The viscosity of encapsulation object 42 and raised temperature can be chosen for uniform fold, example Such as, lower viscosity and raised temperature can be promoted for moulding, cream prints and the flowing of the encapsulation object of spin coating.It also can be in chamber The temperature of control encapsulation object 42 in room 50, to promote the solidification of encapsulation object.Semiconductor grain 14 is embedded in together in encapsulation object 42, Encapsulation object 42 is non-conductive and infringement of the protection semiconductor device from external elements and pollutant in the environment.
The similar sealing schedule about program described in Fig. 2 C of Fig. 2 D displayings.The difference of Fig. 2 D and Fig. 2 C is semiconductor die Orientation of the grain 14 relative to carrier 36 and interface layer 38.Fig. 2 D show embodiment, wherein semiconductor grain 14 down installation and Active surface 20 is oriented towards carrier 36, rather than as shown in Fig. 2 C by the face-up installation of semiconductor grain 14 and active surface 20 is oriented back to carrier 36.Therefore, adhesive agent 41 can be omitted on the back surface 18 of semiconductor grain 14.In addition, although The processing subsequently shown in Fig. 2 E to Fig. 2 K is the encapsulation for semiconductor grain 14 shown in Fig. 2 C, but subsequent processing is same Suitable for being encapsulated shown in Fig. 2 D.
Fig. 2 E displayings are set around semiconductor grain 14 to form the packet of embedded crystal grain panel, molded panel or panel 58 Seal the section view profile diagram of object 42.Panel 58 may include the area of coverage or shape of any shape (such as round, square and rectangle) The factor, and further include the size for allowing and promoting subsequent processing.In some cases, the form factor that panel 58 may include, It is similar to the form factor of 300 millimeters of (mm) semiconductor crystal wafers, and includes the circular coverage area of the diameter with 300mm, so And other sizes or feasible.Panel 58 may include multiple portions or the first built-in part 60, can be used for multiple subsequent shapes At semiconductor module 100, in the same time through being subject to processing on each comfortable panel 58 of semiconductor module.Therefore, although in order to Simplify and can only be formed in Fig. 2 E to Fig. 2 K shows two semiconductor grains 14 of the part of single semiconductor module 100, however It will be appreciated by those skilled in the art that more semiconductor grains 14 and the first built-in part 60 can be included in panel 58 and from The formation of panel 58.First built-in part 60 also can refer to and be interpreted as full molded substrate part, built-in part, embedded crystal grain, substrate Part or first part.First built-in part 60 of panel 58 also can be wrapped also in addition to including one or more semiconductor grains 14 Include integrated circuit (IC), passive device, wafer stage chip Scale Package (WLCSP) and other assemblies.
Consistent with the above, Fig. 2 F shows include the plan view of the panel 58 of multiple first built-in parts 60.Fig. 2 F are also showed that Hatching 2E on panel 58 obtains the sectional view for single first built-in part 60 in Fig. 2 E from the hatching.
In Fig. 2 E, semiconductor grain 14 is removed from mold 44, and embedded crystal grain panel or panel 58 are optionally subjected to Program curing is to cure encapsulation object 42.Optionally, chemical etching, mechanical stripping, CMP, mechanical polishing, heat baking, UV can be passed through Light, radium-shine scanning or wet type divest to remove carrier 36 and boundary layer 38 to expose encapsulation object 42.Alternatively, it carrier 36 and connects Mouth layer 38 can exist for subsequent processing and be removed in later.In some cases, such as adhesive agent 41, interface layer 38 can It persists on semiconductor grain 14 and encapsulation object 42 with the part as final modular structure.For example, interface layer 38 can Be formed as back side coating (other suitable material institutes of the back side 18 by epoxy resin layered product or for sealing semiconductor crystal grain 14 Formed) and form back side or the outer surface of semiconductor module 100.When being formed as back side coating, semiconductor module can formed Any right times during 100 form interface layer 38.Therefore, final module may include interface layer 31, adhesive agent 41 or both. The first surface 55 of encapsulation object 42 can be substantially one of with the back side of semiconductor grain 14 18, adhesive agent 41 and boundary layer 38 Or more persons are coplanar.The first surface 55 of encapsulation object 42 can be substantially coplanar with back side 18, by removing carrier 36 and interface Layer 38 and make encapsulation object 42 expose.
Fig. 2 E also show that panel 58 can be subjected to using the optional polishing operation of sanding machine 62 to planarize encapsulation object 42 Second surface 56 (it is opposed with first surface 55), and reduce the thickness of panel 58 or the first built-in part 60.It can also be used Chemical etching is to remove and planarize a part for the encapsulation object 42 in panel 58, such as second surface 56.Therefore, mutually connection The surface 63 of structure 28 can be exposed relative to the surface 56 of encapsulation object 42, or panel 58 edge expose, with provide between Semiconductor grain 14 and the accumulation interconnection structure subsequently formed are fanned out to being electrically connected between interconnection structure 70.
Fig. 2 E also show that available verifying attachment or optical inspection means 64 measure the semiconductor grain in reconstruction panel 58 14 physical location.Therefore, it can entirely be moulded relative to the physical location of the semiconductor grain 14 in reconstruction panel 58 The subsequent processing of panel 58, as shown about subsequent figures and described.
As described above, the plan view of Fig. 2 F shows panel 58.Fig. 2 F also show that panel 58 may include multiple Cutting Roads or mould The areas Kuai Jian 66, Cutting Road or intermodule area may be disposed between the first built-in part 60 and extend along the first built-in part 60, phase It is similar to the mode that Cutting Road 16 keeps semiconductor grain 14 separated in its primary semiconductor crystal wafer 10.
Fig. 2 G show to form accumulation interconnection structure 70 to be electrically connected conductive interconnection part 28 on molded panel 58, and relatively Wiring is provided in conductive interconnection part 28.Therefore, accumulation interconnection structure 70 may include high-density multi-layered wiring layer.Although accumulation interconnection Shown structure 70 includes three conductive layers, 74,78,82 and three insulating layers 72,76,80, but one of ordinary skill in the art will manage Solution, can be used the layer of less layer or more, this depends on the configuration and design in semiconductor module 100.
Optionally, accumulation interconnection structure 70 may include through forming or being set the first insulating layer on reconstruction panel 58 Or passivation layer 72.First insulating layer 72 may include one or more layers SiO2、Si3N4、SiON、Ta2O5、Al2O3Or with similar The other materials of insulation and architectural characteristic.PVD, CVD, printing, spin coating, spraying, sintering or thermal oxide can be used to form insulation Layer 72.Opening or the first level through-hole may pass through insulating layer 72 and be formed on interconnection structure 28, with semiconductor grain 14 Connection.In some cases, before forming the first conductive layer 74, the opening or the first level through-hole can be filled with conductive material Or be formed as the first level conductive through hole.Alternatively, in company with the formation of the first conductive layer 74 and in the formation of the first conductive layer 74 The same time, which can be filled with conductive material and is formed as the first level conductive through hole.
First conductive layer or wiring 74 can be formed on reconstruction panel 58 and the first insulating layer 72 on using as first RDL layer with：It extends through the opening in the first insulating layer 72, be electrically connected with the first level conductive through hole and and electric interconnection structure 28 electrical connections.Conductive layer 74 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or use patterning and metal deposit program institute Other formed are suitble to conductive material, the program such as sputter, electrolysis plating and electroless plating or other suitable programs.
Can be similar to or be identical to the second insulating layer of the first insulating layer 72 or passivation layer 76 can be arranged or be formed in reconstruct On panel 58, the first conductive layer 74 and the first insulating layer 72.Opening or the second level through-hole can be formed across the second insulation Layer 76 with the first conductive layer 74 to connect.In some cases, before forming the second conductive layer 78, the opening or the second level Through-hole can be filled with conductive material or be formed as the second level conductive through hole.Alternatively, together with formed the second conductive layer 78 and With the same time for forming the second conductive layer 78, which can be filled with conductive material and is formed as the second level and lead Electric through-hole.
Second conductive layer or wiring layer 78 (it can be similar to or be identical to the first conductive layer 74) can be used as the second RDL layer shape At on reconstruction panel 58, on the first insulating layer 72, on the first conductive layer 74, on the second level conductive through hole or In the opening of second insulating layer 72, with mutual with the first conductive layer 74, the first level conductive through hole and the second level conductive through hole, electricity Link structure 28 and semiconductor grain 14 is electrically connected.
Third insulate or passivation layer 80 (can be similar to or be identical to the first insulating layer 72) can be arranged or be formed in second and lead On electric layer 78 and second insulating layer 76.Opening or third level through-hole can also be formed in third insulating layer 80 or be worn through being formed Third insulating layer 80 is crossed to be connect with the second conductive layer 78.In some cases, before forming third conductive layer 82, the opening Or third level through-hole can be filled with conductive material or be formed as third level conductive through hole.Alternatively, it is led together with formation third Electric layer 82 and with same time for forming third conductive layer 82, which can be filled with conductive material and is formed as Third level conductive through hole.
Third conductive layer or wiring layer 82 can be formed on third insulating layer 80, with accumulation interconnection structure 70 in its His conductive layer and conductive through hole electrical connection, and it is electrically connected to semiconductor grain 14 and electric interconnection structure 28.It is similar to such as this paper institutes All layers, electroplated layer or the conductive layer formed by galvanizing process shown, conductive layer 82 can be more metal stacks, more metal stacks Stack includes adhesion layer, barrier layer, kind one or more of crystal layer or wetting layer.Adhesion layer may include titanium (Ti) or titanium nitride (TiN), titanium tungsten (TiW), Al or chromium (Cr).Barrier layer can be formed on adhesion layer, and can by Ni, NiV, platinum (Pt), Pd, TiW or chromium-copper (CrCu) are made.In some cases, barrier layer can be TiW or Ti sputtered layers, and can be used as adhesion layer and resistance Both barrier layer.In any case, barrier layer can inhibit the bad diffusion of the material such as Cu.Kind of crystal layer can be Cu, Ni, NiV, Au, Al or other suitable materials.For example, kind crystal layer can be Cu sputtered layers, include about 2000 angstroms of thickness (such as 2000 ± 0 To 600 angstroms).Kind of crystal layer can be formed on barrier layer, and can act as surface-mount devices (SMD) component subsequently placed or The intermediate conductive layer of 90 lower section of device.In some cases, wetting layer may include Cu layers, and the Cu layers has at about 5 μm to 11 μm Or the thickness in the range of 7 μm to 9 μm.Such as Fig. 2 H are shown that the SMD components 90 subsequently placed may include solder (such as SnAg solders), can be consumed during reflow some of the Cu of conductive layer 84 and the Cu between the solder and the wetting layer it Between interface formed intermetallic compound.However, the Cu of wetting layer may be fabricated into it is sufficiently thick, with prevent Cu pad in high temperature ageing Period is completely consumed by solder.
Photoimageable solder mask material 84 may be provided at accumulation interconnection structure 70 and conductive wiring layer 74,78 or 82 is (all Such as top wiring layer) one or more of on, around accumulation interconnection structure 70 and conductive wiring layer 74,78 or 82 (such as One or more of top wiring layer), or in accumulation interconnection structure 70 and (such as top cloth of conductive wiring layer 74,78 or 82 Line layer) one or more of on and around accumulation interconnection structure 70 and conductive wiring layer 74,78 or 82 (such as top wiring Layer) one or more of the two.Although can change in the quantity of the conductive wiring layer in accumulation interconnection structure, fields The skilled person will understand that the description of the placement of Photoimageable solder mask material 84 is not limited to relative to conductive wiring layer 82.It can Light imaging solder mask material 84 may include epoxy resin, solder resist, polyimides, PBO, organosilicon or other are similar or suitable Material.Photoimageable solder mask material 84 may include the opening around conductive wiring layer 78 to form surface-mount devices (SMD) platform pad 86 can be electrically coupled to semiconductor grain 14 and conductive column 28, such as through the accumulation interconnection structure 70.SMD Platform pad 86 can further include following solderable surface treatment：Ni and Au；Ni, Pd and Au；Sn；Solder；Organic solderability preservative (OSP)；Or other suitable materials.In some cases, solder mask material 84 and SMD platforms pad 86 are formed as accumulation mutually Link the part of structure 70.
With the accumulation interconnection structure 70 being formed on embedded crystal grain panel 58 and built-in part 60, in any SMD groups Part 90 is coupled to before SMD platforms pad 86, can Complete test be embedded in the semiconductor grain 14 in full molded substrate part 60.Together Sample, (it is included in electrical interconnection knot before accumulation interconnection structure 70 is formed on embedded crystal grain panel 58 and built-in part 60 After structure 28 is formed on semiconductor crystal wafer 10, but formed embed crystal grain panel 58 before), also can Complete test it is embedded Semiconductor grain 14 in full molded substrate part 60.As used herein, it can test completely including test suite (such as Semiconductor grain 14 and accumulation interconnection structure 70) electrical connection, interconnection and function ability whether appropriate, and ensure non-desired Defect (such as bridge joint or low quality performance) whether the ability occurred by defect.
(such as it is being used to form panel when making the position of semiconductor grain 14 and interconnection structure 28 be changed from nominal position During 58 semiconductor grain 14 is placed and is sealed), the true or physical location of semiconductor grain 14 may not be directed at fan fully Go out the nominal design of interconnection structure to provide desired reliability under given wiring density and pitch tolerance for encapsulation interconnection. When the shift in position of semiconductor grain 14 is small, position or the conductive layer 74 of the opening in insulating layer 72 need not be adjusted Positioning is configured to be properly aligned with interconnection structure 28.However, when the change in location of semiconductor grain 14 and interconnection structure 28 makes Nominal position do not provide with interconnection structure 28 be properly aligned with and for interconnection structure 28 exposure when, then it is special can to pass through unit Fixed patterning, module specific pattern or Adaptive PatterningTM (hereinafter referred to " unit specific pattern ") are adjusted The position of the whole opening in insulating layer 72 and the positioning and configuration of conductive layer 74, such as United States Patent (USP) filed in 9 days Mays in 2013 More detailed description person in application case the 13/891st, 006, the disclosure of the case are herein incorporated by reference.Optionally, Unit specific patternization can be directed to each semiconductor grain 14 and individually adjust the position of opening 66, or can be directed to several semiconductor dies Grain 14 simultaneously adjusts position.The position of position, alignment or the position of opening in insulating layer 72 and alignment and conductive layer 74 And configuration can pass through the nominal position relative to it or the x-y shift relative to benchmark or reference point on panel 58 or rotation Angle, θ is adjusted.
In some cases, optionally, Quick Response Code can be formed in accumulation interconnection layer 70, such as Electricity Functional RDL layer or be led 74,78, one of 82 or more person of electric layer, each semiconductor grain 14, first of the Quick Response Code unique identification in semiconductor module 100 Built-in part 60 or one or more SMD components 90.Unique Quick Response Code can be such as United States Patent (USP) Shen filed in August in 2015 26 days It please case the 14/836,525th and entitled front end package level serializing (the Front Side comprising unique identifier Package-Level Serialization for Packages Comprising Unique Identifiers) in retouched It states and is formed, which is incorporated herein with this way of reference.
Multiple SMD components 90 are electrically coupled to SMD platforms pad 86 by Fig. 2 H shows with SMT.SMD components 90 may include terminal Or engagement pad 91, it is used for the interconnection between SMD components 90 and SMD platforms pad 86 or electrical interconnection.SMD components 90 may include Semiconductor grain of all kinds, wafer stage chip Scale Package (WLCSP) or IC 92, surface-mount devices or aggressive device 94 and passive device 96 (including welding Passive part, such as resistor or capacitor) and other assemblies, it can install To the first built-in part 60 and it is adapted or be configured to semiconductor grain 14 or be embedded in the first built-in part 60 its His device telecommunication.By being mounted directly or being connected to the first built-in part 60, SMD components 90 need not reach in first It installs to PCB or other base materials before embedding part 60 or signal is made to be routed through PCB or other base materials.But exquisiteness can be established Semiconductor module 100 is excluded for being ready to use in the PCB or base material that interconnect various SMD components and the first built-in part 60 It needs.The improvement of semiconductor module 100 is integrated and is reduced size and is highly suitable for miniature electronic systems, such as needs minimum can The smart watch and other IoT devices of energy form factor.
SMT 97 for SMD components 90 to be electrically coupled to SMD platforms pad or bend (flex) connector 86 may include welding Material, soldering paste, solder projection, convex block or orbicule.It is indicated as described above, connect for the solderable platform pad of SMT 97 or flexure Fitting 86 is formed as the part of the multilayer wiring of accumulation interconnection structure 70 and conductive layer 74,78,82, or is formed in accumulation interconnection On the multilayer wiring of structure 70 and conductive layer 74,78,82 and it is coupled to accumulation interconnection structure 70 and conductive layer 74,78,82 Multilayer wiring, to allow the Big mutation rate of the size of SMT 97.In some cases, it is electrically coupled to the SMD components 90 of SMD platform pads Further include：SMD components 90 comprising welding terminal 91；Soldering paste 97 is set on SMD platforms pad 86；And it is solderable Terminal 91, be arranged on SMD platforms pad 86 and be electrically coupled to SMD platforms pad 86, and welding terminal 91 then with weldering Cream 97 contacts.Similarly, in some cases, at least one for being coupled to the SMD components 90 of platform pad 86 will be with solder projection 97 couplings.
When SMT 97 includes solder, which can be placed on SMD platforms pad 86, to promote between SMD 90 and accumulation Telecommunication between interconnection structure 70 and the first built-in part 60.Solder may include Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, weldering Material and above-mentioned respective combination, in addition optional flux solvent (flux solution).For example, solder can be congruent melting (eutectic) Sn/Pb, high kupper solder or lead-free solder.Vapor deposition, electrolysis plating, electroless plating, drop ball (ball can be used Drop) or screen printing program is by solder deposition on the first built-in part 60 and on SMD platforms pad 68.In some implementations In example, solder is the Sn soldering paste deposited using screen painting.After SMD 90 is coupled to the first built-in part 60 with solder, Solder can be subjected to reflow program or through reflow to improve between SMD 90 and SMD platforms pad 58 or the first built-in part 60 Electrical contact.After reflow, optionally, embedded crystal grain panel 58 or the first built-in part 60 and SMD 90 can be subjected to aqueous clear It washes, automate one or more of optical check (AOI) and plasma-based cleaning.
Fig. 2 I are illustrated in after the installation to embedded crystal grain panel 58 of SMD components 90, can use saw blade or radium-shine cutting tool 98 Embedded crystal grain panel 58 is cut or singly cut across Cutting Road 66, to form semiconductor module, module or semiconductor grain module 100.Semiconductor module 100 may include multiple full moldings or sealing semiconductor crystal grain 14 and Passive part 96 together with other SMD components 90, it can be at position, downwards position or both upwardly.Therefore, semiconductor module 100 is formed as exquisite module, Exclude the needs for being ready to use in the PCB or other base materials that interconnect various SMD components and the first built-in part 60.Semiconductor module The improvement of block 100 is integrated and is reduced size and is highly suitable for miniature electronic systems, and minimum possible form factor is such as needed Smart watch and other IoT devices.In some cases, and for component (such as semiconductor on the opposite side of encapsulation Crystal grain 14 and component 92,94 and interconnection 96) and using PCB or other base materials more known to encapsulation compare, singly cut The size of population or overall dimension of semiconductor module 100 may include the height of reduction 10%, 20%, 30% or more.
In addition to the benefit for providing exquisite size, module 100 can also provide improved magnitude because of Robust design.For example, half Conductor module 100 may include：At least one part of SMD components 90 is in the area of coverage of one of semiconductor grain 14 and part Not in the area of coverage of the semiconductor grain 14.In addition, at least one of SMD platforms pad 86 can be positioned at full molded substrate part On the edge of the area of coverage of semiconductor grain 14 in 60.Mold compound 42 is added in the face or work of semiconductor grain 14 With the mechanical performance that can improve semiconductor module 100 on surface 20 and on the edge of semiconductor grain 14 17.It is specific and Speech, including being positioned in the design of the SMD platforms pad 86 on the edge 17 of semiconductor grain 14, full molded substrate part 60 Planar second surface 56 with the mechanical sexual isolation at the edge 17 of semiconductor grain 14 is provided.In comparison, if towards lower fan Go out that structure is established and fan-out structure is deposited in below semiconductor grain, then SMD components can partly be mechanically coupled to this and partly lead Body crystal grain is simultaneously partly coupled to mold compound, can lead to the higher thermal mechanical stress in solder dots, leads to solder dots event Barrier.
In some cases, unit specific pattern can be used to establish or be formed accumulation interconnection structure 70.Therefore, can make The of each first built-in part 60 adjustment accumulation interconnection structure 70 being directed in molded panel 58 with unit specific pattern One conductive layer 74, to be aligned in the physical location of each semiconductor grain 14 in each first built-in part 60, to be maintained between Constant alignment between SMD platforms pad 86 and the profile of module encapsulation 100.
Continue Fig. 2 I, Fig. 2 J displaying can containing encapsulation object or mold compound 106 in the case ofs formed semiconductor module, Module or semiconductor grain module 110 (being similar to semiconductor module 100).In the installation of SMD components 90 to embedded crystal grain panel 58 Later, SMD components 90 can be sealed, coat molding or be set in encapsulation object or mold compound 106.Encapsulation object or moldingization Closing object 106 can be by being similar or identical to that the material of encapsulation object 42 is formed, including polymer composite material such as contains filler Epoxy resin, the epoxy acrylate containing filler, contain the polymer of suitable fillers or other suitable materials.Encapsulation object It 106 can be non-conductive, provide physical support and infringement of the protection SMD components 90 from external elements and pollutant in the environment. Cream printing, compression molded, transfer molding, liquid envelope object molding, lamination, vacuum lamination, rotary coating or other conjunctions can be used Suitable applicator is similar or identical to that and shows and describe for encapsulation object 42 depositing encapsulation object or mold compound 106 Program.
It can be sealed by encapsulation object 106 or mould component 90 SMD in cladding by form the second built-in part, full molded tip Partly, built-in part, embedded crystal grain, top section or second part 108.Second built-in part 108 can be with the first built-in part 60 is opposed and be coupled to the first built-in part 60, the first built-in part 60 and second can be kept embedded by accumulating interconnection structure 70 Part 108 interconnects, to form semiconductor module, module or semiconductor grain module 110.The molding of encapsulation object 106 can be happened at It is singly cut by saw blade or radium-shine cutting tool 98 to be formed before or after semiconductor module 110.
Fig. 2 K shows semiconductor module, module or semiconductor grain module 114 are similar to the semiconductor that Fig. 2 J are shown Module 110.Module 114 displaying other than the institute exhibitor in module 100 and module 110 can also optionally by including some Supplementary features.For example, semiconductor module 114 can further include：First group of input/output (i/o) connector or pad of module 114 116, it can be adapted to be coupled to battery；And the second group of i/o connector or pad 118 of module 114, it is adapted to be coupled to Display or screen.In some cases, battery may be electrically connected at least two terminal or pad 116 of module 114.In some cases In example, display can be electrically connected to module 114 by flexible connector.Optionally, in addition, solder ball or other are suitable Electrical interconnection assembly attaches to module 114 (such as top of module 114 or bottom part) and is used as i/o interconnection pieces.
As further shown in Fig. 2 K, module 114, which may also comprise, to be integrated in the thickness of mold compound 42 (first The side of semiconductor grain 14 in built-in part 60) embedded device, passive component or 3D interconnecting assemblies 120.In some cases In, embedded device 120 may include the SMD 122 for being coupled to vertical interconnection or base material 124, can form embedded device together 120.In other cases, embedded device can only be SMD 122 or only be vertical interconnection 124.It is interior to be embedded in some cases Setting 120 can be formed in module 114, such as the 15/141st, No. 028 disclosed person of US application case filed in 28 days April in 2016, Entitled three-dimensional interconnection component (the 3D Interconnect Component for Fully for full molded package of the case Molded Packages), and the disclosure full text of the case is incorporated herein with this way of reference.
Fig. 2 K also show that module 114 may also comprise shielded layer 126.Shielded layer 126 may include one or more conductive or gold Belong to material, such as Al, ferrite or carbonyl iron, stainless steel, nickeline, mild steel, ferrosilicon steel, foil, electroconductive resin and can stop Or absorb other metals for being interfered between electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion and other devices with it is compound Object.Electrolysis plating, electroless plating, sputter, PVD, CVD or other suitable deposition procedures can be used to pattern and conformably (conformally) deposited barrier 126.Shielded layer 126 or nonmetallic materials, such as carbon black or aluminum slice, to reduce EMI and RFI effects.For nonmetallic materials, shielded layer can be applied by lamination, spraying, brushing or other suitable programs 126.Shielded layer 126 also may be electrically connected to external Low ESR earth point.Shielded layer 126 can add the upper part in module 114 Backside contact (such as semiconductor and on low portion, and between one of semiconductor grain or SMT features or more persons The back side 18 of crystal grain 14) it can contact, be in direct contact or be coupled to shielded layer 126.In some cases, between one or more half Contact between the side of semiconductor die or SMT features, surface or back side and shielded layer 126 can be used as radiator or be used for heat pipe Reason.Optionally, shielded layer 126 is formed as conformal EMI shieldings, EMI shieldings can overlay module 114 top surface and side Surface wholly or largely, includes the 90% to 100% of top surface and side surface, and in some cases, shielded layer 126 Also can overlay module 114 the 6th side (such as bottom side of module 114) 50% or more.
Fig. 3 displayings are used to form module (such as module 100,110,114) or similar modular blocks (such as thermal-enhanced full molding Fan-out modular) program circuit or chart 130 non-restrictive example.Program circuit 130 shows and is directed to according to schematic form Element, action, step or program 132 to 162 are described.Element 132 to 162 is presented by explaination (by unrestricted), and Although element can be performed according to sequence or sequence presented below, inessential.The less element for forming module can be changed Or the sequence or sequence of additional element and various elements.
In element 132, electrical interconnection 28 can be plated on multiple semiconductor grains in the level of primary semiconductor crystal wafer 12 On 14.In element 134, detectable semiconductor crystal wafer 12 it is respective with test in semiconductor crystal wafer 12 or on semiconductor grain 14 respective function.In element 136, semiconductor crystal wafer 12 can be thinned to the finished product Si less than 500 μm or less than 350 microns Thickness.In element 138, semiconductor grain 14 can be singly cut from semiconductor crystal wafer 12.In element 140, it is known that well fill semiconductor die Grain 14 can be placed on towards Shangdi on temporary carrier or base material 36.In element 142, encapsulation object or mold compound 42 can be used to mould Or sealing semiconductor crystal grain 14 is to form the reconstruct wafer, embedded crystal grain panel or plastic front board of any be intended to size and shape 58.In element 144, carrier 36 can be removed to expose the back side 18 of molded semiconductor crystal grain 14.In element 146, panel 58 is embedded Second surface or front side 56 can be subjected to polishing program to expose electrical interconnection 28.In element 148, can scanning panel 58 to measure The position of each semiconductor grain 14 in panel 58, in multiple first built-in parts 60 or in each first built-in part 60 And orientation.
In element 150, (such as unit specific pattern can be used) and form accumulation interconnection structure or high density, multilayer RDL Wiring pattern 70 is so as to accumulate interconnection structure 70 in alignment with each semiconductor grain 14.In element 152, Photoimageable solder mask material Material 84 can be formed on final RDL layer to form SMD platforms pad 86.In element 154, welding surface treatment can be applied to To promote the surface of component to install assembling on the SMD platforms pad 86 being exposed through.In element 156, optionally, detectable panel 58 To test the function of each built-in part 60 in panel 58.It, optionally, can be by polishing or polishing panel 58 in element 158 Back and thinning panel 58 is such as decreased to less than 250 μm of thickness to reduce the thickness of embedded semiconductor crystal grain 14.It is wanting Element 160 can be used SMT assembly programs that SMD components 90 are attached to SMD platforms pad 86, may include 97 screen painting of soldering paste It is positioned on panel 58 on each SMD platforms pad 86 and by SMD components 90 so that the welding terminal 91 of SMD components 90 Platform pad 86 is contacted, and solder 97 can be through reflow SMD components 90 to be coupled to the SMD pads 86 on panel 58.Finally, it Element 162, modular unit 100,110,114 can coverlet cut to separate modular unit from panel 58.
Therefore, can provide or promote several advantages by module 100,110 and 114, advantage it is exemplary and unrestricted clear Include singly：Improve the control to the contact resistance of the engagement pad 22 on semiconductor grain 14；Improve module 110,110 and 114 RF performances；Improve the hot property and electric power distribution of module；Improve the mechanical reliability of module；For accumulating interconnection structure 70 The flat surfaces of pitch lithographic；The substitution of mold compound 42 first is fanned out to dielectric layer；Between encapsulation object 42 and conductive interconnection part The high contrast surface measured for optics die locations between 28；Complete protection semiconductor grain 14 for low k devices Edge；And simplify the flat surfaces containing bottom surface slab warping of SMT assemblings.
Improved control can be provided to the contact resistance of the engagement pad 22 (such as Al engagement pads 22) on semiconductor grain 14 System.Improvement is relative to wafer scale fan-out structure (WLFO), such as eWLB downwards, and wafer scale fan-out structure generally needs downwards Want sputter barrier layer and kind crystal layer to plastic front board or mold compound, to contact the Al joint sheets on semiconductor grain or connect Touch pad, to prevent the formation of aluminium oxide.Plastic front board or plastics in the sputter deposition of barrier layer (such as Ti or TiW barrier layers) Wafer might have problem, this is because plastics tend to outlet (out-gas), and during sputter-etch and kind crystal layer deposition The aluminium oxide that the presence of the oxygen of preceding trace (trace amount) can form a few angstroms leads to high contact resistance in engagement pad, It can interfere with the performance of semiconductor grain.Following item be can pass through to reach management or prevent the formation of aluminium oxide：Before sputter Panel is stored in nitrogen；Extend the degasification time in sputter tool；Extend pumpdown time (pump down time) with Ensure the low-down pressure of foundation in etching chamber；Or penetrate other suitable programs.The first of module 100,110 or 114 In the full molded structure of built-in part 60, the mode just as conducted in chip-covered boss or wafer WLP programs, by apply Cu or Electrical interconnection 28 can be located in encapsulation object 42 to Si or as-grown wafers showed 10 to provide relative to Al by other conductive interconnection parts 28 Or the high-quality contact resistance of other engagement pads 22.As a result, passing through molding or packet between electrical interconnection 28 and engagement pad 22 Sealing-in closes to protect the engagement pad 22 of semiconductor grain 14 so that compared with the fan-out structure downwards of no column, cylinder or column Compared with the procedures risk (exposure and oxidation) for embedding crystal grain panel 58 or the first built-in part 60 is much relatively low.
Also the improved RF performances of module 100,110 or 114 can be obtained by following：The layer of mold compound 42 is arranged On the active surface 20 of semiconductor grain 14 and electrical interconnection 28 is surrounded, this can be in the active surface 20 of semiconductor grain 14 About 10 μm to 100 μm, 20 μm to 50 μm are established with accumulating interconnection structure 70, high-density multi-layered wiring layer or being fanned out between RDL layer Or deviation or the gap of 30 μm (5 μm of plus-minus).Additional deviation can provide buffering or space, promote have better quality factor (Q) Feature (such as inductor) be intended to performance.
By forming the conductive interconnection part 28 of any size and shape, the improvement of module 100,110 and 114 also can be obtained Hot property and electric power distribution.For example, conductive interconnection part 28 can be formed with small pitch Cu columns, with big Cu columns, and Can further include the power plane being formed on same semiconductor grain 14 or ground plane.Because can be put by mold compound 42 Conductive interconnection part 28 is planarized after being placed on the front side 20 of semiconductor grain 14 upwardly, so reducing or excluding to convex block The misgivings of high homogeneity are (even if the size in bump size or the conductive interconnection part 28 for being coupled to semiconductor grain 14 has big change In the case of change).In the case of few or misgivings independent of bump size uniformity, the conduction of large area can be used mutually Connect part (including Cu interconnection pieces) more effectively to distribute electric power to semiconductor grain 14.In some cases, the plane of thick Cu can It is set up as the part of conductive interconnection part 28, or is established as one or more conductive interconnection parts 28, to improve hot property.In addition, Adjustable Cu layers of thickness adjusts performance to be directed to different application.It can must relative to wherein all solder projections or conductive interconnection part Any " chip sets end " or flip type structure that must have identical, identical or substantial similar size and shape are reached State advantage.
Also addition mold compound 42 is can pass through on the face or active surface 20 of semiconductor grain 14 and in crystal grain On edge 17 and crystal edge 17 is surrounded, to obtain the improved mechanical reliability of module 100,110 and 114.Specifically, It is positioned in the design on the edge 17 of semiconductor grain 14 with SMD platforms pad 86, full molded structure or first embedded Part 60 can provide the flat surfaces being mechanically isolated with the pattern at semiconductor grain edge 17.In fan-out structure downwards, Being fanned out to accumulation and can be mechanically coupled to semiconductor grain at least partly and partly be mechanically coupled to mould below SMD components Compound can cause to interconnect the higher thermal mechanical stress in (such as solder dots), cause solder point failure or other failures.
The improvement of module 100,110 and 114 can further include for pitch lithographic flat surfaces (its may be present be because It is planarized when embedding crystal grain panel 58 after molding), promote pitch lithographic, with small depth of field shape such as in exposure At accumulation interconnection structure 70.In addition, accumulation mutually connection can be formed with coplanar exposed surface of conductive interconnection part 28 or end The first layer (either such as the dielectric layer of insulating layer 72 or such as the metal layer of conductive layer 74) of structure 70 is in single mold compound 42 On.The above improvement relative to being fanned out in matrix structure downwards or embeds crystal grain and is contrasted, wherein first layer shape At on more than one base material, such as semiconductor grain and the encapsulation object around the semiconductor grain.Therefore, feature Size is limited solely by the ability of lithography tool, and now, with route map, the ability of lithography tool can be the model at about 2 μm to 5 μm Line in enclosing and space (or 4 μm to 10 μm pitches) or smaller.Relatively thin photopolymerization nitride layer can be applied to panel, this be because But towards the crystal edge pattern in lower structure.With flat structure upwardly, then prolong without very thin trace transcrystalling edge Capable problem.
The improvement of module 100,110 and 114 may also comprise the substitution of mold compound 42 first and be fanned out to dielectric layer, such as insulate Layer 72 so that the first conductive layer 74 is placed to be in direct contact encapsulation object 42.First is omitted to be fanned out to dielectric layer and RDL will be fanned out to 74, which are applied directly to embedded crystal grain panel 58, can reduce cost, can be beneficial to the small parts with low interconnection density.
In embedded crystal grain panel 58, can also have for optical measurement semiconductor grain 14 relative to 42 position of sealant High contrast surface.Molded structure shows excellent in detection process entirely, because which create for the very high right of detection Than the surface of degree, it may include that for example Cu convex blocks show white under black background.In the active surface of semiconductor grain 14 Sealant 42 on 20 removes distractive feature from optical check program, and this feature is present at active surface 20 simultaneously It can slow down and examine speed or inspection is made to complicate.Therefore, high contrast image caused by current designs allows very quick And it reliably scans and reduces cost.
The improvement of module 100,110 and 114 is also allowed for the complete protection crystal edge 17 of low k devices.Low k devices are logical It often needs to form radium-shine slot before cutting semiconductor crystal grain, can be generated in grain edge and add pattern.Radium before cutting It is additional program step to penetrate slot, increases time and expense, but typically to the necessary step for preventing specific fault pattern Suddenly.The specific fault pattern is appeared in towards in lower structure, and the testing cushion in saw lanes can be lifted or move during singly cutting, So that when using glimmer polymeric layer, the pad (it is conductive) through lifting will contact or short circuit RDL or interconnection structure.This public affairs Die sinking block 100,110 and 114 allows that sensitive crystal edge structure is fully sealed with single mold compound 42, and non-formation mould Produced compounds to the photopolymer interface in the edge of low k apparatus structures or adjacent edges in low k apparatus structures, to avoid Structure through lifting simultaneously prevents short circuit.
The improvement of module 100,110 and 114 also allows the flat surfaces of the low warpage containing embedded crystal grain panel 58, letter Change SMD and SMT assemblings.The structure of module 100,110 and 114 can be with the phase that is arranged on the top and bottom of semiconductor grain 14 Part like the encapsulation object 42 of thickness and material character or layer equilibration.Therefore, on the both sides of semiconductor grain 14, by between half The stress that CTE mismatch between semiconductor die 14 and encapsulation object 42 causes can substantial equilibrium.Therefore, in the SMT of SMD components 90 Program and installation (it may include that placing modules are then with the raising temperature reflow solder more than 230 degree Celsius at room temperature) phase Between, embedded crystal grain panel 58 can keep relatively flat.
Although the disclosure includes various forms of several embodiments, in Figure of description and the following specification write The middle details that specific embodiment is presented, and understand example and principle that the disclosure is considered as disclosed method and system, and it is non- It is intended to make the extensive aspect of disclosed concept to be limited to illustrated embodiment.In addition, it will be appreciated by a person skilled in the art that its His structure, manufacturing device and example can be mutually mixed with the structure, manufacturing device and example that are provided or substitution is provided structure, Manufacturing device and example.Above description refer to specific embodiment place, it should be apparent that, can carry out it is several modification without It is detached from its spirit, and it is clear that these embodiments and embodiment can also be applied to other technologies.Therefore, disclosed Object intention includes all such changes, modification and variation, they and falls within the spirit and scope of the disclosure and affiliated neck In the knowledge of field technique personnel.It is, therefore, apparent that can without departing from as such invention proposed in appended claims compared with Various modification and variation are made in the case of broad spirit and range according to this.Therefore, it need to and not restrictive be anticipated with descriptive sense Justice considers this specification and such Figure of description.

Claims (20)

1. a kind of semiconductor module, including：
Full molded substrate part, including flat surfaces, the full molded substrate part further include：
Semiconductor grain, the semiconductor grain include engagement pad,
Conductive column, the conductive column are coupled to the engagement pad and extend to the flat surfaces, and
Encapsulation object, the encapsulation object is set on the active surface, on four side surfaces and surrounds the conductive column, Described in conductive column end at the flat surfaces of the full molded substrate part from the encapsulation object expose；
Interconnection structure is accumulated, the accumulation interconnection structure includes the wiring layer being set on the full molded substrate part；
Photoimageable solder mask material, the Photoimageable solder mask material are set on the wiring layer and include Opening, to form surface-mount devices (SMD) the platform pad for being electrically coupled to the semiconductor grain and the conductive column；And
SMD components, the SMD components are electrically coupled to the SMD platforms pad using surface mounting technique (SMT).
2. semiconductor module according to claim 1, wherein the Photoimageable solder mask includes epoxy resin welding resistance At least one of agent, polyimides, PBO and organosilicon.
3. semiconductor module according to claim 1, wherein being electrically coupled to the SMD components of the SMD platforms pad also Including：
The SMD components including welding terminal；
The soldering paste being set on the SMD platforms pad；And
When the welding terminal and the soldering paste contact, the welding terminal setting the SMD platforms pad it It goes up and is electrically coupled to the SMD platforms pad.
4. semiconductor module according to claim 3, wherein SMD platforms pad include solderable surface treatment below：Nickel (Ni) and it is golden (Au)；Ni, palladium (Pd) and Au；Tin (Sn)；Solder；Or organic solderability preservative (OSP).
5. semiconductor module according to claim 1, wherein the SMD components are coupled to described put down using solder projection Cushion.
6. semiconductor module according to claim 1, wherein the accumulation interconnection structure includes high-density multi-layered wiring layer.
7. semiconductor module according to claim 1, wherein：
It is in the area of coverage of the semiconductor grain and is partly not at the semiconductor die to the SMD components In the area of coverage of grain；And
At least one SMD platforms pad is positioned at the edge of the area of coverage of the semiconductor grain in the full molded structure On.
8. semiconductor module according to claim 1, further includes：
First out connector of the module, first out connector are adapted to be coupled to battery；With
Second connector of the module, second connector are adapted to be coupled to display.
9. semiconductor module according to claim 1 further includes the semiconductor in the full molded substrate part Crystal grain, the semiconductor grain can Complete tests before any SMD components are coupled to the SMD platforms pad.
10. a kind of semiconductor module, including：
Full molded substrate part, including flat surfaces, the full molded substrate part further include：
Semiconductor grain, the semiconductor grain include engagement pad,
Conductive column, the conductive column are coupled to the engagement pad and extend to the flat surfaces, and
Encapsulation object, the encapsulation object is set on the active surface, on four side surfaces and surrounds the conductive column, Described in conductive column end at the flat surfaces of the full molded substrate part from the encapsulation object expose；
Interconnection structure is accumulated, the accumulation interconnection structure includes the wiring layer being set on the full molded substrate part；With
SMD components, the SMD components are electrically coupled to the wiring layer.
11. semiconductor module according to claim 10, wherein the SMD components for being electrically coupled to the wiring layer also wrap It includes：
The SMD components including welding terminal；
The soldering paste being set on the wiring layer；And
When the welding terminal and the soldering paste contact, the welding terminal is arranged on the wiring layer simultaneously It is electrically coupled to the wiring layer.
12. semiconductor module according to claim 10, wherein the SMD components are coupled to using solder projection described Wiring layer.
13. semiconductor module according to claim 10, wherein：
It is in the area of coverage of the semiconductor grain and is partly not at the semiconductor die to the SMD components In the area of coverage of grain.
14. semiconductor module according to claim 10, further includes：
First out connector of the module, first out connector are adapted to be coupled to battery；With
Second connector of the module, second connector are adapted to be coupled to display.
Further include that described in the full molded substrate part is partly led 15. semiconductor module according to claim 10 Body crystal grain, the semiconductor grain can Complete tests before any SMD components are coupled to such SMD platforms pad.
16. a kind of method making semiconductor module, including：
Electrical interconnection is formed on semiconductor grain；
The semiconductor grain is sealed using encapsulation object to form the first built-in part, wherein the electrical interconnection is from the packet Seal object exposure；
Formation includes the accumulation interconnection structure of conductive RDL layer on first built-in part and is electrically connected to the electrical interconnection Part；
Form surface-mount devices (SMD) the platform pad for being electrically coupled to the conductive RDL layer；And
SMD components are coupled to the SMD platforms pad using surface mounting technique (SMT), to pass through the conductive column and described Interconnection structure is accumulated to provide being electrically connected between the SMD components and the semiconductor grain.
17. further including according to the method for claim 16, by the SMD platforms pad formed below：
Photoimageable solder mask material is set on the conductive RDL layer；
Opening is formed in the Photoimageable solder mask material on the conductive RDL layer；And
Apply solderable surface treatment below on the SMD platforms pad：Nickel (Ni) and gold (Au)；Ni, palladium (Pd) and Au； Tin (Sn)；Solder；Or organic solderability preservative (OSP).
18. according to the method for claim 16, wherein the SMD components are coupled to the SMD platforms pad further including：
By soldering paste screen painting on each of described SMD platforms pad；
The welding terminal of the SMD components is positioned on first built-in part so that welding terminal connects Touch the soldering paste on the SMD platforms pad；And
Soldering paste described in reflow by the SMD components to be coupled to the SMD platforms pad.
19. further including according to the method for claim 16, that any one of described SMD components are being coupled to described first Before built-in part, the semiconductor grain of the electrical testing in first built-in part.
20. further including according to the method for claim 16, that the SMD components are coupled to the SMD platforms pad so that institute It is in the area of coverage of the semiconductor grain with stating SMD components and is partly not at covering for the semiconductor grain In cover region.
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KR102127774B1 (en) 2020-06-29
KR20180084877A (en) 2018-07-25
HK1256963A1 (en) 2019-10-04

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