CN104836582B - Multi-stage D/A converter - Google Patents
Multi-stage D/A converter Download PDFInfo
- Publication number
- CN104836582B CN104836582B CN201410169145.4A CN201410169145A CN104836582B CN 104836582 B CN104836582 B CN 104836582B CN 201410169145 A CN201410169145 A CN 201410169145A CN 104836582 B CN104836582 B CN 104836582B
- Authority
- CN
- China
- Prior art keywords
- digital
- output signal
- output
- analog
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/661—Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
Abstract
The present invention provides Multi-stage D/A converters.A kind of circuit, the circuit include the first digital filter H (z), the second digital filter 1/ (1+H (z)), third digital filter, the first digital modulator, the second digital modulator and gain module.First digital filter is based on the first output of numeral input and the generation of the first digital output signal.First digital modulator is based on the first output and feedback error output the first digital output signal of generation and the output of the first error.First error is exported amplification predetermined ratio by gain module, so as to generate the output of the second error.Second digital modulator is based on the second output of the second error output generation and the output of third error.Second digital filter is based on the second output and generates the second digital output signal.Third wave filter is based on the output generation feedback error output of third error.
Description
Technical field
This invention relates generally to technical field of semiconductors, more particularly, to digital analog converter.
Background technology
Digital analog converter (DAC) is the device or circuit element for converting the digital data into analog signal.In some applications
In, numerical data includes the different digital codings of predetermined amount, and each in digital coding in analog signal only
One voltage or current value corresponds to.For example, at least one application, the 2 of N digit digital datasNA different digital coding pair
It should be in the 2 of corresponding analog signalNA different voltage or current value, wherein, N is positive integer.N digits digital data can be turned
The DAC for being changed to corresponding analog signal is also referred to as the DAC with N bit resolutions.In some applications, it is arranged as by having
There is provided corresponding 2NAt least the 2 of a different voltage or current valueNA passive or active electronic component is differentiated to realize with N
The DAC of rate.2NA passive or active electronic component mismatch can lead to the non-linear conversion error of the output analog signal of DAC.
Invention content
In order to solve the existing defects in the prior art, according to an aspect of the present invention, a kind of circuit is provided, is wrapped
It includes：First digital filter, has a z domain transfer function Hs (z), first digital filter configuration be based on numeral input and
The first output of first digital output signal generation；First digital modulator is configured to first output and feedback error
Output generates first digital output signal and the output of the first error；Gain module is configured to export first error
Amplify predetermined ratio k, so as to generate the output of the second error；Second digital modulator is configured to the second error output
The second output of generation and the output of third error；Second digital filter, have z domains transmission function 1/ (1+H (z)), described second
Digital filter configuration is based on described second output the second digital output signal of generation；And third digital filter, configuration
The feedback error output is generated to be based on the third error output.
In the circuit, the third digital filter has z domains transmission function z-1/k。
In the circuit, the ratio k is in the range of 2 to 16.
In the circuit, the z domain transfer function Hs (z) are z-1/(1-z-1)。
In the circuit, first digital modulator and second digital modulator are unit pulse width modulated numbers
Word modulator.
The circuit further includes：Interpolation filter, is configured to numerical data and the up-sampling ratio m generations number is defeated
Enter, the numerical data corresponds to the first sample frequency fs, the numeral input corresponds to the second sample frequency mfs, and m is big
In 1.
In the circuit, the up-sampling ratio m changes in the range of 10 to 128.
In the circuit, first digital filter, second digital filter, first digital modulator and
Second digital modulator is worked based on the clock frequency equal with second sample frequency.
The circuit further includes：First digital analog converter is configured to first digital output signal and generates the first mould
Intend output signal；Second digital analog converter is configured to second digital output signal and generates the second analog output signal；
Amplifier is configured to the second analog output signal of second analog output signal and scaling 1/k generation scalings；
And reconfiguration unit, the second analog output signal generation for being configured to first analog output signal and the scaling are heavy
The analog signal of structure.
The circuit further includes：First digital analog converter is configured to first digital output signal and generates the first mould
Intend output signal；Second digital-to-analogue converter is configured to second digital output signal and scaling 1/k generation scalings
The second analog output signal；And reconfiguration unit, it is configured to the of first analog output signal and the scaling
The analog signal of two analog output signals generation reconstruct.
According to another aspect of the present invention, a kind of circuit is provided, including：Digital circuit is configured to：Based on z domains
The numeral input of expression formula x (z) has truncated error-p1(z) the first digital modulator has truncated error-p2(z)
Two digital modulators and with the filter transfer function of z domains transmission function that is represented by H (z), generation is with z domains expression formula y1
(z) the first digital output signal and with z domains expression formula y2(z) the second digital output signal, y1(z)=x (z) H
(z)/(1+H(z))+(p1(z)-p2(z)·z-1/ k) (1/ (1+H (z))) and y2(z)=k (p2(z)/k-p1(z))(1/(1+
H(z)))；And digital analog interface circuit, it is configured to first digital output signal and second digital output signal
The analog signal of reconstruct of the generation with z domain expression formula y (z), and y (z)=y1(z)+y2(z)/k。
In the circuit, the ratio k changes in the range of 2 to 16.
In the circuit, the z domains transmission function of the filter transfer function H (z) is z-1/(1-z-1)。
In the circuit, first digital output signal is unit pulse bandwidth modulation signals, and described second is digital
Output signal is multidigit pulse width modulating signal.
In the circuit, the digital analog interface includes：First digital analog converter is configured to first numeral output
Signal generates the first analog output signal；Second digital analog converter is configured to second digital output signal generation the
Two analog output signals；Amplifier is configured to the of second analog output signal and scaling 1/k generation scalings
Two analog output signals；And reconfiguration unit, it is configured to the second mould of first analog output signal and the scaling
Intend the analog signal that output signal generates the reconstruct.
The circuit further includes：First digital analog converter is configured to first digital output signal and generates the first mould
Intend output signal；Second digital analog converter is configured to second digital output signal and scaling 1/k generation scalings
The second analog output signal；And reconfiguration unit, it is configured to the of first analog output signal and the scaling
The analog signal of two analog output signals generation reconstruct.
According to another aspect of the invention, it provides a method, including：Believed based on numeral input, the first numeral output
Number and the first z domain transfer function Hs (z) generation first output；Based on the described first output and feedback error output by the first number
Modulator generates first digital output signal and the output of the first error；First error is exported into amplification predetermined ratio k,
So as to generate the output of the second error；It is missed based on second error output by the second output of the second digital modulator generation and third
Difference output；Second digital output signal is generated based on the described second output and the 2nd z domains transmission function 1/ (1+H (z))；And base
The feedback error output is generated in third error output.
In the method, based on the 3rd z domains transmission function z-1/ k determines the feedback error output of generation.
In the method, the z domain transfer function Hs (z) are z-1/(1-z-1)。
This method further includes：The numeral input, the numerical data pair are generated based on numerical data and up-sampling ratio m
It should be in the first sample frequency fs, the numeral input corresponds to the second sample frequency mfs, and m is more than 1.
Description of the drawings
When reading in conjunction with the accompanying drawings, various aspects of the invention may be better understood by described in detail below.
It should be noted that according to the standard practices in industry, all parts are not drawn to scale.In fact, in order to clearly discuss, it is each
The size of component can be arbitrarily increased or be reduced.
Fig. 1 is the system block diagram of digital analog converter in accordance with some embodiments (DAC).
Fig. 2A is the noise shaper of DAC in accordance with some embodiments and pulse width modulation (PWM) digital-to-analogue (D/A) interface
The block diagram of circuit.
Fig. 2 B are the noise shaper of another DAC in accordance with some embodiments and the frame of PWM count mould (D/A) interface circuit
Figure.
Fig. 3 is the flow chart for the method that PWM DAC are operated according to some embodiments.
Specific embodiment
Disclosure below provides many different embodiments or examples for being used to implement the different characteristic of the present invention.Below
The specific example of component and arrangement is described to simplify the present invention.Certainly, these are only example, it is no intended to limit this hair
It is bright.For example, in the following description, above second component or the upper formation first component can include in a manner of being in direct contact
Form the embodiment of the first component and second component, and can also be included between the first component and second component can be formed it is attached
Made component so that the embodiment that the first component and second component are not directly contacted with.In addition, the present invention can weigh in various embodiments
Multiple reference number and/or letter.The repetition is for purposes of simplicity and clarity, and itself not indicate the various realities discussed
Apply the relationship between example and/or structure.
One or more embodiment according to the present invention, by the first digital modulator by the pulse code of multidigit over-sampling
Modulation (PCM) or pulse density modulated (PDM) signal is converted into a pwm signal and cutting based on the first digital modulator
Disconnected error (truncation error) converts thereof into multidigit pwm signal by the second digital modulator.In some embodiments
In, the truncated error of the first digital modulator is effectively eliminated by the ratio determined by circuit designers, and reduce by the
The truncated error of two digital modulators.
Fig. 1 is the system block diagram of DAC100 in accordance with some embodiments.DAC100 includes numerical portion and analog portion.
In numerical portion, DAC100 includes interpolation filter 110 and noise shaper 120.DAC100 also include bridge joint numerical portion and
The D/A interface circuits 130 of analog portion.In analog portion, DAC100 further includes low-pass filter 140.
Interpolation filter 110 receives numerical data N0And generation up-sampling (up-sample) numeral output N1.Numerical data
N0Correspond to sample frequency fsN position digital signals, wherein, N is positive integer.In some embodiments, numerical data N0It is
PCM signal.In some embodiments, numerical data N0It is PDM signals.In some embodiments, N becomes in the range of 16 to 24
Change.In some embodiments, sample frequency fsIt is to change in the range of 48kHz to 192kHz.Interpolation filter 110 is configured to
Based on numerical data N0With up-sampling ratio m generation up-sampling numeral outputs N1.In some embodiments, numeral output is up-sampled
N1It is also N PCM or PDM digital signals.Up-sampling numeral output N as a result,1With sample frequency mfsIt is corresponding.In some realities
It applies in example, up-sampling ratio m is more than 1.In some embodiments, up-sampling ratio m changes in the range of 10 to 128.One
In a little embodiments, in a frequency domain, interpolation filter 110 is used for numerical data N0Quantization noise from corresponding to numerical data N0
The narrower bandwidth of sample frequency be distributed to corresponding to up-sampling numeral output N1Sample frequency large bandwidth.
Noise shaper 120 is multistage noise shaper.Noise shaper 120 receives up-sampling numeral output N1As making an uproar
The numeral input of sound reshaper 120.Noise shaper 120 generates numeral output N2To be supplied to D/A interface circuits 130.One
In a little embodiments, noise shaper 120 at least has the first PWM count word modulator (for example, 220 in Fig. 2A) and the 2nd PWM
Digital modulator (for example, 240 in Fig. 2A).Digital output signal N2Usually than up-sampling numeral output N1With less position
(that is, lower resolution ratio), wherein, truncated error is attributable to the operation of noise shaper 120.In some embodiments, number
Word exports N2Including at least the first digital output signal and the second digital output signal.First digital output signal is based on the first number
The output of word modulator.Second digital output signal is based on cutting as the first digital modulator handled by the second digital modulator
Disconnected error.In some embodiments, in a frequency domain, noise shaper 120 is pressed down by pushing most of noise to higher frequency
Low frequency noise processed.
D/A interface circuits 130 are configured to numeral output N2Generate the analog signal S of reconstruct1.It is further with reference to Fig. 2A
Show the detail about noise shaper 120 and D/A interface circuits 130.
Low-pass filter (LPF) 140 passes through the analog signal S to reconstruct1Carry out low-pass filtering generation analog output signal
SOUT.In some embodiments, LPF140 inhibits the analog signal S of reconstruct1In noise, the frequency of the noise is more than digital number
According to N0Nyquist frequency (that is, 0.5fs)。
Fig. 2A is the block diagram of the noise shaper 200A and D/A interface circuit 200B of DAC in accordance with some embodiments.One
In a little embodiments, noise shaper 200A can be used as the noise shaper 120 in Fig. 1.In some embodiments, D/A interfaces electricity
Road 200B can be used as the D/A interface circuits 130 in Fig. 1.Z domains expression formula or transmission function based on them are shown in Fig. 2A
Each signal.
Noise shaper 200A includes sum unit 202, sum unit 204, first the 210, first number of digital filter
Modulator 220, gain module 230, the second digital modulator 240, the second digital filter 250 and third digital filter 260.
Noise shaper 200A receives the numeral input represented by z domain expression formula x (z).In some embodiments, numeral input x (z)
Corresponding to the up-sampling numeral output N in Fig. 11.Noise shaper 200A is generated by z domains expression formula y1(z) and y2(z) it is represented
Digital output signal.
Sum unit 202 generates the output represented by a (z), and numeral output is subtracted based on the numeral input x (z) in z domains
Signal y1(z) a (z) is determined.First digital filter 210 has the z domains transmission function represented by H (z), and configuration is made a living
Into the output represented by b (z), b (z) is determined based on H (z) and a (z).
Sum unit 204 generates the output represented by d (z), and d (z) is that the first digital filter 210 is come from z domains
B (z) with from third digital filter 260 feedback error output c (z) and.First digital modulator 220 is based on d (z)
Generate the first digital output signal y1(z) and the first error output-p1(z)。
First digital modulator 220 includes sum unit 222, sum unit 224 and cropper (truncator) 226.It asks
D (z) and digit pulse width-modulated carrier 228, and output life of the cropper 226 based on sum unit 222 are received with unit 222
Into the first digital output signal y1(z).In some embodiments, cropper 226 is unit cropper, and by sum unit 222
PWM count word modulator is configured to cropper 226.Sum unit 224 receives d (z) and the first digital output signal y1(z) it is and raw
Into the first error output-p1(z)。
Gain module 230 includes amplifying unit 232, which receives the first error output-p1(z) and with pre-
Certainty ratio (and sometimes referred to as " gain ") the first error output-p of k amplifications1(z), so as to generate by g (z)=- kp1Z institutes table
The the second error output shown.
Second digital modulator 240 includes sum unit 242, sum unit 244 and cropper 246.Sum unit 242 connects
G (z) and digit pulse width-modulated carrier 248 are received, and output of the cropper 246 based on sum unit 242 is generated by o (z) institutes
The output of expression.In some embodiments, cropper 246 is unit cropper, and sum unit 242 and cropper 246 are matched
It is set to PWM count word modulator.Sum unit 244 receives g (z) and output o (z) and generation third error output-p2(z)。
Second digital filter 250 has the z domains transmission function represented by 1/ (1+H (z)), and is configured to 1/ (1
+ H (z)) and the second digital output signal y of o (z) generations2(z).In some embodiments, output o (z) is unit pwm signal, and
Second digital output signal y2(z) it is multidigit pwm signal.
Third digital filter 260 includes being configured to transmission function z-1The delay cell 262 and amplifying unit of/k
264.Therefore, third digital filter 260 is generated by c (z)=- z-1/k·p2(z) the feedback error output represented by.
Based on the above, noise shaper 200A is configured to the first numeral output y of generation1(z) and the second numeral output y2
(z)：
y1(z)=x (z) H (z)/(1+H (z))+(p1(z)-p2(z)·z-1/ k) (1/ (1+H (z))) and
y2(z)=k (p2(z)/k-p1(z))(1/(1+H(z)))。
In some embodiments, H (z) is single order or multistage lowpass digital filter.In some embodiments, H (z) is z-1/(1-z-1).In some embodiments, k is the positive integer in the range of 2 to 16.In some embodiments, k is 2 times
Number.
In some embodiments, noise shaper 200A is realized by hard-wired logic circuit.In some embodiments
In, based on the first digital filter of clock frequency operation equal to the second sample frequency mfs
210th, the second digital filter 250, the first digital modulator 220 and the second digital modulator 240.In some implementations
In example, noise shaper 200A is realized by performing the digital signal processing unit of one group of instruction.
D/A interface circuits 200B includes the first DAC units 272, the 2nd DAC units 274, amplifier 276 and reconfiguration unit.
First DAC units 272 are configured to the first digital output signal y1(z) the first analog output signal S is generated21。
In some embodiments, the first DAC units 272 are unit PWM DAC.In some embodiments, DAC units 272 are switch electricity
Appearance type DAC.In some embodiments, DAC272 is current drive-type DAC.
2nd DAC units 274 are configured to the second digital output signal y2(z) the second analog output signal S is generated22。
In some embodiments, the 2nd DAC units are multidigit DAC.In some embodiments, DAC units 274 are switching capacity type DAC.
In some embodiments, DAC units 274 are current drive-type DAC.
Amplifier 276 is configured to the second analog output signal S22With the second simulation of scaling 1/k generation scalings
Output signal S23.Reconfiguration unit 278 is configured to the first analog output signal S21With the second analog output signal S of scaling23's
With the analog signal S of generation reconstruct24.In some embodiments, the analog signal S of reconstruct24It can be used as the mould of the reconstruct in Fig. 1
Intend signal S1。
Based on the above, the analog signal S of reconstruct24With z domain expression formula y (z)：
Y (z)=y1(z)+y2(z)/k and
Y (z)=x (z) H (z)/(1+H (z))+p2(z)/k((1-z-1)/(1+H(z)))。
Therefore, the analog signal S of the reconstruct represented by y (z)24With the module gain at about low frequency.Also, disappear
In addition to error p1(z), and error p is reduced2(z) predetermined ratio k.
Fig. 2 B are the block diagrams of the noise shaper 200A and D/A interface circuit 200C of another DAC in accordance with some embodiments.
Identical reference label is given with the same or similar component in Fig. 2A in Fig. 2 B, and omits their datail description.
Compared with the D/A interface circuits 200B in Fig. 2A, D/A interface circuits 200C has DAC units 282, the DAC units
282 are configured to the second digital output signal y2(z) and scaling 1/k generations scale the second analog output signal S23.It changes
Sentence is talked about, and the function of the amplifier 276 in Fig. 2A is integrally realized in DAC units 282.In some embodiments, when DAC is mono-
When member 282 is switching capacity type DAC, implement the scaling of signal by the way that size or the ratio of capacitor is configured；Or when DAC units
282 when being current drive-type DAC, implements the scaling of signal by the way that size or the ratio of current element is configured.
Fig. 3 is the method 300 that DAC (such as with reference to the DAC shown in Fig. 1, Fig. 2A and Fig. 2 B) is operated according to some embodiments
Flow chart.It should be understood that additional operations can be implemented before, during and/or after the method 300 being shown in FIG. 3, and
This can simply just describe some other techniques.
As shown in figures 1 and 3, technique 300 starts from operation 310, wherein, based on numerical data N0With up-sampling ratio m
Generate numeral input N1.Numerical data N0Corresponding to the first sample frequency fs, numeral input N1Corresponding to the second sample frequency m
Fs, and m is more than 1.In some embodiments, fsIn the range of 48kHz to 192kHz.In some embodiments, ratio is up-sampled
Example m changes in the range of 10 to 128.In some embodiments, numeral input N1It is N PDM signals or PCM signal.One
In a little embodiments, N changes in the range of 16 to 24.
As illustrated in figs. 2 a and 3, technique 300 proceeds to operation 320.Wherein, based on represented by z domain expression formula x (z)
Numeral input N1, the first digital output signal y1(z) and the first z domain transfer function Hs (z) generate the letter with z domain expression formula b (z)
Number.In some embodiments, z domain transfer function Hs (z) are z-1/(1-z-1)。
Technique 300 proceeds to operation 330, wherein, based on signal b (z) and feedback error signal c (z) by digital modulator
220 the first digital output signal y of generation1(z) and the first error signal-p1(z).In some embodiments, the first numeral output is believed
Number y1(z) it is unit pwm signal.
Technique proceeds to operation 340, wherein, the first error signal-p is amplified with predetermined ratio k1(z), so as to generate second
Error signal g (z).In some instances, ratio k is in the range of 2 to 16.In some embodiments, ratio k is 2 multiple.
Technique proceeds to operation 350, wherein, the second letter is generated by digital modulator 240 based on the second error signal g (z)
Number o (z) and third error signal-p2(z).In some embodiments, second signal o (z) is unit pwm signal.
Technique proceeds to operation 360, wherein, it is raw based on second signal o (z) and the 2nd z domains transmission function 1/ (1+H (z))
Into the second digital output signal y2(z).In some embodiments, the second digital output signal y2(z) it is multidigit pwm signal.
Technique proceeds to operation 370, wherein, based on third error signal-p2(z) and z domains transmission function z-1/ k generations are anti-
Feedforward error signal c (z).
According to one embodiment, a kind of circuit includes the first digital filter with z domain transfer function Hs (z), the first number
Word modulator, gain module, the second digital modulator, have z domains transmission function 1/ (1+H (z)) the second digital filter with
And third digital filter.First digital filter configuration is defeated based on numeral input and the generation first of the first digital output signal
Go out.First digital modulator is configured to the first output and feedback error output the first digital output signal of generation and first misses
Difference output.Gain module is configured to amplify the output of the first error with predetermined ratio k, so as to generate the output of the second error.Second number
Word modulator is configured to the second output of the second error output generation and the output of third error.Second digital filter configuration is
Based on second output the second digital output signal of generation.Third digital filter configuration is to export generation feedback based on third error
Error exports.
According to another embodiment, a kind of circuit includes digital circuit and digital-to-analogue interface circuit.Digital circuit is configured to
Numeral input with z domain expression formula x (z), with truncated error-p1(z) the first digital modulator has truncated error-p2
(z) the second digital modulator and with the filter transfer function of z domains transmission function represented by H (z), generation is with z domains table
Up to formula y1(z) the first digital output signal and with z domains expression formula y2(z) the second digital output signal,
y1(z)=x (z) H (z)/(1+H (z))+(p1(z)-p2(z)·z-1/ k) (1/ (1+H (z))) and
y2(z)=k (p2(z)/k-p1(z))(1/(1+H(z)))。
Digital analog interface circuit configuration is to have z domains table based on the first digital output signal and the generation of the second digital output signal
Up to the analog signal of the reconstruct of formula y (z), and
Y (z)=y1(z)+y2(z)/k。
According to another embodiment, a kind of method includes transmitting based on numeral input, the first digital output signal and the first z domains
The first output of function H (z) generations.It is defeated by the first number of the first digital modulator generation based on the first output and feedback error output
Go out signal and the output of the first error.First error is exported into amplification predetermined ratio k, so as to generate the output of the second error.Based on
The output of two errors is exported by the second output of the second digital modulator generation and third error.It is passed based on the second output and the 2nd z domains
Delivery function 1/ (1+H (z)) generates the second digital output signal.Generation feedback error output is exported based on third error.
Foregoing has outlined the features of several embodiments so that the present invention may be better understood in those of ordinary skill in the art
Various aspects.It will be understood by those skilled in the art that they can easily design using based on the present invention
Or modification is for performing other process and structures with introducing the identical purpose of embodiment and/or realization same advantage at this.
Those of ordinary skill in the art should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and
In the case of without departing substantially from the spirit and scope of the present invention, they can make a variety of variations, replace and change herein.
Claims (20)
1. a kind of d convertor circuit, including：
First digital filter, has a z domain transfer function Hs (z), first digital filter configuration be based on numeral input and
The first output of first digital output signal generation；
First digital modulator, is configured to first output and feedback error output generates the first numeral output letter
Number and the first error output；
Gain module is configured to first error exporting amplification predetermined ratio k, so as to generate the output of the second error；
Second digital modulator is configured to the second output of the second error output generation and the output of third error；
Second digital filter, has z domains transmission function 1/ (1+H (z)), and second digital filter configuration is based on described
Second output the second digital output signal of generation；And
Third digital filter is configured to the third error output and generates the feedback error output.
2. d convertor circuit according to claim 1, wherein, there is the third digital filter z domains to transmit letter
Number z-1/k。
3. d convertor circuit according to claim 1, wherein, the ratio k is in the range of 2 to 16.
4. d convertor circuit according to claim 1, wherein, the z domain transfer function Hs (z) are z-1/(1-z-1)。
5. d convertor circuit according to claim 1, wherein, first digital modulator and second number
Modulator is unit pulse width modulated digital modulator.
6. d convertor circuit according to claim 1, further includes：
Interpolation filter, is configured to numerical data and up-sampling ratio m generates the numeral input, the numerical data pair
It should be in the first sample frequency fs, the numeral input corresponds to the second sample frequency mfs, and m is more than 1.
7. d convertor circuit according to claim 6, wherein, the up-sampling ratio m is in the range of 10 to 128
Variation.
8. d convertor circuit according to claim 6, wherein, first digital filter, second number
Wave filter, first digital modulator and second digital modulator are based on the clock equal with second sample frequency
Frequency works.
9. d convertor circuit according to claim 1, further includes：
First digital analog converter is configured to first digital output signal and generates the first analog output signal；
Second digital analog converter is configured to second digital output signal and generates the second analog output signal；
Amplifier is configured to the second simulation output of second analog output signal and scaling 1/k generation scalings
Signal；And
Reconfiguration unit is configured to the second analog output signal generation weight of first analog output signal and the scaling
The analog signal of structure.
10. d convertor circuit according to claim 1, further includes：
First digital analog converter is configured to first digital output signal and generates the first analog output signal；
Second digital-to-analogue converter is configured to the second of second digital output signal and scaling 1/k generation scalings
Analog output signal；And
Reconfiguration unit is configured to the second analog output signal generation weight of first analog output signal and the scaling
The analog signal of structure.
11. a kind of d convertor circuit, including：
Digital circuit is configured to：
Based on the numeral input with z domain expression formula x (z), with truncated error-p1(z) the first digital modulator has and cuts
Disconnected error-p2(z) the second digital modulator and with the filter transfer function of z domains transmission function represented by H (z), generates
With z domains expression formula y1(z) the first digital output signal and with z domains expression formula y2(z) the second numeral output letter
Number,
y1(z)=x (z) H (z)/(1+H (z))+(p1(z)-p2(z)·z-1/ k) (1/ (1+H (z))) and
y2(z)=k (p2(z)/k-p1(z))(1/(1+H(z)))；And
Digital analog interface circuit, being configured to first digital output signal and second digital output signal generation has
The analog signal of the reconstruct of z domain expression formula y (z), and
Y (z)=y1(z)+y2(z)/k。
12. d convertor circuit according to claim 11, wherein, ratio k changes in the range of 2 to 16.
13. d convertor circuit according to claim 11, wherein, the z domains of the filter transfer function H (z) are transmitted
Function is z-1/(1-z-1)。
14. d convertor circuit according to claim 11, wherein, first digital output signal is unit pulse
Bandwidth modulation signals, and second digital output signal is multidigit pulse width modulating signal.
15. d convertor circuit according to claim 11, wherein, the digital analog interface includes：
First digital analog converter is configured to first digital output signal and generates the first analog output signal；
Second digital analog converter is configured to second digital output signal and generates the second analog output signal；
Amplifier is configured to the second simulation output of second analog output signal and scaling 1/k generation scalings
Signal；And
Reconfiguration unit is configured to the second analog output signal generation institute of first analog output signal and the scaling
State the analog signal of reconstruct.
16. d convertor circuit according to claim 11, further includes：
First digital analog converter is configured to first digital output signal and generates the first analog output signal；
Second digital analog converter is configured to the second of second digital output signal and scaling 1/k generation scalings
Analog output signal；And
Reconfiguration unit is configured to the second analog output signal generation weight of first analog output signal and the scaling
The analog signal of structure.
17. a kind of operating method of d convertor circuit, including：
Based on the first output of numeral input, the first digital output signal and the first z domain transfer function Hs (z) generation；
Based on the described first output and feedback error output by the first digital modulator generate first digital output signal and
First error exports；
First error is exported into amplification predetermined ratio k, so as to generate the output of the second error；
It is exported based on second error output by the second output of the second digital modulator generation and third error；
Second digital output signal is generated based on the described second output and the 2nd z domains transmission function 1/ (1+H (z))；And
The feedback error output is generated based on third error output.
18. the operating method of d convertor circuit according to claim 17, wherein, based on the 3rd z domains transmission function z-1/ k determines the feedback error output of generation.
19. the operating method of d convertor circuit according to claim 17, wherein, the z domain transfer function Hs (z)
It is z-1/(1-z-1)。
20. the operating method of d convertor circuit according to claim 17, further includes：
The numeral input is generated based on numerical data and up-sampling ratio m, the numerical data corresponds to the first sample frequency
fs, the numeral input corresponds to the second sample frequency mfs, and m is more than 1.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/177,519 | 2014-02-11 | ||
| US14/177,519 US9136865B2 (en) | 2014-02-11 | 2014-02-11 | Multi-stage digital-to-analog converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104836582A CN104836582A (en) | 2015-08-12 |
| CN104836582B true CN104836582B (en) | 2018-06-08 |
Family
ID=53775868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410169145.4A Active CN104836582B (en) | 2014-02-11 | 2014-04-24 | Multi-stage D/A converter |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US9136865B2 (en) |
| CN (1) | CN104836582B (en) |
| TW (1) | TWI538412B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9136865B2 (en) * | 2014-02-11 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stage digital-to-analog converter |
| US9979445B2 (en) | 2016-07-15 | 2018-05-22 | Futurewei Technologies, Inc. | Digital to analog converter apparatus, system, and method with quantization noise that is independent of an input signal |
| US11005493B2 (en) | 2017-04-25 | 2021-05-11 | Telefonaktiebolaget Lm Ericsson (Publ) | Digital-to-analog conversion circuit |
| CN109150187A (en) * | 2018-08-02 | 2019-01-04 | 南京理工大学 | A kind of D/A converting circuit based on multiple bit digital signal |
| CN113519124A (en) * | 2019-03-28 | 2021-10-19 | 松下知识产权经营株式会社 | Digital filter, A/D converter, sensor processing circuit, and sensor system |
| US11870453B2 (en) * | 2021-11-22 | 2024-01-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuits and methods for a noise shaping analog to digital converter |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1714502A (en) * | 2002-11-22 | 2005-12-28 | 皇家飞利浦电子股份有限公司 | Pulse width-modulated noise shaper |
| CN101317169A (en) * | 2005-09-26 | 2008-12-03 | Ess技术公司 | Low noise digital to pulse width modulated converter with audio applications |
| CN101611543B (en) * | 2006-12-27 | 2012-10-10 | 夏普株式会社 | A delta-sigma modulation digital-analog converter, digital signal processing method, and AV device |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5369403A (en) * | 1992-09-01 | 1994-11-29 | The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University | Dual quantization oversampling digital-to-analog converter |
| US5323157A (en) | 1993-01-15 | 1994-06-21 | Motorola, Inc. | Sigma-delta digital-to-analog converter with reduced noise |
| DE19854124C1 (en) * | 1998-11-24 | 2000-08-24 | Bosch Gmbh Robert | Sigma-Delta D / A converter |
| JP4209035B2 (en) * | 1999-05-28 | 2009-01-14 | 株式会社ルネサステクノロジ | ΔΣ modulator, DA converter, and AD converter |
| US6920182B2 (en) * | 2001-01-09 | 2005-07-19 | Microtune (Texas), L.P. | Delta-sigma modulator system and method |
| JP4530119B2 (en) * | 2001-06-08 | 2010-08-25 | ルネサスエレクトロニクス株式会社 | Digital ΔΣ modulator and D / A converter using the same |
| FR2840471A1 (en) * | 2002-05-28 | 2003-12-05 | St Microelectronics Sa | DIGITAL-DIGITAL SIGMA-DELTA MODULATOR, AND DIGITAL FREQUENCY SYNTHESIZER INCORPORATING SAME |
| JP3748543B2 (en) * | 2002-08-12 | 2006-02-22 | ローム株式会社 | Variable order type delta-sigma modulator and DA converter |
| CN1914806A (en) * | 2004-01-28 | 2007-02-14 | 皇家飞利浦电子股份有限公司 | A DA-converter system and a method for converting a multi-bit digital signal to an analog signal |
| JP4237230B2 (en) * | 2007-01-22 | 2009-03-11 | パナソニック株式会社 | Pulse width modulation method and digital-analog converter using the same |
| US7432841B1 (en) * | 2007-05-29 | 2008-10-07 | Texas Instruments Incorporated | Delta-sigma analog-to-digital converter with pipelined multi-bit quantization |
| US7868798B2 (en) * | 2009-03-31 | 2011-01-11 | Lsi Corporation | Methods and apparatus for whitening quantization noise in a delta-sigma modulator using dither signal |
| US7969340B2 (en) * | 2009-07-22 | 2011-06-28 | Mediatek Inc. | Noise-shaped segmented digital-to-analog converter |
| US7903015B1 (en) * | 2009-08-24 | 2011-03-08 | Texas Instruments Incorporated | Cascaded DAC architecture with pulse width modulation |
| US8299946B2 (en) | 2010-02-03 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Noise shaping for digital pulse-width modulators |
| US8031096B2 (en) * | 2010-02-18 | 2011-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | High resolution delta-sigma digital-to-analog converter |
| WO2012127579A1 (en) * | 2011-03-18 | 2012-09-27 | 富士通株式会社 | Mash sigma-delta modulator and d/a converter circuit |
| US8325074B2 (en) | 2011-03-22 | 2012-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and circuit for continuous-time delta-sigma DAC with reduced noise |
| US8698663B2 (en) * | 2012-08-29 | 2014-04-15 | Telefonaktiebolaget L M Ericsson (Publ) | Digital analog converter |
| US9136865B2 (en) * | 2014-02-11 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stage digital-to-analog converter |
-
2014
- 2014-02-11 US US14/177,519 patent/US9136865B2/en not_active Expired - Fee Related
- 2014-04-24 CN CN201410169145.4A patent/CN104836582B/en active Active
- 2014-12-25 TW TW103145538A patent/TWI538412B/en active
-
2015
- 2015-09-11 US US14/851,263 patent/US9525429B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1714502A (en) * | 2002-11-22 | 2005-12-28 | 皇家飞利浦电子股份有限公司 | Pulse width-modulated noise shaper |
| CN101317169A (en) * | 2005-09-26 | 2008-12-03 | Ess技术公司 | Low noise digital to pulse width modulated converter with audio applications |
| CN101611543B (en) * | 2006-12-27 | 2012-10-10 | 夏普株式会社 | A delta-sigma modulation digital-analog converter, digital signal processing method, and AV device |
Also Published As
| Publication number | Publication date |
|---|---|
| US9525429B2 (en) | 2016-12-20 |
| TWI538412B (en) | 2016-06-11 |
| US20150229323A1 (en) | 2015-08-13 |
| US20160006451A1 (en) | 2016-01-07 |
| CN104836582A (en) | 2015-08-12 |
| US9136865B2 (en) | 2015-09-15 |
| TW201539987A (en) | 2015-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104836582B (en) | Multi-stage D/A converter | |
| EP2843841B1 (en) | Method and device for driving digital speaker based on code conversion | |
| CN104579346B (en) | Analog-digital converter | |
| EP2263355B1 (en) | High resolution digital modulator by switching between discrete PWM or PPM values | |
| US7058464B2 (en) | Device and method for signal processing | |
| Li et al. | A 21-GS/s single-bit second-order delta–sigma modulator for FPGAs | |
| KR20170083109A (en) | System and method for generating a multi-band signal | |
| CN105356884A (en) | Sensor readout circuit based on Sigma-Delta analog-digital converter | |
| EP1653605B1 (en) | Noise shaper for shaping a power spectral density of an error signal and method therefor | |
| US7061415B2 (en) | Word length reduction circuit | |
| CN110945783B (en) | Distortion reducing quantizer circuit, method for reducing distortion noise, and digital transmitter | |
| Vanderkooy et al. | Why 1-bit sigma-delta conversion is unsuitable for high-quality applications | |
| TWI523413B (en) | System and method for amplifying a digital input signal to generate an analog output signal | |
| TWI504161B (en) | System and method of digital-to-analog converter | |
| Tavangaran et al. | Continuous time digital systems with asynchronous sigma delta modulation | |
| CN113497746B (en) | Fieldbus transmitter/receiver interface, system having the same, and encoding method | |
| US10861433B1 (en) | Quantizer | |
| CN1878000B (en) | Digital-to-analog converter | |
| CN104639097A (en) | Digital audio PDM (pulse duration modulation) signal DC (direct current) filter circuit | |
| CN101145785A (en) | An over-sampling increment modulation method and device | |
| Kong et al. | A power-efficient digital amplifier using input dependent bit flipping for portable audio systems | |
| Tariq et al. | An iterative LMI algorithm for quantization noise reduction in ΔΣ modulators | |
| CN107222216A (en) | The second order continuous-time SD analog-digital converters coupled using self noise | |
| US10566986B2 (en) | Converting module and converting circuit | |
| Shukla et al. | Comparative Analysis of Decimation Approach of Single Stage Discrete Time Sigma-Delta modulator using Simulink |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |