CN104836464B - Neutral-point-potential balance control device and method for direct current side of VIENNA rectifier - Google Patents

Abstract

The invention discloses a neutral-point-potential control method for a direct current side of a three-phase three-level rectifier and a neutral-point-potential control system for direct current side of the three-phase three-level rectifier, which are applied to digital one-cycle control. The principle of the control method is as follows: firstly collecting a current value of an input side of the rectifier and voltage values of an upper capacitor and a lower capacitor at the direct current side, then calculating an integral initial value of each period in the one-cycle control so as to control the duty ratio of a three-phase switch tube, thereby balancing the neutral-point-potential of the direct current side. A core control system is composed of a DSP and an FPGA. The DSP is mainly used for calculating a zero sequence duty ratio, carrying out PI control over the voltage differences of the upper capacitor and the lower capacitor at the direct current side, calculating the integral initial value of a single cycle, communicating with an upper computer, etc. The FPGA is mainly used for collecting data, judging failures, protecting, realizing the one-cycle control method and the like. The method has the characteristics that the algorithm is simple and easy to realize, the hardware cost is low and the control effect is excellent.

Description

A kind of VIENNA rectifier DC side neutral-point-potential balance control device and method

Technical field

The present invention relates to electric and electronic technical field, and in particular to a kind of VIENNA for being applied to the control of digital monocyclic phase is whole Stream device DC side neutral-point potential balance control method and system.

Background technology

With the fast development of Power Electronic Technique, the use of non-linear element is filled with substantial amounts of harmonic wave to electrical network.For This problem is solved, circuit of power factor correction is more and more applied in power electronic equipment.VIENNA rectifier It is a kind of outstanding three-phase tri-level power factor corrective rectifier, with simple structure easy care, number of switches be few, power device Part stress is little, without output voltage it is straight-through dangerous the advantages of.

One-cycle control (One Cycle Control, abbreviation OCC) is to be added by the U.S. earlier 1990s A kind of new PWM control technologies that Keyue professors M.Smedley of state university propose, its basic thought is by controlling electricity The dutycycle on road carrys out mean value of the controlling switch amount in a switch periods and is equal to or is proportional to reference quantity.The control of simulation monocycle Technology processed is only capable of achieving the purpose of PFC without the need for multiplier by rest-set flip-flop, reset integrator and comparator, It is a kind of technology that big signal nonlinear switching is converted to linear switch.Compared with traditional analog one-cycle control, base Have a clear superiority in the digital monocyclic phase control technology of DSP+FPGA.Mainly include：1) control is more flexible, is deriving After the Duty ratio control equation of system, may be programmed according to equation and realize digital algorithm；2) it is easier in combination with other control modes, Constitute complex controll to improve systematic entirety energy；3) noise antijamming capability is strong；4) peripheral hardware integrated level is higher.

Neutral balance problem is the intrinsic problem of VIENNA rectifier.Realizing the control strategy of neutral point voltage balance mainly has Two kinds, a kind of is based on space vector pulse width modulation (Space Vector PWM, the SVPWM) method of space vector, another kind It is based on sinusoidal pulse width modulation (Carrier-based PMW, the CBPWM) method of carrier wave.In SVPWM method, mainly There is following several method：1) open loop is passively controlled：In each new switch periods, the positive and negative state of small vector is changed.This The method of kind can preferably control midpoint potential only in the case of balanced load, and its dynamic adjustment characteristic is bad；2) it is stagnant ring-like Control：It is at present using a kind of most closed loop control methods, on detection is basic per phase current direction, by selecting little arrow Measuring positive and negative state makes midpoint potential towards the rightabout in uneven direction to select.The shortcoming of this method is exactly have 1/ in electric current The ripple of 2 switching frequencies；3) Active control：The modulation factor that this method passes through control electric current, needs to detect midpoint potential not The size of balance and the amplitude of phase current, benefit is exactly the ripple without 1/2 switching frequency, but is opened due to increased others Off status is so as to increased switching loss, and the typically no Hysteresis control of this method is so reliable.In SPWM modulator approaches, in The algorithm of point voltage balance is mostly to be realized by injecting zero-sequence component in three-phase modulations ripple.But zero-sequence component Selection need very high skill, the calculating of zero-sequence component to generally require three-phase reference voltage, output current, dc-link capacitance The parameter such as voltage and capacitance, substantial amounts of parameter make the calculating of zero-sequence component become complexity be also unfavorable for real-time control system Realize, while increased cost.

The content of the invention

Goal of the invention：In order to overcome the deficiencies in the prior art, the present invention to provide a kind of VIENNA rectifier direct current Side neutral-point-potential balance control apparatus and method, the neutral balance for more optimally solving existing VIENNA rectifier is asked Topic.

Technical scheme：For achieving the above object, the technical solution used in the present invention is：

A kind of VIENNA rectifier DC side neutral-point potential balance control method, comprises the following steps：

The input side three-phase current i of step one, collection VIENNA rectifier_a、i_b、i_c, input side three-phase voltage V_as、V_bs、 V_csWith DC voltage value V_dc；Upper and lower capacitance voltage value V of collection DC side_c1、V_c2；

Step 2, by input side three-phase current i_a、i_b、i_c, input side three-phase voltage V_as、V_bs、V_csWith DC voltage value V_dc Bring the sinusoidal component d that following formula obtains dutycycle into_a、d_b、d_c：

Wherein, L_a、L_b、L_cThe respectively Inductor of a, b, c three-phase；

By dutycycle sinusoidal component d_a、d_b、d_cBring following formula into obtain switching zero sequence dutycycle d₀：

By upper and lower capacitance voltage value V of DC side_c1、V_c2Make difference and carry out PI controls, P, I parameter is entered with reference to following formula relational expression Row design, obtains PI controlled output voltage V_m2：

In formula, C=C₁=C₂For DC bus capacitor, △ V_dc=V_c1-V_c2For the upper and lower capacitance voltage difference of DC side；

Step 3, utilization switch zero sequence dutycycle d₀With PI controlled output voltage V_m2Calculate according to the following formula and obtain digital monocyclic Phase controls the integration initial value Λ in each cycle_k：

In above formula,

i_kFor input side three-phase current, k takes respectively a, b, c, R_sFor alternating current sampling resistor；

Using the integral way with symmetry characteristic, from the integration initial value Λ in each cycle_kStart integration to carrier wave peak Direct reduction, to zero, but is not decremented to the integration initial value Λ in the cycle after value 1_k, complete the symmetric integral mistake of a cycle Journey.The modulated process can be considered as the synthesis of rising edge modulation and trailing edge modulation, with average current input and input voltage The features such as being directly proportional, reduce odd harmonic.

Step 4, the digital monocyclic phase control in, DC voltage reference value is deducted into the upper and lower capacitance voltage value of DC side The difference for obtaining afterwards obtains PI controlled output voltage V through PI controls_m1, by V_m1It is multiplied to adjustment and adjusts with modulating wave after inverted The amplitude of ripple processed；

Step 5, will adjustment amplitude after modulating wave input comparator, with monocycle carrier wave be compared output PWM letter Number.In traditional carrier modulating method, the generation of monocycle carrier wave and modulating wave is completed in the middle of a processor, and of the invention It is above-mentioned the function being related in carrier modulation is divided in two controllers, there is same effect with traditional OCC, but will A large amount of multiplyings work in FPGA is transferred in the middle of DSP, reduces the operand of FPGA, also causes DSP to be good at computing Advantage is played, and the arithmetic speed for making system is improved.

The present invention is using integration initial value Λ_kControlling switch dutycycle, so as to control neutral-point potential balance.Adjust controlled zero Sequence dutycycle introduces feedforward control, while feedback regulation effect is played in DC capacitor voltage difference PI controls.Therefore number is adjusted Word OCC integration starting points can just realize the balance of VIENNA rectifier DC side midpoint potential.

Said method can be realized based on a kind of VIENNA rectifier DC side neutral-point-potential balance control device, the device Including FPGA and DSP；Comprising operation of power networks data acquisition module and one circle control module in the FPGA, wrap in the DSP The computing module of dutycycle containing zero sequence, capacitance voltage difference PI control modules, the digital monocyclic phase control integration calculation of initial value module and Modulating wave range-adjusting module；The FPGA collection operation of power networks data are simultaneously transmitted to DSP, and the DSP is according to the electrical network for obtaining Service data calculates the integration initial value Λ for the acquisition digital monocyclic phase controlling each cycle_kAnd transmit the monocycle into FPGA control Molding block, one circle control module generates monocycle carrier wave and carries out duty cycle of switching control.

Beneficial effect：

The technical solution used in the present invention is a kind of being applied in the VIENNA rectifier DC side of digital monocyclic phase control Point potential control method, the upper and lower capacitance voltage value in the method collection rectifier DC side is made to carry out PI controls after difference, while meter The switch zero sequence dutycycle related to midpoint potential is calculated, PI results and switch zero sequence dutycycle are sent into into numeral OCC integrations Calculation of initial value module, the integration initial value that the result obtained after calculating is controlled into each cycle as digital OCC, is controlled with this The dutycycle of each switch periods is made, and then controls neutral-point potential balance.There is the method algorithm simply easily to realize, hardware cost The good advantage of low, control effect.

Description of the drawings

Fig. 1 is VIENNA rectifier main circuit topology figure；

Fig. 2 is DSP+FPGA core controller functional block diagrams；

Fig. 3 is digital monocyclic phase control integration calculation of initial value module diagram；

Fig. 4 is neutral-point-potential balance control schematic diagram；

Fig. 5 is the capacitance voltage of DC side two entirety simulation waveform；

Fig. 6 is the capacitance voltage simulation waveform partial enlarged drawing of DC side two；

Fig. 7 is the overlapping simulation waveform of monocycle integrated carrier and alternating current.

Specific embodiment

The present invention is further described below in conjunction with the accompanying drawings.

Fig. 1 for three-phase tri-level (VIENNA) rectifier main circuit topology figure, L in figure_a、L_b、L_cFor Inductor, i_a、i_b、i_cFor AC input current.S_a、S_b、S_cFor two-way switch.V_dcFor DC side output voltage, C₁、C₂Respectively direct current Support Capacitor, V_c1、V_c2For electric capacity C₁、C₂The voltage at two ends.V_MIDFor mid-point voltage, under normal circumstances, mid-point voltage does not occur Skew, V_MID=V_dc/2.But inconsistent due to Support Capacitor parameter, laod unbalance and the not equal reason of modulation strategy, Capacitor charge and discharge can be made uneven, cause mid-point voltage to fluctuate, mid-point voltage undulating value Δ V_dcIt is defined as △ V_dc=V_c1-V_c2。

Fig. 2 is DSP+FPGA core controller functional block diagrams.DSP includes communication module and midpoint potential core algorithm mould Block, midpoint potential core algorithm module includes zero sequence dutycycle computing module, capacitance voltage difference PI control modules, digital monocyclic again Phase control integration calculation of initial value module and modulating wave range-adjusting module.FPGA includes sampling module, protection module, twoport RAM (DPRAM1, DPRAM2), one circle control module, state machine module, system control module.

Sampling module in FPGA is mainly responsible for the voltage from A/D chip collection main circuit, current signal and is supplied to DPRAM2 and protection module.Protection module is mainly responsible for detecting that the output signal of circuit is processed to overvoltage, excessively stream etc., in event Locking pulse is with protection switch device during barrier.DPRAM2 is mainly responsible for the DSP transtation mission circuits running status such as letter such as voltage, electric current Breath.Communication module in DSP is mainly responsible for reading the circuit operations conditions in DPRAM2, electricity by address bus and data/address bus The information such as pressure, electric current, and realize the communication with host computer.DPRAM1 in FPGA is mainly responsible for receiving midpoint potential in DSP The output result of core algorithm.One circle control module is mainly responsible for performing one circle control core algorithm and generating various switches The driving pulse of device.

Fig. 3 is DSP algorithm partial function figure, by zero sequence dutycycle computing module, capacitance voltage difference PI control module sums Word one circle control integration calculation of initial value module composition.Computational methods flow process is as follows：

Step 1, in zero sequence dutycycle computing module, by input side three-phase electricity flow valuve i for collecting_a、i_b、i_c, input side Three-phase voltage V_as、V_bs、V_csWith DC side output voltage values V_dcProcessed, obtained the sinusoidal component d of dutycycle_a、d_b、d_c.Account for The sinusoidal component d of empty ratio_a、d_b、d_cIt is given by：

Wherein, L_a、L_b、L_cThe respectively Inductor of a, b, c three-phase；

By calculated dutycycle sinusoidal component d_a、d_b、d_cDutycycle zero-sequence component d is obtained after processing as the following formula₀：

Step 2, in capacitance voltage difference PI control modules, by the voltage V of upper and lower two electric capacity of the DC side for collecting_c1、 V_c2Make the mid-point voltage undulating value △ V after difference_dc=V_c1-V_c2PI controllers are sent into, PI controlled output voltages are obtained.Wherein PI is controlled Device parameter processed is designed by relationship below：

Step 3, for the digital monocyclic phase control integration calculation of initial value module, be input into the zero sequence to obtain in step 1,2 Dutycycle d₀With PI controlled output voltage V_m2, the digital monocyclic phase is obtained after calculating according to the following formula, and to control the integration in each cycle initial Value Λ, for realizing the VIENNA rectifier DC side neutral-point potential balance of digital monocyclic phase control.

Monocycle carrier wave is generated using integration method, from the integration initial value Λ in each cycle_kRise and start to be incremented to carrier wave Peak value 1, is then decremented to the integration initial value Λ in this cycle_k, it is incremented by each cycle and decrementing procedure is symmetrically every so as to generate The carrier wave in individual cycle.

Step 4, Fig. 4 are neutral-point-potential balance control schematic diagram, by DC voltage reference value V_refDeduct upper and lower two electricity The magnitude of voltage V of appearance_c1、V_c2Afterwards, resulting difference is carried out obtaining V after PI process_m1, by V_m1Inverted rear and modulating wave | R_s* i_k| it is multiplied to adjust the amplitude of modulating wave；

Step 5, by step 4 adjust amplitude after modulating wave and monocycle integrated carrier Jing comparator obtain pwm signal.

V in conventional method_m1With monocycle carrier multiplication, then compare with the modulating wave Jing for reflecting alternating current sampled value Device obtains pwm signal.In the method for the invention, the multiplication completed in FPGA is calculated and is transferred in DSP by the method, is improved The arithmetic speed of numerical control system.

Fig. 5, Fig. 6 are the capacitance voltage of DC side two entirety simulation waveform and partial enlargement simulation waveform, can by simulation waveform See, Jing after the neutral point voltage control method of the present invention, the voltage of two electric capacity is approximately the same, control effect is preferable.Fig. 7 is the monocycle The overlapping simulation waveform of integrated carrier and alternating current sampled signal.

The above is only the preferred embodiment of the present invention, it should be pointed out that：For the ordinary skill people of the art For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should It is considered as protection scope of the present invention.

Claims (2)

1. a kind of VIENNA rectifier DC side neutral-point potential balance control method, it is characterised in that：Comprise the following steps：

Step one, the input side three-phase current of collection VIENNA rectifier, three-phase voltage and DC voltage value；Collection DC side Upper and lower capacitance voltage value；

Step 2, by input side three-phase current i_a、i_b、i_c, input side three-phase voltage V_as、V_bs、V_csWith DC voltage value V_dcBring into Following formula obtains the sinusoidal component d of dutycycle_a、d_b、d_c：

$\left\{\begin{array}{c}{V}_{as}=L_a\frac{{\mathrm{di}}_a}{dt}+\frac{V_{dc}}{2}{d}_a\\ V_{bs}=L_b\frac{{\mathrm{di}}_b}{dt}+\frac{V_{dc}}{2}{d}_b\\ V_{cs}=L_c\frac{{\mathrm{di}}_c}{dt}+\frac{V_{dc}}{2}{d}_c\end{array}\right.$

Wherein, L_a、L_b、L_cThe respectively Inductor of a, b, c three-phase；

By dutycycle sinusoidal component d_a、d_b、d_cBring following formula into obtain switching zero sequence dutycycle d₀：

$d_0=-\frac{\left|i_a\right|d_a+\left|i_b\right|d_b+\left|i_c\right|d_c}{\left|i_a\right|+\left|i_b\right|+\left|i_c\right|}$

The upper and lower capacitance voltage value of DC side is made into difference and PI controls are carried out, PI controlled output voltage V are obtained_m2；

Step 3, utilization switch zero sequence dutycycle d₀With PI controlled output voltage V_m2Calculate according to the following formula and obtain the control of digital monocyclic phase The integration initial value Λ in each cycle of system_k,

${\mathrm{\Λ}}_k=\frac{d_0+V_{m2}}{1-\left(R_S\right|i_k|+d_0+V_{m2})}$

In above formula,

i_kFor input side three-phase current, k represents the wherein phase in a, b, c three-phase；R_sFor alternating current sampling resistor；R_S|i_k| table Show modulating wave；

Monocycle carrier wave is generated using integration method, from the integration initial value Λ in each cycle_kRise and start to be incremented to carrier peak value 1, Then it is decremented to the integration initial value Λ in this cycle_k, it is incremented by each cycle and decrementing procedure is symmetrically so as to generate each cycle Carrier wave；

Step 4, DC voltage reference value is deducted after the upper and lower capacitance voltage value of DC side obtain difference through PI controls, Obtain PI controlled output voltage V_m1, by V_m1Inverted rear and modulating wave is multiplied to adjust the amplitude of modulating wave；

Step 5, by the monocycle carrier wave of acquisition with adjustment amplitude after modulating wave be input into comparator obtain pwm signal use In dutycycle of the modulation per mutually switch.

2. the device of the VIENNA rectifier DC side neutral-point potential balance control method described in a kind of employing claim 1, its It is characterised by：Including FPGA and DSP；Comprising operation of power networks data acquisition module and one circle control module, institute in the FPGA State in DSP comprising zero sequence dutycycle computing module, capacitance voltage difference PI control modules, digital monocyclic phase control integration initial value meter Calculate module and modulating wave range-adjusting module；FPGA collection operation of power networks data are simultaneously transmitted to DSP, and the DSP is according to obtaining The operation of power networks data for obtaining calculate the integration initial value Λ for the acquisition digital monocyclic phase controlling each cycle_kAnd transmit into FPGA One circle control module, one circle control module generates monocycle carrier wave and carries out duty cycle of switching control.