CN104835817A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN104835817A CN104835817A CN201410045984.5A CN201410045984A CN104835817A CN 104835817 A CN104835817 A CN 104835817A CN 201410045984 A CN201410045984 A CN 201410045984A CN 104835817 A CN104835817 A CN 104835817A
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, relating to the semiconductor technical field. The semiconductor device manufacturing method can manufacture a gate-all-around (GAA) transistor device and simultaneously manufacture a diode and a bipolar transistor based on silicon nano-wires on a semiconductor substrate, and does not increase extra processes and costs. The semiconductor device according to the invention possesses the above mentioned advantages.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and manufacture method thereof.
Background technology
In technical field of semiconductors, loopful grid (Gate-All-Around; Being called for short GAA) silicon nanowires (nano-wire) field-effect transistor is most one of device architecture having application prospect in the super-small CMOS technology in future.
But seldom have disclosure in prior art, in the device of this type, what kind of the structure of diode and bipolar transistor is and how manufactures this device on body silicon substrate.
Therefore, how in the manufacture method of semiconductor device, while manufacture body silicon loopful grid (GAA) transistor device, body silicon substrate completes diode and bipolar transistor pipe manufacturer, has become the technical problem that semiconductor product industry is urgently to be resolved hurrily.
Summary of the invention
In order to solve the problem, the present invention proposes a kind of semiconductor device structure and manufacture method thereof.
The invention provides a kind of manufacture method of semiconductor device, described method comprises:
Step S101: provide and comprise the first substrate and the Semiconductor substrate of the second substrate be located thereon, the silicon nanowires forming suspension is etched to described second substrate;
Step S102: ion implantation is carried out to form the silicon nanowires with the first doping type to described silicon nanowires;
Step S103: form the first epi dopant layer with the second doping type around described silicon nanowires at the zone line of described silicon nanowires;
Step S104: form the second epi dopant layer with the first doping type around described first epi dopant layer at the zone line of described first epi dopant layer;
Wherein, the first doping type is N-type or the doping of P type, and the second doping type is P type or N-type doping; Described silicon nanowires and described first epi dopant layer form diode; Described silicon nanowires and described first epi dopant layer and described second epi dopant layer form bipolar transistor, wherein said silicon nanowires is the collector electrode of described bipolar transistor, described first epi dopant layer is the base stage of described bipolar transistor, and described second epi dopant layer is the emitter of described bipolar transistor.
Alternatively, in described step S101, also comprised before the described silicon nanowires of formation and silicon atom injection is carried out with the step defining silicon nanowires region to described second substrate.
Alternatively, in described step S101, described first substrate is P type substrate, and described second substrate is amorphous silicon substrate; Further, described first doping type is N-type doping, and the second doping type is the doping of P type.
Alternatively, in described step S101, described first substrate is P type substrate, described second substrate is amorphous silicon substrate, described Semiconductor substrate also comprises the dark N trap that adulterates between described first substrate and described second substrate, further, described first doping type is the doping of P type, and the second doping type is N-type doping.
Alternatively, between described step S101 and described step S102, also step S1012 is comprised: by annealing process, crystallization is carried out to described silicon nanowires.
Alternatively, described step S103 comprises:
Step S1031: be oxidized described silicon nanowires to form the oxide skin(coating) covering described silicon nanowires;
Step S1032: remove described oxide skin(coating) by etching and be positioned at the part of the zone line of described silicon nanowires to form mask layer;
Step S1033: form the first epi dopant layer with the second doping type around described silicon nanowires by epitaxial growth technology in the region that described silicon nanowires is not covered by described mask layer.
Alternatively, in described step S104, while the described second epi dopant layer of formation, form the splicing ear connecting described silicon nanowires at the two ends of described silicon nanowires.
Alternatively, described first epi dopant layer is selected from least one in silicon, germanium silicon, GaAs or the carbon silicon with the second doping type, and described second epi dopant layer is selected from least one in silicon, germanium silicon, GaAs or the carbon silicon with the first doping type.
Alternatively, also step S105 is comprised: form interlayer dielectric layer and the interconnection structure for connecting described silicon nanowires, described first epi dopant layer and described second epi dopant layer after described step S104, wherein, before the described interconnection structure of formation, the region contacted with described interconnection structure at described silicon nanowires, described first epi dopant layer and described second epi dopant layer forms metal silicide.
The present invention also provides a kind of semiconductor device, comprises Semiconductor substrate, the silicon nanowires be positioned in described Semiconductor substrate, the second epi dopant layer around the first epi dopant layer of the zone line of described silicon nanowires and the zone line around described first epi dopant layer, wherein, the second substrate that described Semiconductor substrate comprises the first substrate and is located thereon, described silicon nanowires is positioned at described second substrate, described silicon nanowires and described second epi dopant layer have the first doping type, described first epi dopant layer has the second doping type, described silicon nanowires and described first epi dopant layer form diode, described silicon nanowires and described first epi dopant layer and described second epi dopant layer form bipolar transistor, wherein said silicon nanowires is the collector electrode of described bipolar transistor, described first epi dopant layer is the base stage of described bipolar transistor, described second epi dopant layer is the emitter of described bipolar transistor, wherein, the first doping type is N-type doping or the doping of P type, and the second doping type is the doping of P type or N-type doping.
Alternatively, described first substrate is P type substrate, and described second substrate is amorphous silicon substrate, and described first doping type is N-type doping, and the second doping type is the doping of P type, and described bipolar transistor is NPN type.
Alternatively, described first substrate is P type substrate, and described second substrate is dark doping N trap; Further, described first doping type is the doping of P type, and the second doping type is N-type doping, and described bipolar transistor is positive-negative-positive.
Wherein, described second substrate and described silicon nanowires form PN junction, and described PN junction is by described bipolar transistor and described first substrate isolation.
Alternatively, described semiconductor device also comprises the splicing ear of the described silicon nanowires of connection being positioned at described silicon nanowires two ends, and wherein, described splicing ear is identical with the doping type of described second epi dopant layer.
Alternatively, described first epi dopant layer is selected from least one in silicon, germanium silicon, GaAs or the carbon silicon with the second doping type, and described second epi dopant layer is selected from least one in silicon, germanium silicon, GaAs or the carbon silicon with the first doping type.
Alternatively, described semiconductor device also comprises interlayer dielectric layer and the interconnection structure for connecting described silicon nanowires, described first epi dopant layer and described second epi dopant layer, further, the region contacted with described silicon nanowires, described first epi dopant layer and described second epi dopant layer at described interconnection structure is provided with metal silicide.
The manufacture method of semiconductor device of the present invention, can be implemented in while manufacturing loopful gate transistor device, manufactures the diode based on silicon nanowires and bipolar transistor on a semiconductor substrate, can not increase extra technique and cost.Semiconductor device of the present invention, adopts the manufacture method of above-mentioned semiconductor device to prepare, has above-mentioned advantage.In addition, owing to having diode based on silicon nanowires and bipolar transistor, this semiconductor device can realize greater functionality.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A to 1L is the schematic diagram of the structure that the correlation step of the manufacture method of a kind of semiconductor device of the embodiment of the present invention one is formed;
Fig. 1 M is a kind of indicative flowchart of the manufacture method of a kind of semiconductor device of the embodiment of the present invention one;
Fig. 2 A to 2L is the schematic diagram of the structure that the correlation step of the manufacture method of a kind of semiconductor device of the embodiment of the present invention two is formed;
Fig. 2 M is a kind of indicative flowchart of the manufacture method of a kind of semiconductor device of the embodiment of the present invention two;
Fig. 3 is the schematic diagram of the structure of a kind of semiconductor device of the embodiment of the present invention three;
Fig. 4 is the schematic diagram of the structure of a kind of semiconductor device of the embodiment of the present invention four.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
Here with reference to the cross-sectional view as the schematic diagram of desirable embodiment of the present invention (and intermediate structure), inventive embodiment is described.Like this, it is expected to the change from shown shape because such as manufacturing technology and/or tolerance cause.Therefore, embodiments of the invention should not be confined to the given shape in district shown here, but comprise owing to such as manufacturing the form variations caused.Such as, the injection region being shown as rectangle has round or bending features and/or implantation concentration gradient usually at its edge, instead of the binary from injection region to non-injection regions changes.Equally, by inject formed disposal area this disposal area and injection can be caused to carry out time process surface between district some inject.Therefore, the district shown in figure is in fact schematic, and their shape is not intended the true form in the district of display device and is not intended to limit scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain the technical scheme of the present invention's proposition.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Embodiment one
Below, the detailed step of a manufacture method illustrative methods of the semiconductor device that the embodiment of the present invention proposes is described with reference to Figure 1A-Fig. 1 L and Fig. 1 M.Wherein, Figure 1A to 1L is the schematic diagram of the structure of the correlation step formation of the manufacture method of a kind of semiconductor device of the embodiment of the present invention; Fig. 1 M is a kind of indicative flowchart of the manufacture method of a kind of semiconductor device of the embodiment of the present invention.
The manufacture method of the semiconductor device of the embodiment of the present invention, for completing the manufacture of diode and bipolar npn transistor npn npn in the process manufacturing loopful gate transistor simultaneously, specifically comprises the steps:
Steps A 1: Semiconductor substrate 100 is provided, the amorphous silicon substrate (being denoted as the second substrate) 1002 that described Semiconductor substrate 100 comprises P type substrate (being denoted as the first substrate) 1001 and is positioned on P type substrate 1001, as shown in Figure 1A.
In figure ia, upper figure is vertical view; Left figure in figure below is the cutaway view in X-X ' direction, and right figure is the cutaway view in Y-Y ' direction.In follow-up Figure 1B to Fig. 1 L, the marking mode of each figure is identical therewith.
In figure ia, P-sub represents P type substrate.
Steps A 2: the region 1010 being defined silicon nanowires (silicon nano-wire) place by silicon (Si) Atom injection in amorphous silicon substrate 1002, as shown in Figure 1B.
Steps A 3: by being etched in the silicon nanowires 101 forming suspension on Semiconductor substrate 100, as shown in Figure 1 C.
Wherein, silicon nanowires 101 is formed in the region that amorphous silicon substrate 1002 is injected into silicon atom, that is, be formed in the region 1010 at defined silicon nanowires (silicon nano-wire) place.
In the present embodiment, the method for wet etching is adopted to form silicon nanowires 101.In the process of etching, other regions are covered by mask layer 102, as shown in Figure 1 C.The silicon nanowires 101 formed in this step is made up of amorphous silicon.
In the present embodiment, steps A 3 synchronously can realize with the technique of the silicon nanowires forming GAA transistor, does not need additional process.
Steps A 4: carry out crystallization to silicon nanowires 101 by annealing process, forms the nano wire of crystallization, as shown in figure ip.
Wherein, Fig. 1 D is only for illustrating crystallization process, concise and to the point in order to what represent, and the situation of change of not shown silicon nanowires 101 after crystallization.
Steps A 5: N-type ion implantation is carried out to form N trap to silicon nanowires 101, as referring to figure 1e.
Wherein, in fig. ie, " NW " represents N trap.
Through steps A 5, the silicon nanowires that silicon nanowires 101 adulterates for N-type.
In the present embodiment, the silicon nanowires 101 of this N-type doping as the collector electrode (collector) of bipolar npn transistor npn npn, as referring to figure 1e.
Steps A 6: the mask layer 103 ' forming two end regions covering silicon nanowires 101, as shown in Figure 1 G.
Exemplarily, the method forming mask layer 103 ' comprises:
Steps A 61: be oxidized silicon nanowires 101 to form the oxide skin(coating) 103 covering silicon nanowires 101, as shown in fig. 1f.
Steps A 62: remove by wet etching the part that oxide skin(coating) 103 is positioned at the zone line of silicon nanowires 101, form mask layer 103 ', as shown in Figure 1 G.
Steps A 7: form the P type doped layer (such as: form the in-situ doped layer of P+ source and drain) 104 around this silicon nanowires 101 in the region do not covered by mask layer 103 ' of silicon nanowires 101, as shown in fig. 1h.
Exemplarily, form P type doped layer 104(and be denoted as the first epi dopant layer) method, can be epitaxial growth method.
In the present embodiment, the silicon nanowires 101 that this P type doped layer 104 adulterates around the N-type of the collector electrode as bipolar npn transistor npn npn, as the base stage (base) of bipolar npn transistor npn npn, as shown in fig. 1h.
In the present embodiment, steps A 7 synchronously can realize with the technique of the P+ type source-drain electrode forming GAA transistor, does not need additional process.
Steps A 8: form two end regions the barrier layer (block layer) 105 exposing the two ends of silicon nanowires 101 that cover P type doped layer 104, as shown in figure ij.
Exemplarily, the method forming barrier layer 105 comprises:
Steps A 81: form the barrier material layer 1050 covering P type doped layer 104 and silicon nanowires 101 completely, as shown in Figure 1 I.
Steps A 82: remove barrier material layer 1050 by etching and be positioned at the part of the zone line of P type doped layer 104 and be positioned at the part at two ends of silicon nanowires 101, form barrier layer 105, as shown in figure ij.
Steps A 9: do not formed the N-type doped layer (such as: form the in-situ doped layer of N+ source and drain) 106 around P type doped layer 104 by the region that barrier layer 105 covers at P type doped layer 104, do not formed by the region that barrier layer 105 covers the splicing ear 107 connecting silicon nanowires 101 at the two ends of silicon nanowires 101, as shown in figure ik simultaneously.
Exemplarily, form N-type doped layer 106(and be denoted as the second epi dopant layer) and the method for splicing ear 107, can be epitaxial growth method.
In the present embodiment, this N-type doped layer 106 around the P type doped layer 104 of the base stage as bipolar npn transistor npn npn, as the emitter of bipolar npn transistor npn npn, as shown in figure ik.That is, the silicon nanowires 101 of this N-type doping is as the collector electrode of bipolar npn transistor npn npn; The silicon nanowires 101 that P type doped layer 104 adulterates around this N-type, as the base stage of bipolar npn transistor npn npn; N-type doped layer 106 around this P type doped layer 104, as the emitter of bipolar npn transistor npn npn.
Wherein, the splicing ear 107 of silicon nanowires 101 is identical with the material of N-type doped layer (such as: the in-situ doped layer of N+ source and drain), can be considered a part for collector electrode.The effect forming splicing ear 107 is, can reduce the contact resistance of collector electrode (specifically, referring to silicon nanowires 101).
In the present embodiment, steps A 9 synchronously can realize with the technique of the N+ type source-drain electrode forming GAA transistor, does not need additional process.
Steps A 10: form metal silicide 108 respectively above splicing ear 107, N-type doped layer 106, P type doped layer 104, then form interlayer dielectric layer 109 and be positioned at interlayer dielectric layer 109 and be positioned at the contact hole 110 above metal silicide 108, as can be seen in figure il.
Wherein, contact hole 110 is for the formation of the interconnection structure connecting silicon nanowires (101), P type doped layer (104) and N-type doped layer (106).
Wherein, interlayer dielectric layer 109, except assembly such as covering metal silicide 108 grade, is also filled in the gap between silicon nanowires 101 and Semiconductor substrate 100, as can be seen in figure il.
Wherein, the effect forming metal silicide 108 is the contact resistance of the collector electrode of reduction bipolar transistor, base stage, emitter.
In the present embodiment, this bipolar npn transistor npn npn is level (referring to that three electrode collector electrodes, base stage, emitter itself are parallel to the upper surface of Semiconductor substrate 100), is formed on silicon nanowires.Further, this bipolar npn transistor npn npn and P type substrate 1001 are isolated, as shown in Fig. 1 K and 1L by the PN junction that the silicon nanowires 101 that amorphous silicon substrate 1002 and N-type are adulterated is formed.
In addition, in the present embodiment, the silicon nanowires 101 of this N-type doping also forms diode structure, as shown in Fig. 1 K and Fig. 1 L with this P type doped layer 104.This diode for loopful geometric pattern diode (N-type doping silicon nanowires 101 by P type doped layer 104 institute around), the diode in Fig. 1 L is P+/NW type diode.Except P+/NW type, this diode can also be N+/P+ type diode, such as: when the silicon nanowires 101 in Fig. 1 L splicing ear 107 completely and P type doped layer 104 adjoins time form N+/P+ type diode; Also can being N+/PW type diode, when this bipolar npn transistor npn npn in Fig. 1 L being replaced with positive-negative-positive bipolar transistor (each layer position relationship only changes N-type into P type, P type changes N-type into), N+/PW type diode can being formed.Those skilled in the art will appreciate that the situation except the collector electrode in the two poles of the earth of the diode shown in the present embodiment and bipolar npn transistor npn npn and base stage share, independently diode structure can also be manufactured in above-mentioned technical process.
In the present embodiment, this silicon nanowires bipolar transistor is parasitic (parasitic), namely, the manufacture of silicon nanowires bipolar transistor is completed in the technical process manufacturing body silicon loopful gate transistor (GAA MOSFET), therefore extra masking process can not be increased, also extra cost can not be increased.Obtained semiconductor device, owing to also comprising diode based on silicon nanowires and bipolar transistor except comprising loopful gate transistor, thus can realize more function.
As can be seen here, the manufacture method of the semiconductor device of the embodiment of the present invention, can be implemented in while manufacturing loopful gate transistor, body silicon substrate manufactures diode and bipolar transistor, can not increase extra technique and cost.
Fig. 1 M shows a kind of indicative flowchart of the manufacture method of a kind of semiconductor device that the embodiment of the present invention proposes, for schematically illustrating the typical process of this manufacture method.Specifically comprise:
Step S1: provide and comprise the first substrate and the Semiconductor substrate of the second substrate be located thereon, the silicon nanowires forming suspension is etched to described second substrate;
Step S2: N-type ion implantation is carried out to form the silicon nanowires of N-type to described silicon nanowires;
Step S3: form the first epi dopant layer adulterated around the P type of described silicon nanowires at the zone line of described silicon nanowires;
Step S4: form the second epi dopant layer adulterated around the N-type of described first epi dopant layer at the zone line of described first epi dopant layer.
Embodiment two
Below, the detailed step of a manufacture method illustrative methods of the semiconductor device that the embodiment of the present invention proposes is described with reference to Fig. 2 A-Fig. 2 L and Fig. 2 M.Wherein, Fig. 2 A to 2L is the schematic diagram of the structure of the correlation step formation of the manufacture method of a kind of semiconductor device of the embodiment of the present invention; Fig. 2 M is a kind of indicative flowchart of the manufacture method of a kind of semiconductor device of the embodiment of the present invention.
The manufacture method of the semiconductor device of the embodiment of the present invention, for completing the manufacture of diode and positive-negative-positive bipolar transistor in the process manufacturing loopful gate transistor simultaneously, specifically comprises the steps:
Step B1: Semiconductor substrate 100 is provided, described Semiconductor substrate 100 comprises P type substrate 1001(and is denoted as the first substrate) and dark doping N trap (DNW) 1003 that is positioned on P type substrate 1001 and the amorphous silicon substrate (being denoted as the second substrate) 1002 be positioned on dark doping N trap 1002, as shown in Figure 2 A.
In fig. 2, upper figure is vertical view; Left figure in figure below is the cutaway view in X-X ' direction, and right figure is the cutaway view in Y-Y ' direction.In follow-up Fig. 2 B to Fig. 2 L, the marking mode of each figure is identical therewith.
In figure ia, P-sub represents P type substrate.
Step B2: the region 1003 ' being defined silicon nanowires (silicon nano-wire) place by silicon (Si) Atom injection in amorphous silicon substrate 1002, as shown in Figure 2 B.
Step B3: the top of N trap 1002 (specifically refer to deeply adulterate) forms the silicon nanowires 101 hung by being etched on Semiconductor substrate 100, as shown in Figure 2 C.
Wherein, silicon nanowires 101 is formed in the region that amorphous silicon substrate 1002 is injected into silicon atom, that is, be formed in the region 1002 ' at defined silicon nanowires (silicon nano-wire) place.The silicon nanowires 101 hung, refers to that the zone line of silicon nanowires is in vacant state (that is, below is etched and forms groove), as shown in Figure 2 C.
In the present embodiment, the method for wet etching is adopted to form silicon nanowires 101.In the process of etching, other regions are covered by mask layer 102, as shown in Figure 2 C.The silicon nanowires 101 formed in this step is made up of amorphous silicon.
In the present embodiment, step B3 synchronously can realize with the technique of the silicon nanowires forming GAA transistor, does not need additional process.
Step B4: carry out crystallization to silicon nanowires 101 by annealing process, forms the silicon nanowires of crystallization, as shown in Figure 2 D.
Wherein, Fig. 2 D is only for illustrating crystallization process, concise and to the point in order to what represent, and the situation of change of not shown silicon nanowires 101 after crystallization.
Step B5: P type ion implantation is carried out to form P trap (PW) to silicon nanowires 101, as shown in Figure 2 E.
Wherein, in Fig. 2 E, " PW " represents N trap.
Through step B5, the silicon nanowires that silicon nanowires 101 adulterates for P type.
In the present embodiment, the silicon nanowires 101 of this P type doping as the collector electrode (collector) of positive-negative-positive bipolar transistor, as shown in Figure 2 E.
Step B6: the mask layer 103 ' forming two end regions covering silicon nanowires 101, as shown in Figure 2 G.
Exemplarily, the method forming mask layer 103 ' comprises:
Step B61: be oxidized silicon nanowires 101 to form the oxide skin(coating) 103 covering silicon nanowires 101, as shown in fig. 1f.
Step B62: remove by wet etching the part that oxide skin(coating) 103 is positioned at the zone line of silicon nanowires 101, form mask layer 103 ', as shown in Figure 2 G.
Step B7: form the N-type doped layer (such as: form the in-situ doped layer of N+ source and drain) 104 around this silicon nanowires 101 in the region do not covered by mask layer 103 ' of silicon nanowires 101, as illustrated in figure 2h.
Exemplarily, form N-type doped layer 104(and be denoted as the first epi dopant layer) method, can be epitaxial growth method.
In the present embodiment, the silicon nanowires 101 that this N-type doped layer 104 adulterates around the P type of the collector electrode as positive-negative-positive bipolar transistor, as the base stage (base) of positive-negative-positive bipolar transistor, as illustrated in figure 2h.
In the present embodiment, step B7 synchronously can realize with the technique of the N+ type source-drain electrode forming GAA transistor, does not need additional process.
Step B8: form two end regions the barrier layer (block layer) 105 exposing the two ends of silicon nanowires 101 that cover N-type doped layer 104, as shown in fig. 2j.
Exemplarily, the method forming barrier layer 105 comprises:
Step B81: form the barrier material layer 1050 covering N-type doped layer 104 and silicon nanowires 101 completely, as shown in figure 2i.
Steps A 82: remove barrier material layer 1050 by etching and be positioned at the part of the zone line of N-type doped layer 104 and be positioned at the part at two ends of silicon nanowires 101, form barrier layer 105, as shown in fig. 2j.
Step B9: do not formed the P type doped layer (such as: form the in-situ doped layer of P+ source and drain) 106 around N-type doped layer 104 by the region that barrier layer 105 covers at N-type doped layer 104, do not formed the splicing ear 107 of silicon nanowires 101 by the region that barrier layer 105 covers at the two ends of silicon nanowires 101, as shown in figure 2k simultaneously.
Exemplarily, form P type doped layer 106(and be denoted as the second epi dopant layer) and the method for splicing ear 107, can be epitaxial growth method.
In the present embodiment, this P type doped layer 106 around the N-type doped layer 104 of the base stage as positive-negative-positive bipolar transistor, as the emitter (emitter) of positive-negative-positive bipolar transistor, as shown in figure 2k.That is, the silicon nanowires 101 of this P type doping is as the collector electrode of positive-negative-positive bipolar transistor; The silicon nanowires 101 that N-type doped layer 104 adulterates around this P type, as the base stage of positive-negative-positive bipolar transistor; P type doped layer 106 around this N-type doped layer 104, as the emitter of positive-negative-positive bipolar transistor.
Wherein, the splicing ear 107 of silicon nanowires 101 is identical with the material of P type doped layer (such as: the in-situ doped layer of P+ source and drain), can be considered a part for collector electrode.The effect forming splicing ear 107 is, can reduce the contact resistance of collector electrode (specifically, referring to silicon nanowires 101).
In the present embodiment, step B9 synchronously can realize with the technique of the P+ type source-drain electrode forming GAA transistor, does not need additional process.
Step B10: form metal silicide 108 respectively above the splicing ear 107 of silicon nanowires 101, P type doped layer 106, N-type doped layer 104, then form interlayer dielectric layer 109 and be positioned at interlayer dielectric layer 109 and be positioned at the contact hole 110 above metal silicide 108, as shown in figure 2l.
Wherein, interlayer dielectric layer 109, except assembly such as covering metal silicide 108 grade, is also filled in the gap between silicon nanowires 101 and Semiconductor substrate 100, as can be seen in figure il.
Wherein, the effect forming metal silicide 108 is the contact resistance of the collector electrode of reduction bipolar transistor, base stage, emitter.
In the present embodiment, this positive-negative-positive bipolar transistor is level (referring to that three electrode collector electrodes, base stage, emitter itself are parallel to the upper surface of Semiconductor substrate 100), is formed on silicon nanowires.Further, this positive-negative-positive bipolar transistor and P type substrate 1001 are isolated, as shown in Fig. 2 K and 2L by the PN junction that the silicon nanowires 101 that dark doping N trap 1002 and P type adulterate is formed.
In addition, in the present embodiment, the silicon nanowires 101 of this P type doping also forms diode structure, as shown in Fig. 2 K and Fig. 2 L with this N-type doped layer 104.Those skilled in the art will appreciate that the situation except the collector electrode in the two poles of the earth of the diode shown in the present embodiment and positive-negative-positive bipolar transistor and base stage share, independently diode structure can also be manufactured in above-mentioned technical process.
In the present embodiment, this silicon nanowires bipolar transistor is parasitic (parasitic), namely, the manufacture of silicon nanowires bipolar transistor is completed in the technical process manufacturing body silicon loopful grid (GAA) transistor device, therefore extra masking process can not be increased, also extra cost can not be increased.Obtained semiconductor device, owing to also comprising diode based on silicon nanowires and bipolar transistor except comprising loopful gate transistor, thus can realize more function.
As can be seen here, the manufacture method of the semiconductor device of the embodiment of the present invention, can be implemented in while manufacturing loopful gate transistor, body silicon substrate manufactures diode and bipolar transistor, can not increase extra technique and cost.
Fig. 2 M shows a kind of indicative flowchart of the manufacture method of a kind of semiconductor device that the embodiment of the present invention proposes, for schematically illustrating the typical process of this manufacture method.Specifically comprise:
Step T1: provide and comprise the first substrate, the second substrate and be positioned at the Semiconductor substrate of dark N trap therebetween, the silicon nanowires forming suspension is etched to described second substrate;
Step T2: P type ion implantation is carried out to form the silicon nanowires of P type doping to described silicon nanowires;
Step T3: form the first epi dopant layer adulterated around the N-type of described silicon nanowires at the zone line of described silicon nanowires;
Step T4: form the second epi dopant layer adulterated around the P type of described first epi dopant layer at the zone line of described first epi dopant layer.
Embodiment three
Below, the structure of the semiconductor device that the embodiment of the present invention proposes is described with reference to Fig. 3.Wherein, Fig. 3 is the schematic diagram of the structure of the semiconductor device of the embodiment of the present invention; In figure 3, upper figure is vertical view; Left figure in figure below is the cutaway view in X-X ' direction, and right figure is the cutaway view in Y-Y ' direction.
The semiconductor device of the embodiment of the present invention, can adopt the method manufacture described in embodiment one.As shown in Figure 3, this semiconductor device comprises: comprise Semiconductor substrate 100, be positioned at the silicon nanowires 101 of the level in described Semiconductor substrate, around the second epi dopant layer 106 of the first epi dopant layer 104 of the zone line of described silicon nanowires 101 and the zone line around described first epi dopant layer 104.Wherein, the second substrate 1002 that described Semiconductor substrate 100 comprises the first substrate 1001 and is located thereon, described silicon nanowires 101 is positioned on described second substrate 1002.
In the present embodiment, described silicon nanowires 101 and described second epi dopant layer are N-type doping, and described first epi dopant layer 104 is the doping of P type.
Obviously, described silicon nanowires 101 forms diode structure with described first epi dopant layer 104; Described silicon nanowires 101 forms bipolar npn transistor npn npn with described first epi dopant layer 104 and described second epi dopant layer 106.
Exemplarily, silicon nanowires 101 and the first epi dopant layer 104 form diode is P+/NW type diode.In addition, this diode can also be N+/P+ type diode or N+/PW type diode.
Wherein, described first substrate 1001 is P type substrate, and described second substrate 1002 is amorphous silicon substrate.
As shown in Figure 3, described second substrate 1002 forms PN junction with described silicon nanowires 101, and this bipolar transistor and the first substrate 1001 are isolated by described PN junction.
Further, this semiconductor device also comprises the splicing ear 107 of the described silicon nanowires of connection being positioned at silicon nanowires 101 two ends, and wherein said splicing ear 107 is N-type doping.
Wherein, first epi dopant layer 104 is selected from least one in the silicon (Si) of P type doping, germanium silicon (SiGe), GaAs (GaAs) or carbon silicon (SiC), and the second epi dopant layer 106 is selected from least one in the silicon (Si) of N-type doping, germanium silicon (SiGe), GaAs (GaAs) or carbon silicon (SiC).
Further, this semiconductor device also comprises interlayer dielectric layer 109 and the interconnection structure (illustrate only contact hole 110 in Fig. 3) for connecting described silicon nanowires 101, described first epi dopant layer 104 and described second epi dopant layer 106.Further, the region contacted with silicon nanowires 101, first epi dopant layer 104 and the second epi dopant layer 106 at interconnection structure is provided with metal silicide 108.
It will be appreciated by those skilled in the art that, semiconductor device due to the present embodiment adopts the manufacture method of the semiconductor device of embodiment one to obtain, therefore, except above-mentioned diode and triode in this semiconductor device, also comprise loopful gate transistor device (GAA MOSFET).
Semiconductor device of the present invention, except comprising loopful gate transistor, also comprises the diode based on silicon nanowires and bipolar transistor, thus can realize more function.
Embodiment four
Below, the structure of the semiconductor device that the embodiment of the present invention proposes is described with reference to Fig. 4.Wherein, Fig. 4 is the schematic diagram of the structure of the semiconductor device of the embodiment of the present invention; Figure is vertical view in fig. 4, the upper; Left figure in figure below is the cutaway view in X-X ' direction, and right figure is the cutaway view in Y-Y ' direction.
The semiconductor device of the embodiment of the present invention, can adopt the method manufacture described in embodiment two.As shown in Figure 4, this semiconductor device comprises: comprise Semiconductor substrate 100, be positioned at the silicon nanowires 101 of the level in described Semiconductor substrate, around the second epi dopant layer 106 of the first epi dopant layer 104 of the zone line of described silicon nanowires 101 and the zone line around described first epi dopant layer 104.Wherein, the second substrate 1002 that described Semiconductor substrate 100 comprises the first substrate 1001 and is located thereon, described silicon nanowires 101 is positioned on described second substrate 1002.
In the present embodiment, described silicon nanowires 101 and described second epi dopant layer 106 are the doping of P type, and described first epi dopant layer 104 is N-type doping.
Obviously, described silicon nanowires 101 forms diode structure with described first epi dopant layer 104; Described silicon nanowires 101 forms positive-negative-positive bipolar transistor with described first epi dopant layer 104 and described second epi dopant layer 106.
Exemplarily, silicon nanowires 101 and the first epi dopant layer 104 form diode is N+/PW type diode.In addition, this diode can also be N+/P+ type diode or P+/NW type diode.
Wherein, described first substrate 1001 is P type substrate; Described second substrate 1002 is dark doping N trap, that is, through the substrate with N trap of N-type doping formation.
As shown in Figure 4, described second substrate 1002 forms PN junction with described silicon nanowires 101, and this bipolar transistor and the first substrate 1001 are isolated by described PN junction.
Further, this semiconductor device also comprises the splicing ear 107 of the described silicon nanowires of connection being positioned at silicon nanowires 101 two ends, and wherein said splicing ear 107 is N-type doping.
Wherein, first epi dopant layer 104 is selected from least one in the silicon (Si) of N-type doping, germanium silicon (SiGe), GaAs (GaAs) or carbon silicon (SiC), and the second epi dopant layer 106 is selected from least one in the silicon (Si) of P type doping, germanium silicon (SiGe), GaAs (GaAs) or carbon silicon (SiC).
Further, this semiconductor device also comprises interlayer dielectric layer 109 and the interconnection structure (illustrate only contact hole 110 in Fig. 3) for connecting described silicon nanowires 101, described first epi dopant layer 104 and described second epi dopant layer 106.Further, the region contacted with silicon nanowires 101, first epi dopant layer 104 and the second epi dopant layer 106 at interconnection structure is provided with metal silicide 108, to reduce contact resistance.
It will be appreciated by those skilled in the art that, semiconductor device due to the present embodiment adopts the manufacture method of the semiconductor device of embodiment one to obtain, therefore, except above-mentioned diode and triode in this semiconductor device, also comprise loopful gate transistor (GAA MOSFET).
Semiconductor device of the present invention, except comprising loopful gate transistor, also comprises the diode based on silicon nanowires and bipolar transistor, thus can realize more function.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (16)
1. a manufacture method for semiconductor device, is characterized in that, described method comprises:
Step S101: provide and comprise the first substrate and the Semiconductor substrate of the second substrate be located thereon, the silicon nanowires forming suspension is etched to described second substrate;
Step S102: ion implantation is carried out to form the silicon nanowires with the first doping type to described silicon nanowires;
Step S103: form the first epi dopant layer with the second doping type around described silicon nanowires at the zone line of described silicon nanowires;
Step S104: form the second epi dopant layer with the first doping type around described first epi dopant layer at the zone line of described first epi dopant layer;
Wherein, the first doping type is N-type doping or the doping of P type, and the second doping type is the doping of P type or N-type doping; Described silicon nanowires and described first epi dopant layer form diode; Described silicon nanowires and described first epi dopant layer and described second epi dopant layer form bipolar transistor, wherein said silicon nanowires is the collector electrode of described bipolar transistor, described first epi dopant layer is the base stage of described bipolar transistor, and described second epi dopant layer is the emitter of described bipolar transistor.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in described step S101, also comprises and carried out silicon atom injection with the step defining silicon nanowires region to described second substrate before the described silicon nanowires of formation.
3. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, in described step S101, described first substrate is P type substrate, and described second substrate is amorphous silicon substrate; Further, described first doping type is N-type doping, and the second doping type is the doping of P type.
4. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, in described step S101, described first substrate is P type substrate, described second substrate is amorphous silicon substrate, and described Semiconductor substrate also comprises the dark N trap that adulterates between described first substrate and described second substrate; Further, described first doping type is the doping of P type, and the second doping type is N-type doping.
5. the manufacture method of the semiconductor device as described in claim 3 or 4, is characterized in that, between described step S101 and described step S102, also comprise step S1012: carry out crystallization by annealing process to described silicon nanowires.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, described step S103 comprises:
Step S1031: be oxidized described silicon nanowires to form the oxide skin(coating) covering described silicon nanowires;
Step S1032: remove described oxide skin(coating) by etching and be positioned at the part of the zone line of described silicon nanowires to form mask layer;
Step S1033: form the first epi dopant layer with the second doping type around described silicon nanowires by epitaxial growth technology in the region that described silicon nanowires is not covered by described mask layer.
7. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in described step S104, while the described second epi dopant layer of formation, forms the splicing ear connecting described silicon nanowires at the two ends of described silicon nanowires.
8. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, described first epi dopant layer is selected from least one in silicon, germanium silicon, GaAs or the carbon silicon with the second doping type, and described second epi dopant layer is selected from least one in silicon, germanium silicon, GaAs or the carbon silicon with the first doping type.
9. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, after described step S104, also comprise step S105: forming interlayer dielectric layer and the interconnection structure for connecting described silicon nanowires, described first epi dopant layer and described second epi dopant layer; Wherein, before the described interconnection structure of formation, the region contacted with described interconnection structure at described silicon nanowires, described first epi dopant layer and described second epi dopant layer forms metal silicide.
10. a semiconductor device, it is characterized in that, comprise Semiconductor substrate, the silicon nanowires be positioned in described Semiconductor substrate, the second epi dopant layer around the first epi dopant layer of the zone line of described silicon nanowires and the zone line around described first epi dopant layer, wherein, the second substrate that described Semiconductor substrate comprises the first substrate and is located thereon, described silicon nanowires is positioned at described second substrate, described silicon nanowires and described second epi dopant layer have the first doping type, described first epi dopant layer has the second doping type, described silicon nanowires and described first epi dopant layer form diode, described silicon nanowires and described first epi dopant layer and described second epi dopant layer form bipolar transistor, wherein said silicon nanowires is the collector electrode of described bipolar transistor, described first epi dopant layer is the base stage of described bipolar transistor, described second epi dopant layer is the emitter of described bipolar transistor, wherein, the first doping type is N-type doping or the doping of P type, and the second doping type is the doping of P type or N-type doping.
11. semiconductor device as claimed in claim 10, it is characterized in that, described first substrate is P type substrate, described second substrate is amorphous silicon substrate, described first doping type is N-type doping, and the second doping type is the doping of P type, and described bipolar transistor is NPN type.
12. semiconductor device as claimed in claim 10, it is characterized in that, described first substrate is P type substrate, described second substrate is dark doping N trap, described first doping type is the doping of P type, and the second doping type is N-type doping, and described bipolar transistor is positive-negative-positive.
13. semiconductor device as claimed in claim 10, it is characterized in that, described second substrate and described silicon nanowires form PN junction, and described PN junction is by described bipolar transistor and described first substrate isolation.
14. semiconductor device as claimed in claim 10, it is characterized in that, described semiconductor device also comprises the splicing ear of the described silicon nanowires of connection being positioned at described silicon nanowires two ends, and wherein, described splicing ear is identical with the doping type of described second epi dopant layer.
15. semiconductor device as claimed in claim 10, it is characterized in that, described first epi dopant layer is selected from least one in silicon, germanium silicon, GaAs or the carbon silicon with the second doping type, and described second epi dopant layer is selected from least one in silicon, germanium silicon, GaAs or the carbon silicon with the first doping type.
16. semiconductor device as described in any one of claim 10 to 15, it is characterized in that, also comprise interlayer dielectric layer and the interconnection structure for connecting described silicon nanowires, described first epi dopant layer and described second epi dopant layer, further, the region contacted with described silicon nanowires, described first epi dopant layer and described second epi dopant layer at described interconnection structure is provided with metal silicide.
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| CN1989621A (en) * | 2004-07-20 | 2007-06-27 | 皇家飞利浦电子股份有限公司 | Semiconductor device and method of manufacturing the same |
| US20090227107A9 (en) * | 2004-02-13 | 2009-09-10 | President And Fellows Of Havard College | Nanostructures Containing Metal Semiconductor Compounds |
| CN104217945A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Bipolar transistor, semiconductor device and bipolar transistor forming method |
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| US20090227107A9 (en) * | 2004-02-13 | 2009-09-10 | President And Fellows Of Havard College | Nanostructures Containing Metal Semiconductor Compounds |
| CN1989621A (en) * | 2004-07-20 | 2007-06-27 | 皇家飞利浦电子股份有限公司 | Semiconductor device and method of manufacturing the same |
| CN104217945A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Bipolar transistor, semiconductor device and bipolar transistor forming method |
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