CN104821771B - Photoelectric code disk orthogonal frequency division method based on CPLD - Google Patents
Photoelectric code disk orthogonal frequency division method based on CPLD Download PDFInfo
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Abstract
The photoelectric code disk orthogonal frequency division method based on CPLD that the present invention is provided, including：Divider ratio is passed through into parallel data address bus writing complex programmable logic device (CPLD)；The first phase signals and the second phase signals of photoelectric code disk are subjected to level Four filtering respectively using high frequency clock and obtain the first phase signals of level Four filtering and the second phase signals of level Four filtering；The phase relation for the second phase signals that the first phase signals and the level Four filtered according to the level Four are filtered determines the direction signal of motor；The logic level of the logic level of first phase signals and second phase signals is subjected to the quadruple signal that logical operation obtains the motor；The quadruple signal determines frequency-divided feedback signal according to the direction signal.The present invention can be divided to orthogonal pulses, and effectively reduce the use of CPLD gate.
Description
Technical field
The present invention relates to AC Servo Technology, more particularly to a kind of photoelectric code disk orthogonal frequency division method based on CPLD.
Background technology
In order to realize that the position to AC servo motor is accurately controlled, it is desirable to the position of the rotor of servomotor must be accurate
Quickly detect.Increment photoelectric code disk is the sensor for detecting angular displacement or angular speed, its simple in construction, mechanical longevity
Life length, is widely used in AC servo.In practice, incremental optical-electricity encoder is installed with motor coaxle, exports A
Phase, B phases and the road signal of Z phases three, wherein, the phase difference of A phases and B phases is 90 degree, and Z phase motors every revolution produces a pulse,
For position correction.
In AC servo, increment photoelectric code disk generally requires to feed back to host computer, the work for mainly having two aspects
With：First, the operation of servomotor is monitored, once motor is not run according to the path of planning, then host computer is pulled up a horse to send and cut
Break signal, motor stalls；Second, host computer needs to show the running status of motor, user-friendly.But host computer
Can not the directly higher pulse of receives frequency, so needing orthogonal pulses feeding back to host computer again after frequency dividing.Orthogonal arteries and veins
Rushing frequency dividing needs to consider direction, it is necessary to ensure that pulse number can not be lost when motor positive and inverse switches, and ensures that A phases, B are believed
Number frequency dividing after phase keep 90 degree.
The content of the invention
Orthogonal pulses can be divided by the photoelectric code disk orthogonal frequency division method based on CPLD that the present invention is provided, and
Effectively reduce the use of CPLD gate.
According to an aspect of the present invention there is provided a kind of photoelectric code disk orthogonal frequency division method based on CPLD, including：
Divider ratio is passed through into parallel data address bus writing complex PLD (Complex
Programmable Logic Device, CPLD)；The first phase signals of photoelectric code disk and second are believed using high frequency clock
Level Four filtering is carried out number respectively obtains the first phase signals of level Four filtering and the second phase signals of level Four filtering；According to the level Four
The phase relation of first phase signals of filtering and the second phase signals of level Four filtering determines the direction signal of motor；Will be described
The logic level of the logic level of first phase signals and second phase signals carries out four times that logical operation obtains the motor
Frequency signal；The quadruple signal determines frequency-divided feedback signal according to the direction signal.
Photoelectric code disk orthogonal frequency division method provided in an embodiment of the present invention based on CPLD, by by the first phase signals and
Biphase signaling carries out level Four filtering and obtains the first phase signals of level Four filtering and the second phase signals of level Four filtering respectively, according to four
The phase relation of first phase signals of level filtering and the second phase signals of level Four filtering determines the direction signal of motor, by the first phase
The logic level of the logic level of signal and the second phase signals carries out the quadruple signal that logical operation obtains the motor, so that
Quadruple signal is determined frequency-divided feedback signal according to direction signal, orthogonal pulses can be divided, and effectively reduce
The use of CPLD gate.
Brief description of the drawings
Fig. 1 is the flow chart of the photoelectric code disk orthogonal frequency division method provided in an embodiment of the present invention based on CPLD；
Fig. 2 is the side of the first phase signals that level Four provided in an embodiment of the present invention is filtered and the second phase signals of level Four filtering
To schematic diagram；
Fig. 3 is the another of the second phase signals that the first phase signals and level Four that level Four provided in an embodiment of the present invention is filtered are filtered
One direction schematic diagram；
Fig. 4 is simulation result schematic diagram provided in an embodiment of the present invention.
Embodiment
The photoelectric code disk orthogonal frequency division method provided in an embodiment of the present invention based on CPLD is carried out below in conjunction with the accompanying drawings detailed
Thin description.
Fig. 1 is the flow chart of the photoelectric code disk orthogonal frequency division method provided in an embodiment of the present invention based on CPLD.
Reference picture 1, in step S101, parallel data address bus writing complex programmable logic device is passed through by divider ratio
Part CPLD.
Here, divider ratio can be N, N-1,2*N, 2*N-1,3*N, 3*N-1 and 4*N-1.Digital Signal Processing
(digital signal processing, DSP) is write divider ratio in CPLD by parallel data address bus, and DSP can
Think DSP2812.
In step S102, the first phase signals and the second phase signals of photoelectric code disk are subjected to level Four respectively using high frequency clock
Filtering obtains the first phase signals of level Four filtering and the second phase signals of level Four filtering.
In the phase of step S103, the first phase signals and the level Four filtered according to the level Four the second phase signals filtered
Position relation determines the direction signal of motor.
In step S104, the logic level of the logic level of first phase signals and second phase signals is patrolled
Collect the quadruple signal that computing obtains the motor.
Here, logic level refers to the first level and second electrical level, wherein, the first level is " 1 ", and second electrical level is " 2 ",
Logical operation refers to " with " and " mutually or " computing.
In step S105, the quadruple signal determines frequency-divided feedback signal according to the direction signal.
Further, it is described that divider ratio is passed through into parallel data address bus writing complex programmable logic device (CPLD)
Including：
The CPLD judges whether write signal and chip selection signal gate；
If write signal and chip selection signal gating, CPLD is write by divider ratio by parallel data address bus.
Here, CPLD be DSP2812 peripheral circuit regions, CPLD judge DSP2812 write signal and chip selection signal whether
Gating, if gating, divider ratio is write in CPLD.
If data/address line is " 000000100 ", write-in divider ratio N；If data/address line is
" 000000101 ", then write N-1；If data/address line is " 000000110 ", 2*N is write；If data/address line is
" 000000111 ", then write 2*N-1；If data/address line is " 000001000 ", 3*N is write；If data/address line
For " 000001001 ", then 3*N-1 is write；If data/address line is " 000001010 ", 4*N-1 is write.
Further, it is described that the first phase signals and the second phase signals of photoelectric code disk are carried out four respectively using high frequency clock
Level filtering, which obtains the first phase signals of level Four filtering and the second phase signals of level Four filtering, to be included：
First phase signals and second phase signals of the photoelectric code disk are passed through using the high frequency clock non-
Obstruction assignment method obtains the first phase signals of non-obstruction assignment and the second phase signals of non-obstruction assignment；
The first phase signals and first phase signals of the non-obstruction assignment are carried out logical operation and obtain the level Four
First phase signals of filtering；
The second phase signals and second phase signals of the non-obstruction assignment are carried out logical operation and obtain the level Four
Second phase signals of filtering.
Here, high frequency clock is 30MHZ.First phase signals and the second phase signals are carried out after non-obstruction assignment, obtain non-
Block the first phase signals of assignment and the second phase signals of non-obstruction assignment.It is non-obstruction assignment the first phase signals be specially
Buf1a, buf2a and buf3a, the second phase signals of non-obstruction assignment are specially buf1b, buf2b, buf3b.
By the first phase signals and buf1a, buf2a, buf3a phase of input or for 0, then the first phase signals of level Four filtering are
0；By the first phase signals and buf1a, buf2a, buf3a phase of input with being 1, then filtered first phase signals of level Four are 1.
By the second phase signals and buf1b, buf2b, buf3b phase of input or for 0, then the second phase signals of level Four filtering are
0；By the second phase signals and buf1b, buf2b, buf3b phase of input with being 1, then filtered second phase signals of level Four are 1.
Further, the phase relation includes lead and lag, first phase signals filtered according to the level Four
The phase relation of the second phase signals filtered with the level Four determines that the direction signal of motor includes：
If the second phase signals of the advanced level Four filtering of the first phase signals of the level Four filtering, the motor
Direction signal is the first level；
If the second phase signals of the delayed level Four filtering of the first phase signals of the level Four filtering, the motor
Direction signal is second electrical level.
Here, phase relation refers to 90 degree of the second phase signals or four of the first phase signals advanced level Four filtering of level Four filtering
90 degree of the second phase signals of the delayed level Four filtering of the first phase signals of level filtering.
If 90 degree of the second phase signals of the advanced level Four filtering of the first phase signals of level Four filtering, the direction signal of motor
For the first level, wherein, the first level is 1, referring in particular to the of level Four provided in an embodiment of the present invention filtering as shown in Figure 2
The direction schematic diagram of one phase signals and the second phase signals of level Four filtering, when the first phase signals rising edge that level Four is filtered arrives
When, the second phase signals of level Four filtering are 0；When the first phase signals trailing edge that level Four is filtered arrives, the second of level Four filtering
Phase signals are 1；When the second phase signals phase rising edge that level Four is filtered arrives, the first phase signals of level Four filtering are 1；Work as level Four
When second phase signals trailing edge of filtering arrives, the first phase signals of level Four filtering are 0.
If 90 degree of the second phase signals of the delayed level Four filtering of the first phase signals of level Four filtering, the direction signal of motor
For second electrical level, wherein, second electrical level is 0, referring in particular to the of level Four provided in an embodiment of the present invention filtering as shown in Figure 3
The other direction schematic diagram of one phase signals and the second phase signals of level Four filtering, when the first phase signals rising edge that level Four is filtered is arrived
When coming, the second phase signals of level Four filtering are 1；When the first phase signals trailing edge that level Four is filtered arrives, the of level Four filtering
Biphase signaling is 0；When the second phase signals phase rising edge that level Four is filtered arrives, the first phase signals of level Four filtering are 0；When four
When second phase signals trailing edge of level filtering arrives, the first phase signals of level Four filtering are 1.
Further, the quadruple signal obtains frequency-divided feedback signal according to the direction signal and included：
The quadruple signal determines the value of pulse counter according to the direction signal；
The frequency-divided feedback signal is determined according to the value of the pulse counter.
Further, the quadruple signal determines that the value of pulse counter includes according to the direction signal：
If the direction signal is the first level, the pulse counter carries out add operation；
If the direction signal is second electrical level, the pulse counter carries out subtraction.
Here, if pulse scaler overflows, according to direction signal, new value is assigned to pulse counter again.
Further, the frequency-divided feedback signal includes the phase signals of frequency-divided feedback first and the phase signals of frequency-divided feedback second,
The value according to the pulse counter determines that the frequency-divided feedback signal includes：
If the value of the pulse counter is in the first threshold of the divider ratio, the phase signals of frequency-divided feedback first
For high level；
If the value of the pulse counter is in the Second Threshold of the divider ratio, the phase signals of frequency-divided feedback first
For low level；
If the value of the pulse counter is in the 3rd threshold value of the divider ratio, the phase signals of frequency-divided feedback second
For high level；
If the value of the pulse counter is in the 4th threshold value of the divider ratio, the phase signals of frequency-divided feedback second
For low level.
Specifically, if the value of the pulse counter is in 0~2N-1 scopes, the phase signals of frequency-divided feedback first are high electricity
It is flat；
If the value of the pulse counter is in 2N~4N-1 scopes, the phase signals of frequency-divided feedback first are low level；
If the value of the pulse counter is in N~3N-1 scopes, the phase signals of frequency-divided feedback second are high level；
If the value of the pulse counter is in 3N~4N-1 and 0~N-1 scopes, the phase signals of frequency-divided feedback second are low
Level.
Fig. 4 is simulation result schematic diagram provided in an embodiment of the present invention.Reference picture 4, wherein clk are high frequency clock signal,
Nrst is asynchronous reset signal, and enc_a and enc_b are respectively the first phase signals and the second phase signals, and qepdir is the side of motor
To signal, qepclk is the quadruple signal of motor, and FbEnc_A, FbEnc_B are respectively the phase signals of frequency-divided feedback first and frequency dividing
Feed back the second phase signals.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (4)
1. a kind of photoelectric code disk orthogonal frequency division method based on CPLD, it is characterised in that methods described includes：
Step S101, parallel data address bus writing complex programmable logic device (CPLD) is passed through by divider ratio；
The first phase signals and the second phase signals of photoelectric code disk are carried out level Four using high frequency clock and filtered by step S102 respectively
Second phase signals of the first phase signals and the level Four filtering filtered to level Four：
First phase signals and second phase signals of the photoelectric code disk are passed through into non-obstruction using the high frequency clock
Assignment method obtains the first phase signals of non-obstruction assignment and the second phase signals of non-obstruction assignment；
First phase signals of non-obstruction assignment are specially buf1a, buf2a and buf3a, and the second phase signals of non-obstruction assignment are specific
For buf1b, buf2b, buf3b；
By the first phase signals and buf1a, buf2a, buf3a phase of input or for 0, then the first phase signals of level Four filtering are 0；Will
The first phase signals and buf1a, buf2a, buf3a phase of input are with being 1, then filtered first phase signals of level Four are 1；
By the second phase signals and buf1b, buf2b, buf3b phase of input or for 0, then the second phase signals of level Four filtering are 0；Will
The second phase signals and buf1b, buf2b, buf3b phase of input are with being 1, then filtered second phase signals of level Four are 1；
Step S103, the phase relation for the second phase signals that the first phase signals and the level Four filtered according to the level Four are filtered
Determine the direction signal of motor；
Step S104, logical operation is carried out by the logic level of the logic level of first phase signals and second phase signals
Obtain the quadruple signal of the motor；
Step S105, the quadruple signal determines frequency-divided feedback signal according to the direction signal, including：The quadruple letter
The value of pulse counter number is determined according to the direction signal；The frequency-divided feedback letter is determined according to the value of the pulse counter
Number；
The frequency-divided feedback signal includes the phase signals of frequency-divided feedback first and the phase signals of frequency-divided feedback second, described according to the arteries and veins
The value for rushing counter determines that the frequency-divided feedback signal includes：
If the value of the pulse counter is in the first threshold of the divider ratio, the phase signals of frequency-divided feedback first are height
Level；
If the value of the pulse counter is in the Second Threshold of the divider ratio, the phase signals of frequency-divided feedback first are low
Level；
If the value of the pulse counter is in the 3rd threshold value of the divider ratio, the phase signals of frequency-divided feedback second are height
Level；
If the value of the pulse counter is in the 4th threshold value of the divider ratio, the phase signals of frequency-divided feedback second are low
Level.
2. according to the method described in claim 1, it is characterised in that described to write divider ratio by parallel data address bus
Entering complex programmable logic device (CPLD) includes：
The CPLD judges whether write signal and chip selection signal gate；
If the write signal and chip selection signal gating, the parallel data address bus is passed through by the divider ratio
Write the CPLD.
3. according to the method described in claim 1, it is characterised in that the phase relation includes lead and lag, the basis
The phase relation of first phase signals of the level Four filtering and the second phase signals of level Four filtering determines the direction letter of motor
Number include：
If the second phase signals of the advanced level Four filtering of the first phase signals of the level Four filtering, the direction of the motor
Signal is the first level；
If the second phase signals of the delayed level Four filtering of the first phase signals of the level Four filtering, the direction of the motor
Signal is second electrical level.
4. according to the method described in claim 1, it is characterised in that the quadruple signal determines arteries and veins according to the direction signal
Rushing the value of counter includes：
If the direction signal is the first level, the pulse counter carries out add operation；
If the direction signal is second electrical level, the pulse counter carries out subtraction.
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|---|---|---|---|---|
| CN102394639A (en) * | 2011-10-26 | 2012-03-28 | 深圳市三艾科技有限公司 | Method to realize arbitrary-number frequency dividing of servo driver and arbitrary-number frequency divider based on field programmable gate array (FPGA) |
| CN102840847A (en) * | 2012-09-14 | 2012-12-26 | 昆山允可精密工业技术有限公司 | Sheet thickness measuring system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102394639A (en) * | 2011-10-26 | 2012-03-28 | 深圳市三艾科技有限公司 | Method to realize arbitrary-number frequency dividing of servo driver and arbitrary-number frequency divider based on field programmable gate array (FPGA) |
| CN102840847A (en) * | 2012-09-14 | 2012-12-26 | 昆山允可精密工业技术有限公司 | Sheet thickness measuring system |
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| Title |
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| 基于CPLD的数字交流伺服系统接口设计;沈安文等;《微电机》;20061231;第39卷(第3期);第54-56页 * |
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