CN104810261B - A kind of two-sided method for annealing of semi-conductor silicon chip and device - Google Patents
A kind of two-sided method for annealing of semi-conductor silicon chip and device Download PDFInfo
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- 238000000137 annealing Methods 0.000 title claims abstract description 92
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 82
- 239000010703 silicon Substances 0.000 title claims abstract description 82
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 81
- 238000000034 method Methods 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052796 boron Inorganic materials 0.000 claims abstract description 15
- 238000002161 passivation Methods 0.000 claims abstract description 13
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 11
- 239000011574 phosphorus Substances 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims description 24
- 238000005224 laser annealing Methods 0.000 claims description 18
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 5
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000009434 installation Methods 0.000 abstract description 3
- 125000004122 cyclic group Chemical group 0.000 abstract description 2
- 238000006263 metalation reaction Methods 0.000 abstract description 2
- 239000000243 solution Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000004913 activation Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 230000007306 turnover Effects 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000011324 bead Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention belongs to semiconductor manufacturing facilities and technical field, and in particular to a kind of two-sided method for annealing of semi-conductor silicon chip and device.The method first carries out front side of silicon wafer and backside particulate injection, then carries out front side of silicon wafer and the back side is annealed simultaneously, finally completes front side of silicon wafer metal connecting layer, metal layer and passivation layer process.Described device includes front annealing device, back side annealing device and is arranged between the cyclic annular clamping fixture for silicon wafer for carrying silicon wafer.Technical solution provided by the invention is had the advantage that compared with prior art using annealing emitter principle, and twice annealing is merged into primary annealing and is completed, respective metal and passivation layer finally complete；It avoids traditional single back side annealing process silicon wafer and is unable to automatic turning problem, technology by sucking pen by manually completing at present；Other than effectively improving the activity ratio of boron and phosphorus, the depth and width of buffer area can also be adjusted；Production process is simplified, while improving utilization rate of equipment and installations, also reduces manufacturing cost.
Description
Technical field
The invention belongs to semiconductor manufacturing facilities and technical field, and in particular to a kind of two-sided method for annealing of semi-conductor silicon chip
And device.
Background technique
In semiconductor devices manufacturing process, must there could be electric work by the heat treatment of sufficiently high temperature after ion implanting
Property, and damage when impurity injects to silicon base lattice is eliminated, this process is called annealing.Annealing way includes boiler tube at present
(Furnace), rapid thermal treatment (RTP) and laser annealing (LaserAnneal) etc..
With the development of IC device technology, the silicon wafer of current many semiconductor devices needs to carry out ion note in tow sides
Enter, such as IGBT device, be made of MOSFET and BJT, most common IGBT technology is field cut-off IGBT technology (FS now
IGBT), as shown in Figure 1, device successively includes source-drain area 11, drift region 12 and field cutoff layer etc., midfield cut-off from top to bottom
Layer can only include boron doped back side p type island region domain 13, can also increase the back side between drift region 12 and back side n-type region 14
P type island region domain 13, therefore other than positive normal source and drain ion implanting, the back side will also form a field cutoff layer, need to carry out
Backside particulate injection.
Two-sided IGBT is a kind of New IGBT structure design, is the extension of traditional NPT structure, is equivalent to two IGBT devices
Combination, tow sides also can all carry out the ion implanting of grid source-drain electrode, and the impurity activation of grid source-drain electrode needs twice annealing
Technique, especially back process are needed silicon wafer turnover, and existing 8 cun or less Fab do not have automatic conveying device, to granularity
Difficulty is controlled to increase.
In addition there are also Japan Roma Corporation power devices newly developed, and it is excellent to have both superjunction (SJ) type power MOSFET and IGBT
The novel high voltage switch element of good characteristic, is named as " Hybrid MOS ".Hybrid MOS had both had SJ type power
The high-speed switch characteristic and good low current performance of MOSFET has front but also with the high voltage characteristic of IGBT
CoolMOS and back surface field end structure, therefore there is also backside particulate injections.
It can be seen that, or it will be used double in more and more semiconductor power device manufacturing process from the above citing
The ion implanting in face, and more advanced heat treatment mode after injecting at present --- RTP and Laser Anneal can only to silicon wafer into
The annealing of row single side.By taking FS IGBT annealing process as an example, as shown in Fig. 2, first completing the injection of front grid source-drain electrode, annealed by RTP
Front Doped ions are activated, front metal layer and passivation layer process are then completed；Then silicon wafer turnover is subjected to the thinned and back side
Ion implanting can only realize back side Doped ions using laser annealing technique since thin slice is limited by front metal heatproof condition
Activation.The annealing process of the silicon wafer of two-sided ion implanting is first to carry out positive ion implanting and anneal for the first time；Then gold is carried out
Belong to articulamentum, metal layer, the front such as passivation layer technique；Silicon wafer turnover is subjected to silicon chip back side ion implanting again and is moved back for the second time
Fire.Single side annealing way not only cumbersome twice in this way, production cost and period rise, and the utilization rate of annealing device
It does not give full play to, and because being ready for metallization, silicon temperature can not be more than 500 degree, therefore second is annealed
When, temperature is unsuitable excessively high, but the activity ratio of boron and phosphorus is all relatively low at low temperature < 10%, and note boron is formed under this condition
Emitter concentration it is not dense enough, also not deep enough, emission effciency is relatively low, so being known as transparent emitter.To improve the back side
The activity ratio of boron and phosphorus is injected, annealing temperature is necessarily placed at 700 degree or more, and the emission effciency of emitter can be mentioned obviously at this time
Height claims annealing emitter.
RTP equipment mainly includes the parts such as the lamp source of cellular arrangement, light source cooling chamber, clamping fixture for silicon wafer, and RTP lamp source can be with
Using halogen lamp or xenon lamp, the arrangement mode of lamp can use cellular lamp bead or fluorescent tube arranged in parallel, these lamps are ok
Subregion controls its watt level to enhance the uniformity of silicon wafer heating；And laser annealing apparatus specifically includes that laser, light beam
Processing system, clamping fixture for silicon wafer, scattering optical detection and temperature feedback system, the scattering optical detection and temperature feedback system are for increasing
Strong temperature control capability, laser annealing wavelength can require to select 308nm, 527nm or 10.6um etc., laser according to concrete technology
Incident angle can be vertical incidence or oblique incidence.
Summary of the invention
The technical problem to be solved by the present invention is to double secondary single side annealing process in the prior art are cumbersome, at high cost, the period
Long, utilization rate of equipment and installations is low, and annealing way is limited, in order to overcome the above deficiency, provides that a kind of semi-conductor silicon chip is two-sided to move back
Ignition method and device.
In order to solve the above-mentioned technical problem, the technical scheme is that the two-sided method for annealing of the semi-conductor silicon chip, first
Front side of silicon wafer and backside particulate injection are carried out, then front side of silicon wafer is carried out and the back side is annealed simultaneously, finally completes front side of silicon wafer gold
Belong to articulamentum, metal layer and passivation layer process.It is two-sided while annealing and saved process, efficiency is improved, is reduced costs, finally
Metal connecting layer, metal layer and passivation layer are completed, annealing temperature can be made unrestricted.
Preferably, when the semi-conductor silicon chip back side forms field cutoff layer using boron doping, specifically includes the following steps: first
First complete the ion injecting process of front side of silicon wafer；Then the ion injecting process at the back side is completed；Secondly above semi-conductor silicon chip
With it is following while two-sided annealing is carried out to front and back, realize two-sided Doped ions activation；Finally complete front side of silicon wafer metal
Articulamentum, metal layer and passivation layer process.
Preferably, when the semi-conductor silicon chip back side forms field cutoff layer using boron and phosphorus doping, following step is specifically included
It is rapid: to complete positive ion injecting process first；Then back side phosphorus doping is completed；Secondly same above and below from semi-conductor silicon chip
When two-sided annealing is carried out to front and back, complete the activation of positive back side Doped ions and adjust the depth and width of back side buffer layer
Degree；Back side boron doping is completed later and single side annealing is carried out to the back side again；Finally complete front side of silicon wafer metal connecting layer, metal
Layer and passivation layer process.
Preferably, the temperature range of the two-sided annealing is 700-1500 degree, and the temperature range of the single side annealing is
Less than or equal to 800 degree.
Preferably, front annealing way and back side annealing way can be same or different when the two-sided annealing, move back
Fiery mode is laser annealing or rapid thermal annealing.
Preferably, the two-sided method for annealing of semi-conductor silicon chip can be used for FS IGBT, two-sided IGBT or HybridMOS device
The preparation of part.
The present invention also provides a kind of devices for the two-sided annealing of semi-conductor silicon chip, including front annealing device, the back side
Annealing device and it is arranged between the cyclic annular clamping fixture for silicon wafer for carrying silicon wafer.
Preferably, the front annealing device and back side annealing device can be all RTP equipment or laser annealing apparatus,
The two can also be different, respectively RTP equipment and laser annealing apparatus.
Preferably, the clamping fixture for silicon wafer is including inner ring, to be higher by the outer ring and ring of inner ring with circular ring structure jaggy
Upper notch.Outer ring is used for the fixation of clamping fixture for silicon wafer, and inner ring is fixed for position of the silicon wafer on clamping fixture for silicon wafer, and notch is used on ring
The pick-and-place of silicon wafer.
Technical solution provided by the invention has the advantage that compared with prior art
1. twice annealing is merged into primary annealing and is completed, respective metal and passivation layer are most using annealing emitter principle
After complete；
2. avoiding traditional single back side annealing process silicon wafer is unable to automatic turning problem, technology is by manually by suction at present
Pen is completed；
3. the depth and width of buffer area can also be adjusted other than effectively improving the activity ratio of boron and phosphorus；
4. simplifying production process, while utilization rate of equipment and installations is improved, also reduces manufacturing cost.
Detailed description of the invention
Fig. 1 is FS IGBT structure schematic diagram；
Fig. 2 is FS IGBT annealing process schematic diagram in the prior art；
Fig. 3 is the two-sided one specific embodiment structural schematic diagram of annealing device of semi-conductor silicon chip of the present invention；
Fig. 4 is one specific embodiment structural schematic diagram of clamping fixture for silicon wafer of the present invention；
Fig. 5 is the two-sided method for annealing procedure chart that high pressure FS IGBT device is used for described in embodiment 1；
Fig. 6 is the two-sided annealing device structural schematic diagram of two-sided RTP equipment described in embodiment 1；
Fig. 7 is the two-sided method for annealing procedure chart that two-way IGBT device is used for described in embodiment 2；
Fig. 8 is the two-sided annealing device structural schematic diagram of double-sided laser annealing device described in embodiment 2；
Fig. 9 is the two-sided method for annealing procedure chart that Hybrid MOS device is used for described in embodiment 3；
Figure 10 is RTP equipment in front described in embodiment 3, the two-sided annealing device structural representation of backside laser annealing device
Figure；
As shown in the figure: 11- source-drain area, the drift region 12-, the back side 13- p type island region domain, the back side 14- n-type region, 15-P type extend
Region；The front 21- annealing device, the back side 22- annealing device, 23- silicon wafer, 24- clamping fixture for silicon wafer, 241- inner ring, 242- outer ring,
243- notch.
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing:
As shown in figure 3, being used for the device of the two-sided annealing of semi-conductor silicon chip, including front annealing device 21, back side annealing are set
Standby 22 and be arranged between for carrying the clamping fixture for silicon wafer 24 of silicon wafer 23.
As shown in figure 4, the clamping fixture for silicon wafer 24 is including inner ring 241, to be higher by inner ring 241 with circular ring structure jaggy
Outer ring 242 and ring on notch 243, bis- alignments of CCD can be added using prealignment, by manipulator adjust automatically silicon wafer 23
Behind position, then notch 243 is protruded by manipulator, silicon wafer 23 is placed in fixture inner ring 241, to guarantee upper piece precision.
The front annealing device 21 and back side annealing device 22 can be all RTP equipment or laser annealing apparatus, the two
It can also be different, i.e. respectively RTP equipment and laser annealing apparatus.
Embodiment 1
As shown in figure 5, the two-sided method for annealing of semi-conductor silicon chip of the present invention is used for two-sided the moving back of high pressure FS IGBT device
Fiery process, mainly comprises the steps that
S11 completes the ion injecting process of front side of silicon wafer source-drain area 11, that is, grid electrode front, source electrode and drain electrode are (below
Referred to as " grid source-drain electrode ") p-type (boron) and N-type (phosphorus) doping；
S12 silicon chip back side injects phosphorus, then carries out simultaneously to front and back above and below from semi-conductor silicon chip two-sided
Annealing when two-sided annealing, two-sided can use rapid thermal anneal process, that is, as shown in fig. 6, front annealing device 21 and back
Face annealing device 22 is RTP equipment；Or front is rapid thermal anneal process and the back side is laser annealing, front and back
Parameter and annealing is set separately as needed, just anneals in face of grid source-drain electrode, while the back side is annealed using higher temperature,
Such as 700 DEG C -1500 DEG C depth needed for back side n-type region 14 of annealing and diffuse out；
Boron is injected in S13 silicon chip back side p type island region domain 13, and is annealed with lower temperature single side, such as 800 DEG C of annealing, obtains class
Like transparent emitter；
S14 (not shown) finally completes the techniques such as metal connecting layer, metal layer and the passivation layer of front side of silicon wafer.
Embodiment 2
As shown in fig. 7, the two-sided method for annealing of semi-conductor silicon chip of the present invention is used for the two-sided annealing of two-way IGBT device
Process mainly comprises the steps that
S21 completes the ion injecting process of front side of silicon wafer source-drain area 11, that is, the p-type and N-type of front grid source-drain electrode are mixed
Miscellaneous and back side p type island region domain 13 p-type is adulterated；
S22 completes the ion injecting process of silicon chip back side source-drain area 11, that is, the p-type and N-type of back side grid source-drain electrode are mixed
It is miscellaneous and and back side p type island region domain 13 p-type doping；
S23 carries out two-sided annealing to front and back simultaneously above and below from semi-conductor silicon chip, can be with when two-sided annealing
It is two-sided using rapid thermal anneal process or two-sided using laser annealing technique, that is, as shown in figure 8, front annealing device
21 and back side annealing device 22 be laser annealing apparatus, be arranged same process parameter, realize two-sided doping by once annealing
It is ion-activated, it is preferable that 700 DEG C -1500 DEG C of temperature；
S24 (not shown) finally completes the techniques such as metal connecting layer, metal layer and the passivation layer of front side of silicon wafer.
Embodiment 3
As shown in figure 9, the two-sided method for annealing of semi-conductor silicon chip of the present invention is moved back for the two-sided of Hybrid MOS device
Fiery process, mainly comprises the steps that
S31 completes the ion injecting process of front side of silicon wafer source-drain area 11, that is, the p-type and n-type doping of grid source-drain electrode；
S32 front side of silicon wafer is filled by multiple extension into the extension vertical in silicon wafer of formation p-type elongated area 15；
S33 silicon chip back side injects phosphorus, then carries out simultaneously to front and back above and below from semi-conductor silicon chip two-sided
Annealing, when two-sided annealing, can front be rapid thermal anneal process and the back side is laser annealing, that is to say, that it is as shown in Figure 10,
Front annealing device 21 is RTP equipment, and back side annealing device 22 is laser annealing apparatus；Or two-sided is rapid thermal annealing work
Different technological parameters is arranged in skill, front and back, just anneals in face of source-drain area 11 and p-type elongated area 15, carries on the back simultaneously
Face using temperature it is higher annealing and spread release back side n-type region 14 needed for depth, it is preferable that temperature range be 700 DEG C-
1500℃；
Boron is injected in S34 silicon chip back side p type island region domain 13, and is annealed with lower temperature single side, obtains similar transparent emitter,
Preferably, temperature is less than or equal to 800 DEG C；
S35 (not shown) finally completes the techniques such as metal connecting layer, metal layer and the passivation layer of front side of silicon wafer.
Claims (5)
1. a kind of two-sided method for annealing of semi-conductor silicon chip, which is characterized in that when the semi-conductor silicon chip back side uses boron and phosphorus doping shape
When at field cutoff layer, specifically includes the following steps: completing positive ion injecting process first；Then back side phosphorus doping is completed；
Secondly two-sided annealing is carried out to front and back simultaneously above and below from semi-conductor silicon chip, completes swashing for positive back side Doped ions
Depth and width that are living and adjusting back side buffer layer；Back side boron doping is completed later and single side annealing is carried out to the back side again；Most
Front side of silicon wafer metal connecting layer, metal layer and passivation layer process are completed afterwards.
2. the two-sided method for annealing of a kind of semi-conductor silicon chip according to claim 1, which is characterized in that the temperature of the two-sided annealing
Degree range is 700-1500 degree, and the temperature range of the single side annealing is less than or equal to 800 degree.
3. the two-sided method for annealing of a kind of semi-conductor silicon chip according to claim 1, which is characterized in that for FS IGBT or
The preparation of Hybrid MOS device.
4. the two-sided method for annealing of a kind of semi-conductor silicon chip according to claim 3, which is characterized in that prepare the Hybrid
MOS device further includes being filled by multiple extension into formation boron doped region when carrying out the positive ion injecting process
In the vertical extension of silicon wafer.
5. the two-sided method for annealing of a kind of semi-conductor silicon chip according to claim 1, which is characterized in that when the two-sided annealing just
Face annealing way and back side annealing way are same or different, and annealing way is laser annealing or rapid thermal annealing.
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| CN116072530B (en) * | 2022-12-01 | 2024-01-19 | 北京核力同创科技有限公司 | Preparation method of FS-IGBT back electrode |
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| CN102420133A (en) * | 2011-09-30 | 2012-04-18 | 上海华虹Nec电子有限公司 | manufacturing method of IGBT device |
| CN103117302A (en) * | 2013-03-06 | 2013-05-22 | 江苏物联网研究发展中心 | Back structure of FS type IGBT device |
| CN104347400A (en) * | 2013-07-26 | 2015-02-11 | 无锡华润上华半导体有限公司 | Manufacturing method for non-punch-through type insulated gate bipolar transistor |
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| CN203288595U (en) * | 2013-03-26 | 2013-11-13 | 杭州士兰集成电路有限公司 | Power semiconductor device |
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|---|---|---|---|---|
| CN101106080A (en) * | 2006-07-14 | 2008-01-16 | 台湾积体电路制造股份有限公司 | Method of heating semiconductor wafer |
| CN102244099A (en) * | 2011-06-23 | 2011-11-16 | 西安电子科技大学 | SiC IEMOSFET (Implantation and Epitaxial Metal-Oxide -Semiconductor Field Effect Transistor) device with epitaxy channel and manufacturing method of SiC IEMOSFET device |
| CN102420133A (en) * | 2011-09-30 | 2012-04-18 | 上海华虹Nec电子有限公司 | manufacturing method of IGBT device |
| CN103117302A (en) * | 2013-03-06 | 2013-05-22 | 江苏物联网研究发展中心 | Back structure of FS type IGBT device |
| CN104347400A (en) * | 2013-07-26 | 2015-02-11 | 无锡华润上华半导体有限公司 | Manufacturing method for non-punch-through type insulated gate bipolar transistor |
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