CN104809072A

CN104809072A - Automatic mensurability design method of Perl-based EDIF netlist-grade circuit automatic mensurability design system

Info

Publication number: CN104809072A
Application number: CN201510267393.7A
Authority: CN
Inventors: 俞洋; 陈诚; 彭喜元; 乔立岩
Original assignee: Harbin Institute of Technology
Current assignee: Harbin Institute of Technology
Priority date: 2013-06-28
Filing date: 2013-06-28
Publication date: 2015-07-29
Also published as: CN103294600B; CN103294600A

Abstract

The invention provides an automatic mensurability design method of a Perl-based EDIF netlist-grade circuit automatic mensurability design system and relates to an EDIF netlist-grade circuit automatic mensurability design system and an automatic mensurability design method which are used for adapting to the demand of EDIF netlist-grade circuit automatic mensurability design. A circuit source code resolving module is used for analyzing the EDIF netlist-grade description of a digital logic circuit; a trigger modification module is used for modifying the mensurability of all triggers by use of an EDIF language; a Verilog packaging module is used for packaging the Verilog of an EDIF netlist description circuit; a scanning link connection module is used for finishing circuit scanning link design for the EDIF netlist description circuit by use of a Verilog language; a mensurability circuit generating module is used for packaging the Verilog of the circuit once again; a testing verification module is used for generating a test file and verifying the circuit after mensurability design. The automatic mensurability design method is applicable to the EDIF netlist-grade circuit automatic mensurability design.

Description

Based on the automatic design for Measurability method of the automatic design for Measurability system of the EDIF net table level circuit of Perl

Technical field

The present invention relates to a kind of automatic design for Measurability system of EDIF net table level circuit and automatic design for Measurability method.

Background technology

In the current development along with semiconductor technology, integrated circuit (IC) chip (IC) is widely used, and ensures that the reliability of integrated circuit (IC) chip becomes a major issue.The method of testing IC becomes the main path solving IC reliability, but the low problem of the measurability with the IC of sophisticated functions seriously constrains the validity of IC test.And controllability and the ornamental that design for Measurability effectively can improve circuit is carried out to IC, substantially increase the measurability of chip, IC is tested can effectively carry out.

The design for Measurability of circuit is exactly under the prerequisite not affecting circuit function, transforms the structure of primary circuit, and the node making inside circuit originally not have controllability and objectivity obtains these character, is convenient to test.Conventional method carries out measurability transformation to the trigger used in primary circuit, become measurability trigger, then improved trigger is connected into one or several chain of flip-flops, be called scan chain, using the input end of scan chain and output terminal as the test port of circuit, just can be controlled by these ports and observe the internal node of circuit.Conventional measurability trigger is the measurability trigger of MUX structure, namely adds a MUX at the input end of former trigger, so just can the data of control trigger.

In current circuit design process, circuit design completes a part wherein respectively by different departments or company often, and can relate to multiple eda tool in the process of whole circuit design, this just relates to the problem of exchanges data simultaneously.And a kind of standard format of the swapping data of EDIF Wang Biaoshi different company and different eda tool.EDIF is the english abbreviation of electronic design interchange format (Electronic Design Interchange Format), it is a kind of not by the data layout of copyright restrictions, and it proposes the schematic diagram relevant with defining circuit design, symbol and physical layout, interconnection and structural information.The circuit using EDIF net list language to describe, can carry out message exchange as the Interchange Format of standard at the design link of each circuit.

EDIF net table level circuit is the circuit using EDIF net list language to describe, in the design process of circuit, the Functional Design of circuit and design for Measurability are separated often, the circuit data that the personnel of circuit function design pass to circuit design for Measurability personnel many times describes with EDIF net table, in such net table main each element in circuit described use information and mutual between link information.Just circuit necessary information can be obtained, to carry out a kind of important way that design for Measurability becomes circuit design for Measurability to circuit by the EDIF net table of analysis circuit.

The storage format of EDIF net table is the text formatting of ASIC coding, so Perl language can be used very easily to carry out treatment and analysis to it.Perl language is a kind of senior, general, literal translation formula, dynamic, powerful language, and its most important characteristic is the function of inner integrated regular expression, and huge third party code storehouse CPAN.Wherein the function of regular expression can be our extraordinary process text, can be used for very convenient efficient process EDIF net table here.

In the flip flop design stage, need to carry out measurability amendment to the trigger used in circuit, in the circuit of reality, the usage quantity of trigger is quite huge, so be necessary that use instrument carries out the amendment of robotization to the trigger used in circuit.Here the instrument that we can use the robotization of Perl language compilation to revise completes this function, replaces the amendment manually of wasting time and energy.

In the scan chain design phase, need the connection circuit completing trigger amendment being carried out to trigger, the trigger with measurability those revised connects into one or several chain.Due to the needs of test, the design of scan chain usually needs manually to complete, and revises its connected mode at any time.Although EDIF net table is very general, being applicable to very much using software process, because EDIF net table is not conventional direct design language, as circuit designer, is not very convenient when reading and amendment.But in this stage, designer only needs to know that needs carry out the relevant information of the trigger connected.So can ensure under the prerequisite that circuit function is constant here, conventional circuit design language is used to pack carrying out trigger amended EDIF net watch circuit, there is provided the interface corresponding to EDIF to external shield internal information, to design for trigger scan chain.

In circuit design field, Verilog HDL (Verilog hardware description language) is exactly a kind of conventional design language, can as the design language of encapsulation EDIF net watch circuit, be packaged into the form of Verilog, externally provide the interface meeting Verilog grammer, for design for Measurability, personnel design further easily.The storage format of Verilog language is also text formatting, and Perl language also can be used to complete this work of encapsulation easily, simultaneously sub-scanning chain designer can complete the design effort of scan chain in Verilog environment.

Summary of the invention

The present invention is the demand in order to adapt to the automatic design for Measurability to EDIF net table level circuit, thus proposes a kind of automatic design for Measurability system of the EDIF net table level circuit based on Perl and automatic design for Measurability method.

Based on the automatic design for Measurability system of the EDIF net table level circuit of Perl, it comprises circuit source code parsing module 1, trigger modified module 2, scan chain design module 3, measurability circuit evolving module 4, testing authentication module 5;

Circuit source code parsing module 1, for the analysis described the EDIF net table level of DLC (digital logic circuit), obtains the information that in circuit, all triggers use;

Trigger modified module 2 comprises measurability trigger generation module 21 and trigger measurability modified module 22;

The trigger information of trigger modified module 2 for providing according to circuit source code parsing module, completes with EDIF language and revises the measurability of all triggers in the file that the EDIF net table of circuit describes;

Scan chain design module 3 comprises Verilog package module 31 and scan chain link block 32;

The trigger amended circuit EDIF net table that Verilog package module 31 provides for the trigger information that provides according to circuit source code parsing module and trigger modified module, completes Verilog encapsulation EDIF net table being described to circuit;

The trigger amended circuit EDIF net table that scan chain link block 32 provides for the trigger information that provides according to circuit source code parsing module and trigger modified module, completes scan chain design EDIF net table being described to circuit Verilog language completing circuit;

Measurability circuit evolving module 4 completes for the circuit of the Verilog form generated according to scan chain design module and encapsulates the Verilog again of circuit, obtains the circuit after final design for Measurability;

The circuit completing design for Measurability that testing authentication module 5 provides for the port that provides according to circuit source code parsing module and trigger information and measurability circuit evolving module, generates test file and also verifies the circuit after design for Measurability.

Measurability circuit evolving module 4 obtains the circuit after final design for Measurability to all inside circuit information of external shield, only provides the interface meeting usual hardware descriptive language form.

Based on the automatic test approach of the EDIF net table level circuit of Perl, it is realized by following steps:

The trigger used in step one, employing circuit source code parsing module 1 pair of circuit is analyzed, and uses Perl to process in EDIF environment;

The trigger used in step 2, employing trigger modified module 2 pairs of circuit carries out the amendment of measurability, and uses Perl to process in EDIF environment;

Step 3, use Perl carry out Verilog encapsulation to completing the amended EDIF circuit of trigger measurability, and shielding EDIF details, then carries out the design of scan chain to the trigger of measurability transformation in circuit;

Step 4, use Perl provide final there is measurability and meet the circuit of Verilog grammer, and checking amendment correct after, use Perl to generate the automatic test file meeting Tcl grammer, and then realize the automatic test of EDIF net table level circuit.

Adopt the trigger used in circuit source code parsing module 1 pair of circuit to analyze in step one, and the concrete grammar using Perl to carry out processing in EDIF environment is:

Steps A 1, open EDIF net table level circuit file;

Steps A 2, from EDIF net table level circuit file, analyze element all in circuit use information, and the recalls information of circuit;

The all elements of steps A 3, the circuit obtained from steps A 2 use in the file of information, and what analyze concrete instance calls situation, and is preserved into call format, preserves with document form;

Steps A 4, the file of recalls information that exports from steps A 3, find the recalls information relevant with trigger, the analysis of the trigger used in point paired circuit.

Adopt the trigger used in trigger modified module 2 pairs of circuit to carry out the amendment of measurability in step 2, and the concrete grammar using Perl to carry out processing in EDIF environment is:

In step B1, all trigger information used that analyze from step one, obtain the type triggered;

Step B2, generate a measurability EDIF component library, in this component library, include the measurability trigger that all types of triggers of analyzing in step B1 are corresponding;

Step B3, be inserted in the EDIF element of primary circuit by the measurability storehouse that step B2 obtains, the position of insertion is after the storehouse of the relevant trigger statement of primary circuit;

Step B4, according to all trigger information used analyzed in step one, generate the amendment information of trigger;

Step B5, the amendment information of generation trigger obtained according to step B4, the EDIF file of step B3 is revised one by one, what amendment triggered quotes path, and the node of the statement and test port that increase test port connects, and obtains the EDIF file that trigger has been revised.

Use Perl to carry out Verilog encapsulation to completing the amended EDIF circuit of trigger measurability in step 3, shielding EDIF details, the concrete grammar that the trigger then transformed measurability in circuit carries out the design of scan chain is:

Step C1, use Perl carry out Verilog encapsulation to completing the amended EDIF circuit of trigger measurability, the function port externally retaining primary circuit with the form of Verilog and the test port newly increased;

The connected mode of the scan chain that step C2, basis are preset connects trigger.

Use in step 4 Perl provide final there is measurability and meet the circuit of Verilog grammer, and checking amendment correct after, use Perl to generate the concrete grammar meeting the automatic test file of Tcl grammer to be:

Step D1, the encapsulation carrying out again to the Verilog file of circuit completing scan chain design generated in step 3, use Verilog to provide last circuit form, as the output file of final design for Measurability;

Step D2, information according to circuit, generate a test file, whether the connection for test scan chain is correct;

Step D3, generate a Tcl script for specific emulator, automatically the output file of design for Measurability is verified.

The present invention can adapt to the demand of the automatic design for Measurability to EDIF net table level circuit.

Accompanying drawing explanation

Fig. 1 is the principle schematic of the automatic design for Measurability system of the EDIF net table level circuit based on Perl of the present invention.

Embodiment

Embodiment one, composition graphs 1 illustrate this embodiment, based on the automatic design for Measurability system of the EDIF net table level circuit of Perl, it comprises circuit source code parsing module 1, trigger modified module 2, scan chain design module 3, measurability circuit evolving module 4, testing authentication module 5;

The difference of the automatic design for Measurability system of the EDIF net table level circuit based on Perl described in embodiment two, this embodiment and embodiment one is, measurability circuit evolving module 4 obtains the circuit after final design for Measurability to all inside circuit information of external shield, only provides the interface meeting usual hardware descriptive language form.

Embodiment three, automatic test approach based on the EDIF net table level circuit of Perl, it is realized by following steps:

Embodiment four, this embodiment are that the automatic test approach of the described EDIF net table level circuit based on Perl of embodiment three limits further, adopt the trigger used in circuit source code parsing module 1 pair of circuit to analyze in step one, and the concrete grammar using Perl to carry out processing in EDIF environment is:

Steps A 1, open EDIF net table level circuit file;

From EDIF original, analyze elements all in circuit use information, and the recalls information of circuit, comprise the name of edif, the name of library, comprises the name of all cell in library, the name of view all in cell, the name of the example instance called in view, and this instance quote path viewRef, cellRef, libraryRef, and these information are preserved into a file, for follow-up.Information stores by row with the form of " attribute (space) property value ", and form is as follows:

edif edifname

library libraryname

cellc ellname

view viewname

instance instancename viewRef viewRefname cellRef cellRefname libraryReflibraryRefname

design designname cellRef cellRefname libraryRef libraryname

For edif attribute, its value is edif;

For library attribute, its value is library;

For cell attribute, its value is cellname;

For view attribute, its value is viewname;

For instance attribute, its value is viewname; Instance attribute kit is containing viewRef attribute, and property value is viewname; Comprise cellRef attribute, property value is cellname; May comprise libraryRef attribute, its value is libraryRefname;

For design attribute, property value is designname; Design attribute kit contains cellRef attribute, property value cellRefname; Comprise libraryRef attribute, property value libraryRefname;

Edif only has one to be positioned at the first row, multiple library may be had below edif attribute, the rank of library is the first order, and the rank of multiple cell, cell may be had below library to be the second level, multiple view may be had below cell, view is the third level, and multiple instance, instance may be had below view to be the fourth stage, design only has one, is positioned at last column.

Attribute-name except edif and design occurs successively by rank, if occur out of stock, then preferentially occurs that rank is low.

The all elements of steps A 3, the circuit obtained from steps A 2 use in the file of information, and what analyze concrete instance calls situation, and is preserved into call format, and preserve with document form, its form is as follows:

{lib.cell.view}{inLib.inCell.inView}[instName1 instName2 instName3…]

The view of the cell in lib storehouse, being used in the inView of the inCell of inLib, is instName1, instName2, instName3 etc. by the title used.

Embodiment five, this embodiment are that the automatic test approach of the described EDIF net table level circuit based on Perl of embodiment three limits further, adopt trigger modified module (2) trigger used in circuit to be carried out to the amendment of measurability in step 2, and the concrete grammar using Perl to carry out processing in EDIF environment is:

Step B4, according to all trigger information used analyzed in step one, generate the amendment information of trigger, the form of amendment information is as follows:

{cell}{cellchanges}[portchanges]

Trigger cell quote that path needs to be modified as cellchanges quote path, need the test port added in portchanges.

Embodiment six, this embodiment are that the automatic test approach of the described EDIF net table level circuit based on Perl of embodiment three limits further, Perl is used to carry out Verilog encapsulation to completing the amended EDIF circuit of trigger measurability in step 3, shielding EDIF details, the concrete grammar that the trigger then transformed measurability in circuit carries out the design of scan chain is:

Embodiment seven, this embodiment are that the automatic test approach of the described EDIF net table level circuit based on Perl of embodiment three limits further, use in step 4 Perl provide final there is measurability and meet the circuit of Verilog grammer, and after checking amendment correctly, the concrete grammar using Perl generation to meet the automatic test file of Tcl grammer is:

Embodiment seven, the following automatic test approach that the EDIF net table level circuit based on Perl of the present invention is described with design parameter:

The example of an EDIF net table level circuit as follows, the not function of what reality:

Wherein: this EDIF net table of A1 has three library, LIB1, LIB2, LIB3, devises a design A1 with these three storehouses.Containing a cell in LIB1, name is containing a view in CELL1, CELL1, PRIM by name.Cell containing a FD by name in LIB2, FD has the view of a PRIM by name, and this FD is a kind of trigger.Cell containing a CELL2 by name in LIB3, this cell has the view of a netlist by name, this cell contains two instance, and one of them is quoting the PRIM view of the CELL1 in LIB1, and another is calling the PRIM view of the FD in LIB2.It is more than the explanation of the circuit component used to this example and structure.

Now design for Measurability is carried out to this circuit:

{cell}{cellchanges}[portchanges]

Step (1): use the EDIF net table of Perl to this circuit to carry out the use of element and the analysis of structure.

Step1: read in this EDIF file

Step2: the regular expression that use Perl provides is by line retrieval, extract the information needed, first we can extract the name A1 of edif net table, then can extract the LIB1 of library, and this view of CELL1 and PRIM of LIB1, by that analogy, when the information extracting instance, such as, for INST1, what can obtain it quotes path, the value LIB1 of the value CELL1 of the value PRIM of viewRef, cellRef, libraryRef.If libraryRef is default, represent it is same library.

To the information of following description circuit component and structure be obtained:

edif A1

library LIB1

cell CELL1

view PRIM

library LIB2

cell FD

view PRIM

library LIB3

cell CELL2

viewnetlist

instance INST1 viewRef PRIM cellRef CELL1 libraryRef LIB1

instance INST2 viewRef PRIM cellRef FD libraryRef LIB2

design A1 cellRef CELL2 libraryRef LIB3

Step3: analyze the information obtained in the first step, obtains recalls information each other, as follows

{LIB1.CELL1.PRIM}{LIB3.CELL2.netlist}[INST1]

{LIB2.FD.PRIM}{LIB3.CELL2.netlist}[INST2]

Step4: the recalls information finding trigger FD in this example

{LIB2.FD.PRIM}{LIB3.CELL2.netlist}[INST2]

Step (2):

Step1: obtain the type obtaining triggering all trigger information used from step (1);

Step2: generate a measurability EDIF component library, includes the measurability trigger that all types of triggers of analyzing in Step1 are corresponding in this storehouse;

Here for the trigger of FD type, use edif to realize the measurability trigger of a MUX structure, called after FD_T, the port-for-port S had more and port T, and be put in self-designed measurability storehouse as a cell, such as storehouse DFTFF.

Step3: be inserted in the EDIF element of primary circuit by the measurability storehouse of Step2, the position of insertion is after the storehouse of the relevant trigger statement of primary circuit

Here that measurability storehouse designed above is put into after LIB2 that section of code, and before LIB3 is expert at.

Step4: obtain all trigger information used according to the step (1) in claim 2, generate the amendment information of trigger, amendment information is here:

{LIB3.FD.PRIM}{DFTFF.FD_T.netlist}[S_INST2.INST2T_INST2.INST2 Q_INST2.INST2]

Step5: according to the amendment information of Step4, revises one by one to the EDIF file of Step3, and what amendment triggered quotes path, and the node of the statement and test port that increase test port connects, and obtains the EDIF file that trigger has been revised.

Step (3): use Perl to carry out Verilog encapsulation to completing the amended EDIF circuit of trigger measurability after step (2) completes, shielding EDIF details, then the trigger of measurability transformation in circuit is carried out to the design of scan chain, use Perl Computer Aided Design personnel to complete in Verilog environment, algorithm is as follows:

Step1: Verilog encapsulation is carried out to the EDIF that the step (2) in claim 2 generates, the function port externally retaining primary circuit with the form of Verilog and the test port newly increased;

Step2: designer provides the connected mode of scan chain;

Step3: the scan chain connected mode provided according to designer connects trigger;

Step (4): generate final measurability circuit file, use Perl provide final there is measurability and meet the circuit of Verilog grammer, and whether checking amendment result is correct, use Perl to generate the automatic test file meeting Tcl grammer, algorithm is as follows:

Step1: the Verilog file of circuit completing scan chain design generated the step (3) in claim 2 carries out encapsulation again, Verilog is used to provide last circuit form, as the output file of final design for Measurability.

Step2: according to the information of circuit, generate a test file, whether the connection for test scan chain is correct.

Step3: generate a Tcl script for specific emulator, automatically the Output rusults of design for Measurability is verified.

Feature of the present invention:

1, to the form calling algorithm used and storage data when level is analyzed using circuit described by EDIF net table;

2, to the data layout using the analytical algorithm of trigger and the data layout of storage and the storage used in circuit described by EDIF net table, the design of measurability storehouse (library) and the insertion of library, the different design for Measurability structure triggered;

3, in analysis circuit, trigger is called and the algorithm of the situation of instantiation and storage format by disparate modules;

4, to all algorithms being carried out measurability amendment by the trigger used in circuit described by EDIF net table;

5, use Verilog language to encapsulate circuit described by amended EDIF net table, become the circuit that meets Verilog statement;

6, design according to the scan chain of Verilog grammer to circuit in Verilog environment;

7, the test file that amended circuit is tested automatically is generated;

8, the generation of the automatic test file of the circuit of Tcl form, automatically adds test vector and obtains corresponding test response.

Claims

1. based on the automatic design for Measurability method of the automatic design for Measurability system of the EDIF net table level circuit of Perl, it realizes based on the automatic design for Measurability system of the EDIF net table level circuit of Perl, and this system comprises circuit source code parsing module (1), trigger modified module (2), scan chain design module (3), measurability circuit evolving module (4), testing authentication module (5);

Circuit source code parsing module (1), for the analysis described the EDIF net table level of DLC (digital logic circuit), obtains the information that in circuit, all triggers use;

Trigger modified module (2) comprises measurability trigger generation module (21) and trigger measurability modified module (22);

The trigger information of trigger modified module (2) for providing according to circuit source code parsing module, completes with EDIF language and revises the measurability of all triggers in the file that the EDIF net table of circuit describes;

Scan chain design module (3) comprises Verilog package module (31) and scan chain link block (32);

The trigger amended circuit EDIF net table that Verilog package module (31) provides for the trigger information that provides according to circuit source code parsing module and trigger modified module, completes Verilog encapsulation EDIF net table being described to circuit;

The trigger amended circuit EDIF net table that scan chain link block (32) provides for the trigger information that provides according to circuit source code parsing module and trigger modified module, completes scan chain design EDIF net table being described to circuit Verilog language completing circuit;

Measurability circuit evolving module (4) completes for the circuit of the Verilog form generated according to scan chain design module and encapsulates the Verilog again of circuit, obtains the circuit after final design for Measurability;

The circuit completing design for Measurability that testing authentication module (5) provides for the port that provides according to circuit source code parsing module and trigger information and measurability circuit evolving module, generates test file and also verifies the circuit after design for Measurability;

Based on the automatic design for Measurability method of the automatic design for Measurability system of the EDIF net table level circuit of Perl, it is realized by following steps:

Step one, employing circuit source code parsing module (1) are analyzed the trigger used in circuit, and are used Perl to process in EDIF environment;

Step 2, employing trigger modified module (2) carry out the amendment of measurability to the trigger used in circuit, and use Perl to process in EDIF environment;

Step 4, use Perl provide final there is measurability and meet the circuit of Verilog grammer, and checking amendment correct after, use Perl to generate the automatic test file meeting Tcl grammer, and then realize the automatic test of EDIF net table level circuit;

It is characterized in that: adopt trigger modified module (2) trigger used in circuit to be carried out to the amendment of measurability in step 2, and the concrete grammar using Perl to carry out processing in EDIF environment is:

2. the EDIF based on Perl according to claim 1 nets the automatic design for Measurability method of the automatic design for Measurability system of table level circuit, it is characterized in that in the automatic design for Measurability system based on the EDIF net table level circuit of Perl, measurability circuit evolving module (4) obtains the circuit after final design for Measurability to all inside circuit information of external shield, only provides the interface meeting usual hardware descriptive language form.

3. the EDIF based on Perl according to claim 1 nets the automatic design for Measurability method of the automatic design for Measurability system of table level circuit, it is characterized in that in step one, adopting circuit source code parsing module (1) to analyze the trigger used in circuit, and the concrete grammar using Perl to carry out processing in EDIF environment is:

Steps A 1, open EDIF net table level circuit file;

4. the EDIF based on Perl according to claim 1 nets the automatic design for Measurability method of the automatic design for Measurability system of table level circuit, it is characterized in that in step 3, using Perl to carry out Verilog encapsulation to completing the amended EDIF circuit of trigger measurability, shielding EDIF details, the concrete grammar that the trigger then transformed measurability in circuit carries out the design of scan chain is: