CN104797012A - Communication system - Google Patents

Abstract

The invention discloses a communication system. The communication system comprises a first slave processor which comprises a first data port used for exchanging data with a main processor, a first clock input end used for receiving main clock signals from the main processor, a first synchronization input end used for receiving synchronization signals from the main processor, a first configurable delayer used for synchronizing the clock of the first slave processor with the main processor and synchronizing responses, to the main clock signals and the synchronization signals, of the clock of the first slave process, a first frequency shifter used for setting the frequency of the first slave processor, a first radio frequency receiver used for receiving radio frequency data from the main processor, a first combiner used for combining radio frequency data of the first slave processor and the radio frequency data from the main processor so as to generate combined radio frequency data, and a first radio frequency transmitter used for operating the radio frequency data, used for transmitting combinations, of the first radio frequency transmitter at the frequency of the first slave processor.

Description

Communication system

Technical field

The application relates in general to cellular base stations, and more specifically, relates to concatenation type (cascading) baseband processor.

Background technology

There is a large amount of cellular base stations, they use identical wireless access technology (RAT), the access of the code division multiple access of such as 3G, time division synchronous access (TD-SCDMA), high-speed packet (HSPA), two carrier wave HSPA(DC-HSPA), LTE etc.These base stations can have different capacity, to hold the concurrent user of varying number, different bandwidth (BW), transmitting (TX) antenna of varying number, reception (RX) antenna etc. of varying number.Along with cellular technologies becomes more general, cellular operator is planned and is disposed the network with wider base station range, and these base stations have different sizes and capacity.

Summary of the invention

Embodiment there is provided a kind of communication system according to the application's one, this communication system comprises: the first slave processor, comprising: the first FPDP, for primary processor swap data; First input end of clock, for receiving the master clock signal of host processor; First synchronous input end, for receiving the synchronizing signal of host processor; First configurable delayer, for making the first slave processor clock synchronous with primary processor, the first slave processor clock in response to master clock signal and synchronizing signal by synchronously; First frequency shifter, for setting the first slave processor frequency; First radio frequency receiver, for receiving the rf data of host processor; First combiner, for combining the rf data of the first slave processor and carrying out the rf data of host processor, to generate the rf data of combination; And first radiofrequency launcher, operate under the first slave processor frequency, the first radiofrequency launcher is for launching the rf data of combination.

In addition, according to this execution mode, this communication system also comprises: primary processor, and primary processor comprises: the first primary data port, for the first slave processor swap data; Master clock input, for receiving the clock signal from external clock reference; Master clock output, for transmitting master clock signal; Main synchronous output end, for synchronous signal transmission; Main frequency shifter, for setting primary processor frequency; Main radiofrequency launcher, operates under primary processor frequency, and main radiofrequency launcher is for launching the rf data of host processor.

In addition, according to this execution mode, the first slave processor frequency is identical with primary processor frequency.

In addition, according to this execution mode, this system also comprises: the second slave processor, and the second slave processor comprises: the second FPDP, for primary processor swap data; Second clock input, for receiving master clock signal; Second synchronous input end, for synchronous signal transmission; Second configurable delayer, for making the second slave processor clock synchronous with primary processor, the second slave processor clock in response to master clock signal and synchronizing signal by synchronously; Second frequency shifter, for setting the second slave processor frequency, the second slave processor frequency is identical with primary processor frequency; Second radio frequency receiver, for receiving the rf data of combination; Second combiner, for the rf data of the rf data and combination that combine the second slave processor, to generate the rf data of combination further; And second radiofrequency launcher, operate under the second slave processor frequency, the second radiofrequency launcher is for launching the rf data of combination further; And the second primary data port on the host processor, the second primary data port and the second slave processor swap data.

In addition, according to this execution mode, primary processor frequency is different from the first slave processor frequency.

In addition, according to this execution mode, the first slave processor comprises the second radiofrequency launcher for launching the first slave processor rf data further; And primary processor comprises further: main radio frequency receiver, for receiving the first slave processor rf data; Main combiner, for combining rf data and the first slave processor rf data of primary processor, to generate the rf data of main combination; And the second main radiofrequency launcher, operate under primary processor frequency, the second main radiofrequency launcher is for launching the rf data of main combination.

In addition, according to this execution mode, the first slave processor comprises further: the second radio frequency receiver, for receiving the rf data of host processor; Second combiner, for combining the rf data of the first slave processor and carrying out the rf data of host processor, to generate the rf data of the second combination; And second radiofrequency launcher, for launching the rf data of the second combination.

In addition, according to this execution mode, primary processor comprises further: main radiofrequency launcher, and for future, the rf data rf data of host processor is emitted to the second radio frequency receiver of the first slave processor.

According to another execution mode of the application, additionally provide a kind of method, comprise the following steps: make the clock of the second processor and the clock synchronous of first processor; The frequency of the second processor is become the frequency of first processor; Combination is from the data of first processor and the data from the second processor; And launch the data of combination.

In addition, the method is further comprising the steps of: make the clock of the 3rd processor and the clock synchronous of first processor; The frequency of the 3rd processor is become the frequency of first processor; The data of further combination from the 3rd processor and the data of combination; And launch the data of combination further.

In addition, according to this another execution mode, combine in the second processor from the data of first processor and the data from the second processor.

According to the another execution mode of the application, additionally provide a kind of system, comprise: first processor, for operating under predetermined frequency band, first processor comprises the first input end of clock for receiving external timing signal, first processor operates with a clock speed in response to receiving external timing signal further, first processor comprises the first reflector for launching the first data group, first processor comprises the first output terminal of clock for clock signal further, first processor comprises the first synchronous output end for exporting synchronizing signal further, and second processor, for operating under predetermined frequency band, second processor comprises the second clock input for receiving the clock signal from the first output terminal of clock, second processor comprises the second processor synchronous input end for receiving the synchronizing signal from the first synchronous output end further, second processor is in response to receiving clock signal and synchronizing signal synchronously operates further with clock speed, second processor comprises the second processor receiver for receiving the first data group, second processor comprises further for combining the second data group and the first data group to generate the second processor combiner of the data group of combination.

In addition, according to this another execution mode, the second processor comprises the configurable delayer of the second processor of the propagation delay for compensating first processor further.

In addition, according to this another execution mode, this system also comprises: the second reflector on the second processor, and the second reflector is for launching the data group of combination, and the 3rd processor, for operating under predetermined frequency band, 3rd processor comprises the 3rd input end of clock for receive clock signal, 3rd processor comprises the 3rd processor synchronous input end for receiving synchronizing signal further, 3rd processor is in response to receiving clock signal and synchronizing signal synchronously operates further with predetermined clock speed, 3rd processor comprises the 3rd processor receiver of the data group for receiving combination, 3rd processor comprises the 3rd processor combiner further, for combining the data group of the 3rd data group and combination, to generate the data group of combination further.

In addition, according to this another execution mode, this system also comprises the 3rd reflector on the 3rd processor, and the 3rd reflector is for launching further data splitting group.

In addition, according to this another execution mode, the 3rd processor comprises the configurable delayer of the 3rd processor of the propagation delay for compensating the second processor further, and the configurable delayer of the 3rd processor compensates the propagation delay of first processor further.

Accompanying drawing explanation

The many aspects of the application can be understood better with reference to accompanying drawing.Assembly in accompanying drawing is not necessarily to scale, and the principle focusing on clearly illustrating the application emphasized.In addition, in the accompanying drawings, identical reference number represents the corresponding component in all several figure.

Fig. 1 shows the diagram of an execution mode of the baseband processor comprising transmission modem block (transmit modem block).

Fig. 2 shows the diagram of an execution mode of the transmission modem block of Fig. 1.

The diagram of an execution mode of the system that three processors that Fig. 3 shows Fig. 1 are serially connected.

The diagram of an execution mode of the system that two processors that Fig. 4 shows Fig. 1 are serially connected.

Fig. 5 shows the diagram of an execution mode of the system of the processor using Fig. 1.

The diagram of another execution mode of the system that two processors that Fig. 6 shows Fig. 1 are serially connected.

Fig. 7 shows the diagram of another execution mode of the baseband processor comprising different transmission modem block.

Fig. 8 shows the diagram of an execution mode of the transmission modem block of Fig. 7.

The diagram of an execution mode of the system that two processors that Fig. 9 shows Fig. 7 are serially connected.

Embodiment

Use identical wireless access technology (RAT(such as, 3G, TD-SCDMA, HSPA, DC-HSPA, LTE etc.) cellular base stations can have different capacity, with hold the concurrent user of varying number, different bandwidth (BW), varying number transmitting (TX) and/or receive (RX) antenna etc.So, designing different systems for each possible configuration is numerous and diverse and the task of Expenses Cost.

In the system and method illustrated herein, processor is serially connected in together to provide different configurations.These different configurations cause that the capacity of base station is higher, the quantity of concurrent user on a frequency band increases and/or some carrier aggregations, are still only suitable for radio frequency (RF) chipset simultaneously.Some of these execution modes will create some RAT(such as DC-HSPA, Rel-9HSPA, HSPA++, LTE-Advanced) advantageous feature.

In brief, processor is consistent over time and frequency, and each processor all has the FPDP of carrying out exchanges data with other processors.Alignment of data (data alignment) and exchange can make processor be used as individual unit in the mode of assembling.The series connected ability of honeycomb fashion baseband processor makes the scalable architecture holding different system configuration.

Given this, the existing execution mode that will describe in detail as shown in accompanying drawing.The appended drawings illustrate some execution modes although combine, the application be not limited to an execution mode herein or some execution modes by its purport.On the contrary, its intention covers all replacements, amendment and equivalent.

Fig. 1 shows the diagram of an execution mode of the processor 105 comprising transmission modem block 10.In a preferred embodiment, this processor 105 is Celivero(or BCM61680) chip.

As shown in Fig. 1, processor 105 comprises three radio frequencies (RF) receiver (RX) (it can be analog or digital IQ), 120,130,140 and two reflectors (TX) 125,135.RF RX1120, RF RX2130 and RF RX3140 provide air interface for RF data receiver.Similarly, RF TX1125 and RF TX2 provides air interface for RF transfer of data.

About some execution mode, processor 105 also comprises synchronously (SYNC) input (IN) 150, SYNC output (OUT) 155, clock (CLK) IN160, CLK OUT165.This CYNC IN150 is configured to reception SYNC signal (or some signals), and it allows processor 105 that its internal clocking is synchronous with the source of SYNC signal, and SYNC OUT155 is configured to transmission SYNC signal to other processors.Similarly, CLK IN160 is configured to receive CLK signal from external source or from other processors 105, thus allows processor 105 according to its internal clocking of CLK signal sets.This CLK OUT165 is configured to transmission CLK signal to other processors 105, makes other processors can make their respective clocks and CLK signal synchronously or consistent.

In the execution mode of Fig. 1, processor 105 also comprises three data port ones 70,180,190, and it is shown as medium and has nothing to do port (MII) port.These MII1170, MII2180 and MII3190 are preferably implemented as gigabit medium access control (GMAC) port.

The processor 105 of Fig. 1 also comprises the transmission modem block 110 illustrated in greater detail with reference to figure 2.Particularly, Fig. 2 shows an execution mode with two pseudo noises (PN) module (PNM1250 and PNM2260) generating PN code for modem data.

As shown in the execution mode of Fig. 2, transmission modem block 110 comprises first in first out (FIFO) register array 202, and it exports one group of fagging (a bank of spreader) 206 to.In the execution mode of Fig. 2, there are 88 faggings, comprise two Primary Common Pilot instruction passage (P-CPICH), two secondary CPICH(S-CPICH), two Primary Common Control Physical passages (P-CCPC), two secondary CCPC(S-CCPC), two synchronizing channels (P-SCH), two secondary SCH(S-SCH), 32 dedicated physical channel (DPCH), catch instruction passage (AICH) for two, two paging indication channels (PICH), six Compliance control passages (SCCH), 30 high-speed slender body theory (HSDPA), two absolute grant passages (AGCH), and two relative authorization passages (RGCH).

Fagging 206 provides and inputs to two combiner selectors (first combiner selector 216 and the second combiner selector 266), and they are each all has 88 inputs corresponding to 88 faggings 206 and 88 outputs.Fagging 206 also provides and inputs to HSDPA multiple-input and multiple-output (MIMO) combiner 210, and it provides again and inputs to the first combiner selector 216 and the second combiner selector 266.

The output of the first combiner selector 216 is operatively coupled to the input providing the first passage combiner antenna 220 inputing to the first forming filter 224.

Data from the first forming filter 224 are provided to the first configurable delayer 228(and are also known as programmable delay).This first configurable delayer 228 can make transmission modem clock 110 compensating delay, and this delay is owing to showing himself by the data dissemination of other processors or Clock Distribution error.This first configurable delayer 228 can allow processor 105 to make base at that time synchronous with the time base of other processors.

This first configurable delayer 228 is operatively coupled to the first frequency shifter (first frequency shifter)

232, it allows transmission modem block 110 to set operating frequency.About some execution mode, the first frequency shifter 232 allows processor 105 to move to another operating frequency from an operating frequency.First configurable delayer 228 and the first frequency shifter 232 provide a mechanism with the form of combination, by this mechanism, processor 105 can make base and its frequency band and other processors at that time time base and frequency band synchronous.

Data 234 from the first frequency shifter 232 are transmitted to combiner 238 and multiplexer (MUX) 246.Combiner 238 is operatively coupled to RF RX1120, thus allows transmission modem block 110 closes himself data 236 and introduces RF data at RF RX1120 group place, to generate data splitting 240.Then, data splitting 240 is input to orthorhombic phase module (quadrature phase module) 242, and is provided to the data splitting 244 of multiplexing orthorhombic phase modulation and the MUX 246 of frequency-shift data 234 subsequently.Then multiplex data are launched by RF TX1 125.Path between first combiner selector 216 and RF TX1 125 is called as first data transmission path here.

Second data transfer path comprises the second combiner selector 266.Data from the second combiner selector 266 are input to the second channel combiner antenna 270 providing input 272 to the second forming filter 274 subsequently.Similar to first data transmission path, the second data transfer path comprises the second configurable delayer 278, and it is operatively coupled to the second frequency shifter 282.This second configurable delayer 278 allows processor 105 to make base at that time synchronous with the time base of other processors again, and the second frequency shifter 282 allows transmission modem block 110 to set its operating frequency and, if necessary, another operating frequency is moved to from an operating frequency.Second configurable delayer 278 and the second frequency shifter 282 provide a kind of mechanism with the form of combination, by this mechanism, processor 105 can make base and its frequency band and other processors at that time time base and frequency band synchronous.Then data from the second frequency shifter 282 are launched by RF TX2135.Frequency shifter 232,282 can realize multi-band and/or multiple radio frequency combing further.

As shown in the transmission modem block of Fig. 2, configurable delayer 228,278, frequency shifter 232,282 and combiner 238 can allow processor 105 accurately to assemble the modem data of himself and the introducing data from other processors, and with other processor simultaneous operation.

An execution mode of the system that three processors 105a, 105b, 105c that Fig. 3 shows Fig. 1 are serially connected.As shown in Fig. 1, a controller 105a is used as primary processor 105a, and other two processors 105b, 105c are used as the first slave processor 105b and the second slave processor 105c.

The CLK IN 160a of primary processor 105a is operatively coupled to outside CLK source, and this outside CLK source is shown as the temperature-controlled crystal oscillator (TCXO) 305 in the embodiment of Fig. 3.This TCXO 305 preferably in 19.2 megahertzes (MHz) or 26MHz work, and provides clock signal to primary processor 105a.The MII1 170a of primary processor 105a is operatively coupled to network (being internet 325 shown in Fig. 3), thus allows backhaul data (backhaul data) biography to pass through MII1170a.

The SYNC OUT155a of primary processor 105a is operatively coupled to the SYNC IN150b of the first slave processor 105b and the SYNC IN 150c of the second slave processor 105c.In addition, the CLK OUT 165a of primary processor 105a is operatively coupled to the CLK IN 160b of the first slave processor 105b and the CLK IN 160c of the second slave processor 105c.Carrying out the SNYC OUT 155a of host processor 105a and CLK OUT 165a allows slave processor 105b, 105c to make their respective time bases synchronous with the time base of primary processor 105a.This can make all three processors 105a, 105b, 105c (such as, chip phase, groove, frame, Hyperframe etc.) synchronous working in all standards, thus is used as individual unit.

Referring back to Fig. 2, each processor 105a, 105b, 105c comprise configurable delayer 228,278(Fig. 2), this can allow to transmit modem block 110 makes the time base of its respective processor synchronous.Consider in Fig. 3 and three processors 105a, 105b, 105c have been shown, to programme primary processor 105a with zero propagation, with N time delay programme the first slave processor 105b(this will be applicable to compensate by all propagation delays of primary processor 105a), and with the time delay of 2N programme the second slave processor 105c(this will be applicable to compensate all propagation delays by primary processor 105a and the first slave processor 105b).

The MII2 180a of primary processor 105a is operatively coupled to the MII1 170b of the first slave processor 105b, and permission primary processor 105a is carried out exchanges data by FPDP 180a, 170b and the first slave processor 105b by this.Similarly, the MII3 190a of primary processor 105a is operatively coupled to the MII1 170c of the second slave processor 105c, thus allows primary processor 105a and the second slave processor 105c to carry out exchanges data.

RF RX2 130a is operatively coupled to RF integrated circuit (IC) path (RF IC PATH1) 385, and RFRX3140a is operatively coupled to the 2nd RF IC path (RF IC PATH1) 395, this pair of RX antenna structure achieves the diversity of RX.

The RF TX1 125a of primary processor 105a is operatively coupled to the RF RX1120b of the first slave processor 105b, thus primary processor 105a can provide its RF data to the first slave processor 105b.

Referring back to Fig. 2, RF RX1 120b by combiner 238(Fig. 2) be operatively coupled to RF TX1120b, thus allow the first slave processor 105b combine himself modem data and the RF data of introducing carrying out host processor 105a.So, transmission modem block 110 processes each side of RAT physical layer 1, and each side of processor subsystem (such as, such as, MIPS74K processor core) processing protocol stack (such as, such as, RAT software layer) above.

Similar to primary processor 105a, the RF RX2 130b of the first slave processor 105b is operatively coupled to RF integrated circuit (IC) path 385, and the RF RX3 140b of the first slave processor 105b is operatively coupled to the 2nd RFIC path 395.

The RF TX1 125b of the first slave processor 105b is operatively coupled to the RFRX1 120c of the second slave processor 105c.Similar to the first slave processor 105b, combiner 238(Fig. 2 of the second slave processor 105c) allow the second slave processor 105c to combine himself modem data and the introducing RF data from the first slave processor 105b.Consider that the first slave processor 105b has assembled himself modem data and carried out the modem data of host processor 105a, the data of assembling in the second slave processor 105c comprise all data from primary processor 105a, the first slave processor 105b, the second slave processor 105c.Moreover the transmission modem block 110 of the second slave processor 105c processes each side of RAT physical layer 1, and each side of processor subsystem processing protocol stack.

The RF TX1 125c of the second slave processor 105c is operatively coupled to a RF IC path 385, and the RF TX2 135c of the second slave processor 105c is operatively coupled to the 2nd RF IC path 395.And, similar with the first slave processor 105b to primary processor 105a, the RF RX2 130c of the second slave processor 105c is operatively coupled to RF integrated circuit (IC) path 385, and the RF RX4 140c of the second slave processor 105c is operatively coupled to the 2nd RF IC path 395.

When 32 3G/HSPA++ users all supported by each processor 105, the serial connection architecture (as shown in the execution mode of Fig. 3) of three processors 105a, 105b, 105c can allow base station to use two TX antennas and RX antenna, and only use a RF chipset, support use 96 3G/HSPA++ users.In brief, the first slave processor 105b and the second slave processor 105c only as modulator-demodulator, and does not perform upper strata RAT protocol stack function.Alternatively, primary processor 105c is all 96 user's processing protocol stacks (upper RAT layers).As skilled in the art can be understood, by making the operating frequency of the internal clocking of processor 105a, 105b, 105c and all processor 105a, 105b, 105c synchronous, seamless serial connection architecture can be created, thus increase potential concurrent user's sum.

An execution mode of the system that two processors 105d, 105e that Fig. 4 shows Fig. 1 are serially connected.Particularly, the execution mode of Fig. 4 shows and uses the two carrier operation of single RF chipset in single antenna.

As shown in Fig. 4, first processor 105d receives its CLK IN 106d from TCXO 305, and backhaul data is transmitted to network (such as, the Internet 325) by its MII1 170d by execution.The MII2 180d of first processor 105d is operatively coupled to the MII1 170e of the second processor 105e, thus allows the exchanges data between first processor 105d and the second processor 105e.

The SYNC OUT 155d of first processor 105e is operatively coupled to the SYNC IN 150e of the second processor, and the CLK OUT 165d of first processor 105d is operatively coupled to the CLK IN 160e of the second processor 105e, thus two processors 105d, 105e are allowed to make its respective CLK phase mutually synchronization.About this embodiment, the frequency shifter 232 of first processor 105d, 282(Fig. 2) for Tape movement (band-shifting), and the frequency shifter 232 of the second processor 105e, 282(Fig. 2) for making two bands be concentrated to RF.

So far, first processor 105d has the ability of process 32 designated lane (DCH) users and 15 HSDPA, and the second processor 105e similarly has the ability of process 32 DCH users and 15 HSDPA, processor 105d, 105e of combination can only use a RF chipset fully to support 64 users now on an antenna.

Fig. 5 shows the diagram of an execution mode of the system of the processor 105f using Fig. 1.In the execution mode of Fig. 5, second frequency shifter 282(Fig. 2 relevant to RF TX2 135f) for changing RF TX2 135f, thus produce two carrier effect.Therefore, the combination of RF TX1125f and RF TX2 135f allows processor 105f on single RF interface (IF) and RF IC 515, serve two carrier wave base station.

For this execution mode, CLK IN 160f is again from TCXO 305 receive clock signal, and MII1 170f is used as the FPDP that backhaul data is propagated.Different from the execution mode of Fig. 3 and Fig. 4, the execution mode of Fig. 5 shows the RF TX2 135f of the frequency shifts being operatively coupled to RF RX1 120f.Consider that RF RX1 120f combines (Fig. 2) with RF TX1 125f by combiner 238, the RF TX1 125f caused thus is two carrier RF signal now.These pair of carrier RF signal can be used for two carrier wave 3G and operates or two carrier wave time domain space code division multiple access access (TD-SCDMA) operation.

The diagram of another execution mode of the system that two processors 105g, 105h that Fig. 6 shows Fig. 1 are serially connected.Configure different from two processors of Fig. 4, two processor execution modes of Fig. 6 show two processor 105g, 105h intersection serial connection (or cross-coupled).

In the execution mode of Fig. 6, the MII1 170g of first processor 105g is operatively coupled to network (such as, the Internet 325), propagates to process backhaul data.Further, first processor 105g receives CLK IN 160g from TCXO 305, and provides SYNC OUT 155g and CLK OUT 165, thus controls the synchronous of serial connection architecture.

The MII2 180g of first processor 105g is operatively coupled to the MII1 170h of the second processor 105h, thus allows processor 105g, 105h by they respective FPDP 180g, 170h swap datas.

In the intersection serial connection execution mode of Fig. 6, the RF TX2 135g of first processor 105g is operatively coupled to the RF RX1 120h of the second processor 105h.On the contrary, the RF TX2 135h of the second processor is operatively coupled to the RF TX1 120g of first processor 105h.Allow data to be combined by the RF RX1 120g in first processor 105g referring back to Fig. 2, RF TX1 125g, and RF TX1 125h allow data to be combined by RF RX1 120h in the second processor 105h.Thus, be connected in series by the intersection of two processors 105g, 105h, when being represented as two carrier wave RF2 695 during RF TX1 125g is by a two carrier wave RF(Fig. 6) transmission and RF TX1 125h by another couple of carrier wave RF(Fig. 6 in be assigned as two carrier wave RF1685) when transmitting, the architecture of Fig. 6 realizes complete carrier operation by MIMO.

As instantiation, if the RF TX2 135g of first processor 105g moves+5MHz(, this is the bandwidth of 3G carrier wave) and the RF TX2 135h of the second processor 105h moves-5MHz, then the RF TX1125g of first processor 105g corresponds to the 10MHz of a MIMO branch by launching and the RF TX1 125h of the second processor 105h will launch the 10MHz corresponding to another MIMO branch.Thus the seamless intersection of two processors 105g, 105h serial connection allows MIMO and DC-HSPA to operate simultaneously, thus 84 MBPSs (Mbps) be provided on 10MHz and only use two strand RF transceivers.

Fig. 7 shows the diagram of another execution mode of the processor 705 comprising different transmission modem block 710.Different from the processor 105 of Fig. 1, the processor 705 of Fig. 7 comprise operatively be coupled to RF RX2 730(and RFTX1 125 how to be coupled to RF RX1 120 similar) RF TX2 735, thus allow RF TX1 125 and the modem data of RF TX2 735 combining processor self and the modem data of introducing.Owing to describing RFRX3 140, SYNC IN 150, SYNC OUT 155, CLK IN 160, CLK OUT 165, MII1 170, MII2 180 and MII3 190 with reference to figure 1, the explanation of these assemblies will be omitted with reference to figure 7.

Fig. 8 shows the diagram of an execution mode of the transmission modem block 710 of Fig. 7.Different from the transmission modem block 110 of Fig. 2, the transmission modem block 710 of Fig. 8 allows processor 705 to combine the modem data of himself and the RF data of introducing by RF RX2 730.So, this transmission modem block 710 except the every other assembly with reference to figure 2 explanation (such as, FIFO 202, fagging 206, combiner selector 216,266, HSDPA MIMO, combiner 210, channel combining unit antenna 220,270, forming filter 224,272, configurable delayer 228,278, frequency shifter 232,282 etc.) beyond, also comprise the second combiner 738, second orthorhombic phase module 742, the 2nd MUX 746.

Similar to first data transmission path, from data dissemination to the second combiner 738 and the 2nd MUX 746 of the second frequency shifter 282.This second combiner 738 is operatively coupled to RF RX2 730, thus allows transmission modem block 710 in himself data 736 of RF RX2 730 place combination and the RF data introduced, to generate data splitting 740.Then this data splitting 740 is input to the second orthorhombic phase module 242, and the MUX 246 of the data splitting 744 be provided to subsequently for the modulation of multiplexing orthorhombic phase and frequency shift data 284.Then these multiplex data are transmitted by RF TX2 735.

As shown in Fig. 8, RF TX1 125 and RF TX2 735 allows the RF data of assembling processor self modem data and the introducing from other processors now.As shown in Fig. 9, the processor architecture of these types allows two multicarrier MIMO operations.As shown in Fig. 9, an execution mode of two-processor system illustrates that primary processor 705a receives CLK IN 160a from outside TCXO 305, and make its MII1 170a operatively be coupled to network (such as, the Internet 325), to allow to be propagated by the backhaul data of MII1 170a.The MII2 180a of this primary processor 705a is operatively coupled to the MII1 170b of slave processor 705b, thus allows on these FPDP 180a, 170b, to carry out exchanges data, as HSDPA data and/or DCH data.

Primary processor 705a provides SYNC IN 150 and CLK IN 160b for slave processor 705b, thus allows slave processor 705b to make its timing synchronous with primary processor 705a.

The RF TX1 125 of primary processor 705a is operatively coupled to the RFRX1 130b of slave processor 705b, and the RF TX2 735a of primary processor 705a is operatively coupled to the RF RX2 730b of slave processor 705b.Because slave processor 705b has combiner 238,738(Fig. 8 for RF TX1 125a and RF TX2 735a now), slave processor 705b can combine himself modem data now on two RF reflectors 125b, 735b.The RF interface 985,995 that then this data splitting is separated by two transmits.

As shown in Fig. 1 to Fig. 9, allow the ability of high power capacity base station for concatenation processor provides, be increased in the quantity of concurrent user on a frequency band and/or assemble some Carriers only to use radio frequency (RF) chipset simultaneously.The serial connection architecture of these types for some RAT of such as DC-HSPA, Rel-9HSPA, LTE-Advanced, can produce favourable feature.

Processor 105,705 can be implemented in hardware, software, firmware or their combining form.In a preferred embodiment, this processor 105,705 to utilize in this technical field known all following technology or their combination and implements within hardware: discrete logic, has the gate for actuating logic function on data-signal; Application-specific IC (ASIC), has suitable gate capable of being combined; Programmable gate array (PGA); Field programmable gate array (FPGA) etc.In alternate embodiments, processor 105,705 to be stored in memory and to implement in software performed by suitable instruction execution system or firmware.

As one of ordinary skill in the art will appreciate, arbitrary process prescription in flow chart or block are appreciated that the module, fragment or the partial code that represent the one or more executable instructions comprised for performing logic function concrete in process or step, and replacing executive mode is included in the scope of the preferred implementation of the application, in a preferred embodiment, according to comprised function, order (comprising the order of basic synchronization) that can be different from the order illustrated and discuss or in reverse order n-back test.

Claims (6)

1. a communication system, comprising:

First slave processor, comprising:

First FPDP, for primary processor swap data;

First input end of clock, for receiving the master clock signal from described primary processor;

First synchronous input end, for receiving the synchronizing signal from described primary processor;

First configurable delayer, for making the first slave processor clock synchronous with described primary processor, described first slave processor clock in response to described master clock signal and described synchronizing signal by synchronously;

First frequency shifter, for setting the first slave processor frequency;

First radio frequency receiver, for receiving the rf data from described primary processor;

First combiner, for combining the rf data of described first slave processor and the described rf data from described primary processor, to generate the rf data of combination;

And first radiofrequency launcher, operate under described first slave processor frequency, described first radiofrequency launcher is for launching the rf data of described combination.

2., according to the communication system described in claim 1, also comprise:

Described primary processor, comprising:

First primary data port, for described first slave processor swap data;

Master clock input, for receiving the clock signal from external clock reference;

Master clock output, for transmitting described master clock signal;

Main synchronous output end, for transmitting described synchronizing signal;

Main frequency shifter, for setting primary processor frequency;

Main radiofrequency launcher, operates under described primary processor frequency, and described main radiofrequency launcher is for launching the described rf data from described primary processor.

3. according to the communication system described in claim 2, described first slave processor frequency is identical with described primary processor frequency, and described communication system also comprises: the second slave processor, comprises: the second FPDP, for described primary processor swap data; Second clock input, for receiving described master clock signal; Second synchronous input end, for transmitting described synchronizing signal; Second configurable delayer, for making the second slave processor clock synchronous with described primary processor, described second slave processor clock in response to described master clock signal and described synchronizing signal by synchronously; Second frequency shifter, for setting the second slave processor frequency, described second slave processor frequency is identical with described primary processor frequency; Second radio frequency receiver, for receiving the rf data of described combination; Second combiner, for the rf data of the rf data and described combination that combine described second slave processor, to generate the rf data of combination further; And second radiofrequency launcher, operate under described second slave processor frequency, described second radiofrequency launcher is for launching the rf data of described further combination; And the second primary data port on described primary processor, described second primary data port and described second slave processor swap data.

4. communication system according to claim 2: described primary processor frequency is different from described first slave processor frequency, and described first slave processor comprises the second radiofrequency launcher for launching the first slave processor rf data further; And described primary processor comprises further: main radio frequency receiver, for receiving described first slave processor rf data; Main combiner, for combining the rf data of described primary processor and described first slave processor rf data, to generate the rf data of main combination; And the second main radiofrequency launcher, operate under described primary processor frequency, described second main radiofrequency launcher is for launching the rf data of described main combination.

5. according to the communication system described in claim 1, described first slave processor comprises further: the second radio frequency receiver, for receiving the rf data from described primary processor; Second combiner, for combining the described rf data of described first slave processor and the described rf data from described primary processor, to generate the rf data of the second combination; And second radiofrequency launcher, for launching the rf data of described second combination.

6. according to the communication system described in claim 5, described primary processor comprises further: main radiofrequency launcher, for rf data described in the described rf data from described primary processor being emitted to described second radio frequency receiver of described first slave processor.