CN104796634B - A kind of pixel biasing circuit and control method for super large face array CMOS image sensor - Google Patents
A kind of pixel biasing circuit and control method for super large face array CMOS image sensor Download PDFInfo
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Abstract
The invention discloses a kind of pixel biasing circuit and control method for super large face array CMOS image sensor, it is therefore intended that：Reduce ground wire dead resistance influences on pixel bias current precision and uniformity, while reduces the influence of pixel leakage current and alignment parasitic capacitance to row FPN, and used technical scheme is：Including the first order bias current generating circuit being sequentially connected, second level bias current generating circuit and third level bias current generating circuit, first order bias current generating circuit, second level bias current generating circuit and third level bias current generating circuit are using the high amplitude of oscillation cascode structure of two equal currents inputs, first order bias current generating circuit, the inside of second level bias current generating circuit and third level bias current generating circuit is by the way of voltage transmission, first order bias current generating circuit, second level bias current generating circuit and third level bias current generating circuit are between any two by the way of electric current transmission.
Description
Technical field
The invention belongs to cmos image sensor technical field, and in particular to one kind is used to surpass large area array CMOS images biography
The pixel biasing circuit and control method of sensor.
Background technology
In the cmos image sensor of main flow, pixel structure is mainly using source follower as output device, pixel
Current source load of the biasing circuit as source follower, high accuracy and the high row electric current of uniformity are provided for pixel array, really
Protect the work of pixel array normal table.In small-scale cmos image sensor, report that precision highest is that voltage leads to so far
Road pattern cascode structure pixel biasing circuit.However, in the cmos image sensor of ten million Pixel-level and the above, due to
Pixel biasing circuit power consumption rises and the increase of ground wire dead resistance, channel-length modulation have had a strong impact on pixel biasing circuit
Output current relative accuracy so that under voltage path pattern pixel biasing circuit different lines export Current compliance it is poor, figure
As the column fixed pattern noise (FPN) of sensor is difficult to reduce.In addition, in the cmos image with row pixels thousands of or even up to ten thousand
In sensor, the alignment dead resistance of tens k Ω levels and the parasitic capacitance of pF levels seriously limit the foundation of alignment and turn off speed
Degree, and the row of pA levels selects switch leakage current to turn into one of limitation image sensor line FPN principal element.
Fig. 1 is traditional pixel array and its biasing circuit schematic diagram, and by taking N=64 row pixel arrays as an example, wherein pixel is inclined
Circuits 100 include bias-voltage generating circuit 103 and the cascode current generation circuit 104-167 of voltage transmission mode.
The two-way electric current that current source 101 inputs is converted to bias voltage by bias-voltage generating circuit 103, is transmitted through voltage, common source is common
Gate current generation circuit 104-167 produces output current, the static working current as pixel array 102.
Fig. 2 is to consider that the pure voltage after ground wire dead resistance transmits cascade pixel biasing circuit, and bias voltage produces
Circuit includes NMOS tube 168-170, and first via input current is converted to bias voltage V by wherein NMOS tube 168H, NMOS tube
169th, 170 second road input current is converted into bias voltage VL, cascode current generation circuit is converted to bias voltage
Electric current exports, including common bank tube 171-234 and common source pipe 235-298, wherein bank tube meets bias voltage V altogetherH, common source pipe connects partially
Put voltage VL.If pixel biasing circuit is used for large area array pixel such as N much larger than 64, ground wire dead resistance 299-352 can be produced
Pressure drop, common source pipe 235-298 gate source voltage larger difference is present, cause each road electric current I of outputOUTDifference is big, each road
Output current uniformity is poor.
Fig. 3 is to consider M rows pixel, pixel biasing circuit and the sampling hold circuit schematic diagram after pixel alignment parasitism, with M
Exemplified by=64, wherein, pixel 353-416 output is connected by column bus 547.Dead resistance 417-480 and parasitic capacitance 481-
544 be the parasitism of metal column bus 547 under unit pixel width, and the output end of column bus 547 is connected to the He of sampling switch 545
Sampling capacitance 546.When M is much larger than 64, even if the row choosing switch of pixel disconnects, its larger leakage current also can be parasitic in alignment
Certain electric charge is stored on electric capacity 481-544, and its storage amount of charge of not going together is inconsistent, turns into image sensor line FPN's
One of principal element.
The content of the invention
In order to solve the problems of the prior art, the present invention proposes that one kind can reduce ground wire dead resistance and pixel is biased
Current precision and uniformity influence, while reduce the influence of pixel leakage current and alignment parasitic capacitance to row FPN is used for super large
The high-speed, high precision pixel biasing circuit and control method of face array CMOS image sensor.
In order to realize the above object the technical solution adopted in the present invention is：One kind is used to surpass large area array CMOS images biography
The pixel biasing circuit of sensor, including the first order bias current generating circuit, the second level bias current that are sequentially connected produce electricity
Road and third level bias current generating circuit, first order bias current generating circuit are connected with the current source of two-way, and described
One-level bias current generating circuit, second level bias current generating circuit and third level bias current generating circuit use two
The high amplitude of oscillation cascode structure of equal currents input, first order bias current generating circuit and second level bias current produce electricity
Road is exported using PMOS, and third level bias current generating circuit is exported using NMOS；Described first order bias current produces
The inside of circuit, second level bias current generating circuit and third level bias current generating circuit is using the side of voltage transmission
Formula, first order bias current generating circuit, second level bias current generating circuit and third level bias current generating circuit are two-by-two
Between using electric current transmission by the way of.
The input of described first order bias current generating circuit is two-way current signal, exports and believes for 2n roads equal currents
Number, and connect n second level bias current generating circuit；The output of each second level bias current generating circuit is equivalent for 2m roads
Current signal, and connect m third level bias current generating circuit；The output of each third level bias current generating circuit is 2l
Road equal currents signal, so as to realize the output of n × m × l roads equal currents signal.
It is respectively provided with described first order bias current generating circuit and the input of second level bias current generating circuit
There is global controlling switch, in first order bias current generating circuit, the drain electrode of global controlling switch is input, and grid connects
Global sequential control circuit, source electrode connect grid end caused by the bias voltage of high amplitude of oscillation cascode structure；In second level biased electrical
Flow in generation circuit, the output PMOS of the drain electrode connection first order bias current generating circuit of global controlling switch drain electrode, grid
Pole connects global sequential control circuit, and source electrode connects grid end caused by the bias voltage of high amplitude of oscillation cascode structure.
Described first order bias current generating circuit, second level bias current generating circuit and the miscarriage of third level biased electrical
NMOS charge discharging resistings switch is provided between the NMOS voltages transmission bias point and ground wire of raw circuit, described NMOS electric charges are let out
Decontrol the grid that the drain electrode connection NMOS cascode structures closed produce bias voltage, grid connection sequential control circuit, source electrode
Connect ground level.
The PMOS voltages transmission of described first order bias current generating circuit and second level bias current generating circuit is inclined
Put and PMOS charge discharging resistings switch is a little provided between power line, the source electrode connection power supply of described PMOS charge discharging resistings switch
Voltage, grid connect global sequential control circuit, and drain electrode connection PMOS cascode structures produce the grid of bias voltage.
NMOS row are provided between the NMOS outputs of described third level bias current generating circuit and pixel alignment to control
Switch, the drain electrode connection pixel array column line of NMOS row controlling switches, grid connection row control circuit, the source electrode connection third level are inclined
Put the output of current generating circuit.
NMOS pre-arcing switch is provided between the pixel alignment and ground wire of described third level bias current generating circuit,
The drain electrode connection pixel array column line of NMOS pre-arcing switch, grid connection pre-arcing sequential control circuit, source electrode connection ground electricity
It is flat.
The control sequential of described PMOS charge discharging resistings switch is consistent with the control sequential of the global controlling switch, described
The control sequential of NMOS charge discharging resistings switch is opposite with the control sequential of the global controlling switch.
Described NMOS pre-arcing switch of short duration closure before each sampling switch opening.
A kind of control method of pixel biasing circuit for super large face array CMOS image sensor, including：Described in control
Global controlling switch switch to closure state from off-state at the first moment, the control of described PMOS charge discharging resistings switch
Sequential processed is consistent with the control sequential of described global controlling switch, and the control sequential of described NMOS charge discharging resistings switch is
The inverted signal of described global controlling switch control sequential；
The described NMOS row controlling switch of control switches to closure state at the second moment from off-state, and described second
Moment was later than for the first moment；
The described NMOS pre-arcing of control switchs switches to closure state at the 3rd moment from off-state, and at the 4th
To carve from closure state and switch to off-state, the 5th moment started to sample, after the completion of to be sampled, described NMOS row controlling switches
Off-state is switched to from closure state, the 3rd described moment was later than for the second moment, and the 4th moment was later than for the 3rd moment, and the 5th
Moment was later than for the 4th moment.
Compared with prior art, circuit of the invention realizes that the pixel under large area array biases using three level conversions, first
Level is transmitted for short distance ionization voltage, and using high amplitude of oscillation cascode structure, i.e., input is two-way current signal, cascode structure
With the higher amplitude of oscillation, meet low supply voltage design requirement.First order bias current generating circuit is miscarried with second level biased electrical
Transmitted between raw circuit using electric current, because electric current transmission can meet required precision of the transmission to signal over long distances, so the
One-level bias current generating circuit and second level bias current generating circuit can be present on chip layout between larger physics
Away from.Second level bias current generating circuit transmits for short distance ionization voltage, and using high amplitude of oscillation cascode structure, input two-way is equivalent
Current signal, this two-way current signal are transmission of the current signal through long range of first order bias current generating circuit output
And obtain, the output of first order bias current generating circuit can input for the electric current of second level bias current generating circuit simultaneously, often
Individual second level bias current generating circuit exports equal currents signal.Second level bias current generating circuit and third level biased electrical
Transmitted between stream generation circuit using electric current, therefore second level bias current generating circuit can with third level bias current generating circuit
With apart from each other on domain, the current signal transfer of long distance and high precision is realized.Third level bias current generating circuit is short
Transmitted apart from voltage, using high amplitude of oscillation cascode structure, input two-way equal currents signal, this two-way current signal is the
The current signal of two level bias current generating circuit output is transmitted and obtained through long range, and each second level bias current produces electricity
Road can provide high-precision current input, each third level bias current generating circuit for third level bias current generating circuit simultaneously
Export equal currents signal.In the transmission of short-range signal, voltage, which transmits, can meet high-precision requirement, caused by large area array
For long range signals line when transmitting electric current, current value is constant all the time, i.e., voltage path is suitable for short-range signal transmission, electric current
Path is suitable for remote signal transmission.The pixel biasing circuit can use short distance ionization voltage to transmit, and long range electric current passes
Defeated, classification is implemented in order to ensure that conversion accuracy and coherence request.The circuit of the present invention is combined using current path-voltage path
Three-level step pattern, be capable of the electric current output of the high uniformity of high accuracy altogether, reliable and stable quiescent biasing provided for N row pixels
Electric current, influence of the ground wire dead resistance to pixel bias current precision and uniformity can be reduced.
Further, the input of first order bias current generating circuit is two-way current signal, is exported as 2n roads equal currents
Signal, and connect n second level bias current generating circuit；The output of each second level bias current generating circuit is 2m roads etc.
It is worth current signal, and connects m third level bias current generating circuit；The output of each third level bias current generating circuit is
2l roads equal currents signal, so as to realize the output of n × m × l roads equal currents signal, provided for N row pixels reliable and stable
Quiescent bias current.
Further, it is all provided with the input of first order bias current generating circuit and second level bias current generating circuit
Be equipped with global controlling switch, can control the present invention biasing circuit work whether.
Further, first order bias current generating circuit, second level bias current generating circuit and third level biased electrical
NMOS charge discharging resistings switch, first order biased electrical are provided between the NMOS voltages transmission bias point and ground wire of stream generation circuit
It is provided between the PMOS voltages of stream generation circuit and the second level bias current generating circuit transmission bias point and power line
PMOS charge discharging resistings switch, and can speed up circuit turn-off speed and improve the reliability of circuit.
Further, a NMOS is set to arrange control between the output of third level bias current generating circuit and pixel alignment
System is switched to realize the control to pixel row, is disconnected NMOS row controlling switches in the non-reading stage, can effectively be reduced pixel battle array
Row operating power consumption.
Further, it is provided with NMOS pre-arcing between the pixel alignment and ground wire of third level bias current generating circuit
Switch, the of short duration closure NMOS pre-arcing switch before pixel each time reads data, it is ensured that alignment level is in output number every time
According to fixing before, row FPN can be effectively reduced.
Further, NMOS pre-arcing switch of short duration closure, NMOS charge discharging resistings before each sampling switch opening is opened
The control sequential of pass is the inverted signal of global controlling switch sequential, and control sequential and the overall situation control of PMOS charge discharging resistings switch are opened
The sequential of pass is consistent so that when off, the electric charge stored on NMOS and PMOS parasitic gate capacitances can quickly release biasing circuit
To ground wire or power line, it is ensured that circuit stability turns off, and NMOS row controlling switch is entirely reading stage closure.
The control method of the present invention is by controlling PMOS charge discharging resistings to switch, NMOS charge discharging resistings switch, global control is opened
Close, the sequential of NMOS row controlling switch and pre-arcing switch, can reduce ground wire dead resistance to pixel bias current precision and
The influence of uniformity, while reduce the influence of pixel leakage current and alignment parasitic capacitance to row FPN.
Brief description of the drawings
Fig. 1 is pixel array and its biasing circuit schematic diagram；
Fig. 2 is traditional pure voltage transmission cascade pixel biasing circuit figure with ground wire dead resistance；
Fig. 3 is with alignment parasitic M rows pixel, single-row pixel biasing circuit and sampling hold circuit schematic diagram；
Fig. 4 is the pixel biasing circuit block diagram of the present invention；
Fig. 5 A are first order bias current generating circuit figures；
Fig. 5 B are second level bias current generating circuit figures；
Fig. 5 C are third level bias current generating circuit figures；
Fig. 6 is the pixel biasing circuit timing Design figure of the present invention；
Wherein, 100 be pixel biasing circuit, 101 be current source, 102 be pixel array, 103 be bias voltage produce electricity
Road, 104-167 are cascode current generation circuit, 168-170 is NMOS tube, 171-234 is common bank tube, 235-298 is altogether
Source capsule, 299-352 ground wires dead resistance, 353-416 are pixel, 417-480 dead resistances, 481-544 are parasitic capacitance, 545
It is sampling capacitance for sampling switch, 546,547 be column bus, 548 be first order bias current generating circuit, 549 is the second level
Bias current generating circuit, 550 be third level bias current generating circuit, 551 be NMOS charge discharging resistings switch, 552 be PMOS
Charge discharging resisting switch, 553 be global controlling switch, 554 be NMOS row controlling switch, 555 be NMOS pre-arcing switch.
Embodiment
With reference to embodiment, the invention will be further described.
Referring to Fig. 4, pixel biasing circuit of the invention include be sequentially connected first order bias current generating circuit 548,
Second level bias current generating circuit 549 and third level bias current generating circuit 550, first order bias current generating circuit
548 are connected with the current source 101 of two-way, and described first order bias current generating circuit 548, second level bias current produce electricity
The high amplitude of oscillation cascode structure that road 549 and third level bias current generating circuit 550 are inputted using two equal currents, the
One-level bias current generating circuit 548 and second level bias current generating circuit 549 are exported using PMOS, third level biased electrical
Generation circuit 550 is flowed to export using NMOS；Described first order bias current generating circuit 548, second level bias current produce
The inside of circuit 549 and third level bias current generating circuit 550 is by the way of voltage transmission, first order bias current
Generation circuit 548, second level bias current generating circuit 549 and third level bias current generating circuit 550 use between any two
The mode of electric current transmission.The input of described first order bias current generating circuit 548 is two-way current signal, is exported as 2n roads
Equal currents signal, and connect n second level bias current generating circuit 549；Each second level bias current generating circuit 549
Output be 2m roads equal currents signal, and connect m third level bias current generating circuit 550；Each third level biased electrical
The output for flowing generation circuit 550 is 2l roads equal currents signal, so as to realize the output of n × m × l roads equal currents signal.
Referring to Fig. 5 A and Fig. 5 B, first order bias current generating circuit 548 and second level bias current generating circuit 549
Global controlling switch 553, in first order bias current generating circuit 548, global controlling switch are provided with input
553 drain electrode is input, and grid connects global sequential control circuit, and source electrode connects the bias voltage of high amplitude of oscillation cascode structure
Caused grid end；In second level bias current generating circuit 549, the drain electrode connection first order biasing of global controlling switch 553
The output PMOS of current generating circuit 548 drain electrode, grid connect global sequential control circuit, and source electrode connects high amplitude of oscillation common source and is total to
Grid end caused by the bias voltage of grid structure.
Referring to Fig. 5 A, Fig. 5 B and Fig. 5 C, first order bias current generating circuit 548, second level bias current generating circuit
NMOS electric charges are provided between 549 and the NMOS voltages transmission bias point and ground wire of third level bias current generating circuit 550
Release switch 551, the drain electrode connection NMOS cascode structures of described NMOS charge discharging resistings switch 551 produce bias voltage
Grid, grid connection sequential control circuit, source electrode connection ground level.
Referring to Fig. 5 A and Fig. 5 B, first order bias current generating circuit 548 and second level bias current generating circuit 549
PMOS voltages, which transmit, is provided with PMOS charge discharging resistings switch 552, described PMOS charge discharging resistings between bias point and power line
The source electrode connection supply voltage of switch 552, grid connect global sequential control circuit, drain electrode connection PMOS cascode structure productions
The grid of raw bias voltage.
Referring to Fig. 5 C, NMOS is provided between the NMOS outputs of third level bias current generating circuit 550 and pixel alignment
Row controlling switch 554, the drain electrode connection pixel array column line of NMOS row controlling switch 554, grid connection row control circuit, source electrode
Connect the output of third level bias current generating circuit.
NMOS is provided with referring to Fig. 5 C, between the pixel alignment and ground wire of third level bias current generating circuit 550 to put in advance
Electric switch 555, the drain electrode connection pixel array column line of NMOS pre-arcing switch 555, grid connection pre-arcing sequential control circuit,
Source electrode connects ground level.
Referring to Fig. 6, the control sequential of the control sequential and the global controlling switch 553 of PMOS charge discharging resistings switch 552
Unanimously, the control sequential of the NMOS charge discharging resistings switch 551 is opposite with the control sequential of the global controlling switch 553.
The of short duration closure before each sampling switch 545 opening of NMOS pre-arcing switch 555.
Referring to Fig. 6, the control method of pixel biasing circuit of the present invention, including：The described global controlling switch 553 of control exists
First moment switched to closure state from off-state, the control sequential of described PMOS charge discharging resistings switch 552 with it is described
The control sequential of global controlling switch 553 is consistent, and the control sequential of described NMOS charge discharging resistings switch 551 is the described overall situation
The inverted signal of the control sequential of controlling switch 553；
The described NMOS row controlling switch 554 of control switches to closure state at the second moment from off-state, described
Second moment was later than for the first moment；
The described NMOS pre-arcing switch 555 of control switches to closure state at the 3rd moment from off-state, and the
Four moment switched to off-state from closure state, and the 5th moment started to sample, after the completion of to be sampled, described NMOS row controls
Switch 554 switches to off-state from closure state, and the 3rd described moment was later than for the second moment, when the 4th moment was later than the 3rd
Carve, the 5th moment was later than for the 4th moment.
When the columns of pixel is N, pixel biasing circuit needs to provide precision and consistent sexual satisfaction one for each row pixel
The bias current of provisioning request.When n is large, traditional voltage path cascade current source circuit is difficult to meet precision and uniformity
Requirement.For this problem, the present invention is based on the discovery that：In the transmission of short-range signal, voltage transmission can be with
Meet high-precision requirement, for long range signals line caused by large area array when transmitting electric current, current value is constant all the time, i.e. voltage path
It is suitable for short-range signal transmission, current path is suitable for remote signal transmission.
The pixel biasing circuit of the present invention is transmitted using short distance ionization voltage, and long range electric current transmission, classification is implemented in order to ensure that
Conversion accuracy and coherence request.The present invention realizes the pixel biasing circuit under large area array using three level conversions.The first order is inclined
Put current generating circuit 548 to transmit for short distance ionization voltage, using high amplitude of oscillation cascode structure, i.e. input is believed for two-way electric current
Number, output 2n roads equal currents signal.Improved cascode structure has the higher amplitude of oscillation, meets that low supply voltage design will
Ask.Transmitted between first order bias current generating circuit 548 and second level bias current generating circuit 549 using electric current, due to
Electric current transmission can meet required precision of the transmission to signal over long distances, so first order bias current generating circuit 548 and the
Two level bias current generating circuit 549 can have larger physics spacing on chip layout.Second level bias current produces
Circuit 549 transmits for short distance ionization voltage, using improved cascode structure, inputs two-way equal currents signal, this two-way electricity
Stream signal is that the current signal of first order output obtains through the transmission of long range, and first order output can be simultaneously n second
Level short distance voltage path module provides high-precision electric current input, and each second level bias current generating circuit 549 exports 2m
Road equal currents signal.Using electricity between second level bias current generating circuit 549 and third level bias current generating circuit 550
Streaming, therefore second level bias current generating circuit 549 can be on domain apart with third level bias current generating circuit 550
Farther out, the current signal transfer of long distance and high precision is realized.Third level bias current generating circuit 550 passes for short distance ionization voltage
It is defeated, using improved cascode structure, two-way equal currents signal is inputted, this two-way current signal is what the second level exported
Current signal is transmitted and obtained through long range, and each second level bias current generating circuit 549 can bias for the m third level simultaneously
Current generating circuit 550 provides high-precision current input, and each third level bias current generating circuit 550 exports 2l roads electric current letter
Number.The three-level step pattern that current path-voltage path is combined can realize N=n × m × l roads high uniformity in high precision altogether
Electric current is exported, and reliable and stable quiescent bias current is provided for N row pixels.
In the short-range voltage path module of three-level, the grid short circuit of multichannel NMOS tube/PMOS is in same biasing
On level, a switch of NMOS charge discharging resistings switch 551 is added between the grid and ground wire of NMOS tube, grid are obtained in PMOS
PMOS charge discharging resisting switch 552 is added between pole and ground wire, electricity during for realizing global shut-off on parasitic gate electric capacity
Lotus is quickly released.
Between the output of third level bias current generating circuit and pixel alignment, NMOS row controlling switch 554 is set
The control to pixel row is realized, disconnects NMOS row controlling switch 554 in the non-reading stage, can effectively reduce the work of pixel array
Power consumption.In addition, NMOS pre-arcing switch 555 is set between pixel alignment and ground wire, it is short before pixel each time reads data
Temporarily closure NMOS pre-arcing switch 555, it is ensured that alignment level is fixed before each output data, effectively to reduce row FPN.
It is as shown in Figure 4 according to the circuit block diagram that above-mentioned thought is realized.It is in traditional pure voltage path pixel shown in Fig. 2
It is improved on the basis of biasing circuit, including first order short distance ionization voltage transmission cascode current generation circuit 548, second
Level short distance ionization voltage transmission cascode current generation circuit 549, third level short distance ionization voltage transmission cascode current produce
Transmitted using electric current between circuit 550, the wherein first order and the second level, transmitted between the second level and the third level using electric current, and
Transmitted using voltage inside at different levels.Specific three-level circuit is respectively as shown in Fig. 5 A, Fig. 5 B and Fig. 5 C.Devised in every one-level
NMOS tube charge discharging resisting switch 551 and PMOS obtain charge discharging resisting switch 552, in addition, add global controlling switch 553,
The row controlling switch 554 of the third level and pre-arcing switch 555.The timing Design of pre-arcing circuit is as shown in Figure 6.Pre-arcing switchs
555 is of short duration for height before sampling switch turns on every time.
The circuit implementing scheme of the present invention with the pure voltage transmission cascade pixel of tradition shown in Fig. 2 as shown in figure 4, bias
Circuit is different, and structure is realized in the cascade classification that circuit of the invention is combined using voltage transmission and electric current transmission.It is at different levels
Specific circuit as shown in Fig. 5 A, Fig. 5 B and Fig. 5 C, the more NMOS pre-arcing circuits 555 of the pixel biasing circuit of new construction,
NMOS charge discharging resistings switch 551, PMOS charge discharging resistings switch 552, global controlling switch 553 and third level output NMOS row controls
System switch 554.The of short duration closure before each sampling switch 545 opening of NMOS pre-arcing switch 555.NMOS charge discharging resistings switch
551 control sequential for global controlling switch 553 sequential inverted signal, PMOS charge discharging resistings switch 552 control sequential with
The sequential of global controlling switch 553 is consistent so that biasing circuit when off, the electricity stored on NMOS and PMOS parasitic gate capacitances
Lotus can quickly be released to ground wire/power line, it is ensured that circuit stability is turned off, and NMOS row controlling switch 554 is closed in the whole reading stage
Close.
In Fig. 5 A, first order bias current generating circuit 548 transmits high amplitude of oscillation cascode structure using short distance ionization voltage,
2 road electric current input 2n roads electric current outputs are realized, and use the PMOS way of outputs, second level biased electrical is transferred to through long range electric current
Generation circuit 549 is flowed, second level bias current generating circuit 549 transmits high amplitude of oscillation cascode structure using short distance ionization voltage,
2 road electric current input 2m roads electric current outputs are realized, and use the PMOS way of outputs, third level biasing is transferred to through long range electric current
Current generating circuit 550, third level bias current generating circuit 550 transmit high amplitude of oscillation cascade knot using short distance ionization voltage
Structure, 2 road electric current input 2l roads electric current outputs are realized, and use the NMOS way of outputs, finally exported with N=n × m × l roads electric current
Quiescent bias circuit as N row pixels.
The feature of first order bias current generating circuit 548 is：1) using the high amplitude of oscillation cascode structure of two inputs, expand
The amplitude of oscillation is opened up, reduces the status requirement to input current source and the biasing circuit；2) exported using 2n roads PMOS, through long range
Electric current transmits the input as second level short distance ionization voltage transmission circuit；3) NMOS overall situation controlling switches are added in two-way input
553, can control the biasing circuit work whether；4) transmitted in NMOS voltages and NMOS electricity is added between bias point and ground wire
Lotus is released switch 551, is transmitted in PMOS voltages and PMOS charge discharging resistings switch 552 is added between bias point and power line, accelerate electricity
Road turn-off speed has simultaneously improved reliability.
The feature of second level bias current generating circuit 549 is：1) using the high amplitude of oscillation cascode structure of two inputs, expand
The amplitude of oscillation is opened up, reduces the status requirement to the first order and second level current generating circuit；2) exported using 2m roads PMOS, through it is long away from
From electric current transmit input as third level short distance ionization voltage transmission circuit.In addition, equally have in first order biasing circuit
NMOS overall situations controlling switch 553, NMOS charge discharging resistings switch 551 and PMOS charge discharging resistings switch 552.
The feature of third level bias current generating circuit 550 is：1) using the high amplitude of oscillation cascode structure of two inputs, expand
The amplitude of oscillation is opened up, reduces the second level and the status requirement of third level biasing circuit；2) exported using 2l roads NMOS, the electricity through long range
Quiescent biasing of the streaming as pixel；3) NMOS row controlling switch 554 is added between NMOS outputs and pixel alignment；4) exist
NMOS pre-arcing switch 555 is added between pixel alignment and ground wire.In addition, equally there is the NMOS electricity in first order biasing circuit
Lotus is released switch 551.
The present invention is improved on the basis of existing pure voltage transmission pixel biasing circuit, proposes that short distance ionization voltage passes
Defeated, long range electric current transmission classification realizes the pixel biasing circuit of duplex high precision electric current output, and adds pre-arcing and open
Pass, global controlling switch, row controlling switch, NMOS charge discharging resistings switch and PMOS charge discharging resistings switch, it is real by SECO
Now rapidly switch off and effectively reduce row FPN.Present invention reduces ground wire dead resistance to pixel bias current precision and uniformity
Influence, reduce the influence of pixel leakage current and alignment parasitic capacitance to row FPN.
Claims (10)
- A kind of 1. pixel biasing circuit for super large face array CMOS image sensor, it is characterised in that：Including what is be sequentially connected First order bias current generating circuit (548), second level bias current generating circuit (549) and third level bias current produce electricity Road (550), first order bias current generating circuit (548) are connected with the current source (101) of two-way, described first order biased electrical Stream generation circuit (548), second level bias current generating circuit (549) and third level bias current generating circuit (550) are adopted The high amplitude of oscillation cascode structure inputted with two equal currents, first order bias current generating circuit (548) and the second level are inclined Put current generating circuit (549) to export using PMOS, third level bias current generating circuit (550) is exported using NMOS；Institute First order bias current generating circuit (548), second level bias current generating circuit (549) and the miscarriage of third level biased electrical stated The inside of raw circuit (550) is by the way of voltage transmission, first order bias current generating circuit (548), second level biasing Current generating circuit (549) and third level bias current generating circuit (550) are between any two by the way of electric current transmission.
- 2. a kind of pixel biasing circuit for super large face array CMOS image sensor according to claim 1, its feature It is：The input of described first order bias current generating circuit (548) is two-way current signal, is exported as 2n roads equal currents Signal, and connect n second level bias current generating circuit (549)；Each second level bias current generating circuit (549) is defeated Chu Wei 2m roads equal currents signal, and connect m third level bias current generating circuit (550)；Each third level bias current The output of generation circuit (550) is 2l roads equal currents signal, so as to realize the output of n × m × l roads equal currents signal.
- 3. a kind of pixel biasing circuit for super large face array CMOS image sensor according to claim 2, its feature It is：On described first order bias current generating circuit (548) and the input of second level bias current generating circuit (549) Global controlling switch (553) is provided with, in first order bias current generating circuit (548), global controlling switch (553) Drain and connect global sequential control circuit for input, grid, the bias voltage that source electrode connects high amplitude of oscillation cascode structure produces Grid end；In second level bias current generating circuit (549), the drain electrode connection first order biasing of global controlling switch (553) The output PMOS of current generating circuit (548) drain electrode, grid connect global sequential control circuit, and source electrode connects high amplitude of oscillation common source Grid end caused by the bias voltage of common gate structure.
- 4. a kind of pixel biasing circuit for super large face array CMOS image sensor according to claim 3, its feature It is：Described first order bias current generating circuit (548), second level bias current generating circuit (549) and the third level are inclined Put and NMOS charge discharging resistings switch is provided between the NMOS voltages transmission bias point of current generating circuit (550) and ground wire (551), the drain electrode connection NMOS cascode structures of described NMOS charge discharging resistings switch (551) produce the grid of bias voltage Pole, grid connection sequential control circuit, source electrode connection ground level.
- 5. a kind of pixel biasing circuit for super large face array CMOS image sensor according to claim 4, its feature It is：Described first order bias current generating circuit (548) and the PMOS voltages of second level bias current generating circuit (549) PMOS charge discharging resistings switch (552), described PMOS charge discharging resistings switch are provided between transmission bias point and power line (552) source electrode connection supply voltage, grid connect global sequential control circuit, and drain electrode connection PMOS cascode structures produce The grid of bias voltage.
- 6. a kind of pixel biasing circuit for super large face array CMOS image sensor according to claim 5, its feature It is：NMOS row are provided between the NMOS outputs of described third level bias current generating circuit (550) and pixel alignment to control System switch (554), the drain electrode connection pixel array column line of NMOS row controlling switch (554), grid connection row control circuit, source electrode Connect the output of third level bias current generating circuit.
- 7. a kind of pixel biasing circuit for super large face array CMOS image sensor according to claim 6, its feature It is：NMOS pre-arcing is provided between the pixel alignment and ground wire of described third level bias current generating circuit (550) to open Close (555), the drain electrode connection pixel array column line of NMOS pre-arcing switch (555), grid connection pre-arcing sequential control circuit, Source electrode connects ground level.
- 8. a kind of pixel biasing circuit for super large face array CMOS image sensor according to claim 7, its feature It is：The control sequential and the control sequential one of the global controlling switch (553) of described PMOS charge discharging resistings switch (552) Cause, the control sequential of the NMOS charge discharging resistings switch (551) is opposite with the control sequential of the global controlling switch (553).
- 9. a kind of pixel biasing circuit for super large face array CMOS image sensor according to claim 8, its feature It is：Described NMOS pre-arcing switch (555) of short duration closure before each sampling switch (545) opening.
- A kind of 10. controlling party of the pixel biasing circuit as claimed in claim 9 for super large face array CMOS image sensor Method, it is characterised in that including：The described global controlling switch (553) of control switches to closure at the first moment from off-state State, the control sequential of the control sequential of described PMOS charge discharging resistings switch (552) and described global controlling switch (553) Unanimously, the control sequential of described NMOS charge discharging resistings switch (551) is described global controlling switch (553) control sequential Inverted signal；The described NMOS row controlling switch (554) of control switches to closure state at the second moment from off-state, and described the Two moment were later than for the first moment；The described NMOS pre-arcing switch (555) of control switches to closure state at the 3rd moment from off-state, and the 4th Moment switches to off-state from closure state, and the 5th moment started to sample, and after the completion of to be sampled, described NMOS row controls are opened Close (554) and switch to off-state from closure state, the 3rd described moment was later than for the second moment, when the 4th moment was later than the 3rd Carve, the 5th moment was later than for the 4th moment.
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