CN104779792A - Control circuit and control method of vehicle-mounted charger DC-DC system - Google Patents

Abstract

The invention discloses a control circuit and a control method of a vehicle-mounted charger DC-DC system. The control method comprises the following steps: using a light-load comparator, a line loss compensation comparator and a peak current limit comparator, connecting negative input ends of the three comparators with an output signal of an error amplifier inside the DC-DC system, and connecting the positive input ends with voltages with different values, which are formed on serially-connected polysilicon resistors by positive temperature coefficient current output by a positive temperature coefficient current generating module; outputting light-load high-efficiency mode, line loss voltage compensation and peak current limit control signals at an output end. Through the control method, output current can be monitored, light-load high-efficiency mode, line loss compensation and peak current limit threshold values are determined, and the threshold values do not change along with the temperature; the control circuit is simple in functional principle and easy in process realization, can reduce the cost of a chip, is high in reliability, and is applicable to other DC-DC systems needing such functions.

Description

The control circuit of onboard charger DC-DC system and control method

Technical field

The present invention relates to one is applied in onboard charger DC-DC system, the positive temperature coefficient reference voltage produced by inside is compared with the sampled voltage of power tube metallic parasitic resistance, realize the technology that the restriction of the underloading high efficiency to DC-DC system output, line loss voltage compensation and peak current controls, belong to DC-DC converter technical field.

Background technology

Flourish along with portable type electronic product, dc-dc is widely used in electronic product, market prospects are boundless, also just more and more higher to the requirement of its performance, such as input and output voltage scope, output maximum current, power supply conversion efficiency, operating frequency and power volume etc.

Onboard charger is the application that DC-DC is newer; this kind of DC-DC belongs to BUCK type electric pressure converter; there is high voltage applications scope; and require higher underloading conversion efficiency; it is another because its output is to longer by the cable of charging device; larger voltage loss is had when High-current output, and not damaged by charging device for protecting, and the output current of DC-DC needs to be limited.Therefore in onboard charger DC-DC designs, the applied environment considering its reality is needed.

Fig. 1 is the synchronous rectification BUCK type DC-DC schematic diagram in vehicle-mounted charge applied environment, wherein on QH1, pipe is main switch, under QL2, pipe is synchro switch pipe, L1 is energy storage inductor, and Rl is inductance equivalent series resistance, and CL is filter capacitor, Rc is capacitor equivalent series resistance, Rcable is charge cable resistance, and VO1 is DC-DC output voltage, and VO2 is actual loading terminal voltage.

In each cycle, main switch QH1 first conducting is that inductance L 1 is charged, and inductance L 1 electric current rises, and stored energy, after certain duty ratio, main switch QH1 turns off.And inductance L 1 is by synchronous rectifier QL2 afterflow, and inductive current declines, and inductance L 1 releases energy to output, completes the power conversion that one-period is input to output like this.And by the voltage detecting of VFB and current detecting two feedback control loops of RM, duty ratio is controlled simultaneously, realize stable voltage and current and export.

In vehicle-mounted charge DC-DC applies, need consideration three kinds of output current situations emphatically.One is in the load trickle charge stage, and DC-DC can the electric current in output constant current stage 1/10, and being generally below 300mA, is reduce system power dissipation, needs to add underloading mode of operation and when certainty annuity enters light-load mode.Two is at constant-current charging phase, may continue for dissimilar load system the charging current exporting 1A-3A.And can see in FIG, the line resistance of about Rcable=150m Ω is there is between DC-DC output and actual loading, if output current is 2A, then this ohmically pressure drop will reach 300mV, will impact safely by charging system like this, therefore onboard charger DC-DC needs to add lambda line voltage loss compensate function.Three is if system exports be shorted to ground by mistake, then can cause inductance big current, therefore need to add peak current limitation function, to prevent big current conducting defective chip.

Summary of the invention

The present invention is directed to onboard charger DC-DC system environment characteristics, a kind of simple control circuit and the control method efficiently that realize onboard charger DC-DC system underloading high efficiency, line loss voltage compensation and peak current limitation function are provided.The present invention also can be applicable to other to be needed in the DC-DC system of this type of function, and circuit framework is simple, and technique is easy to realize, and reduce development cost, reliability is high.

Technical scheme of the present invention is as follows:

A kind of control circuit of onboard charger DC-DC system, comprise a underloading comparator, a line loss compensation comparator, a peak current restriction comparator and a positive temperature coefficient current generating module, described underloading comparator, the negative input of line loss compensation comparator and peak current restriction comparator connects the output signal of described onboard charger DC-DC system internal error amplifier, the voltage of the different value that the positive temperature coefficient electric current that positive input connects the output of described positive temperature coefficient current generating module is respectively formed on the polysilicon resistance of series connection, output exports underloading high effective model respectively, the control signal of line loss voltage compensation and peak current restriction.

A control method for onboard charger DC-DC system, comprises the steps:

(1) underloading comparator COMP1, line loss compensation comparator COMP2 and peak current restriction comparator COMP3 is set; The negative end of described three comparators is all connected the output signal VC of DC-DC system internal error amplifier, forward end then connects positive temperature voltage VPEAK, VCABLE and VLIGHT of the different value that a positive temperature coefficient electric current is formed on polysilicon resistance respectively;

(2) when load current reduces, when making the output signal VC of error amplifier lower than VLIGHT voltage, the output signal L_EN upset of underloading comparator COMP1 is for high, turn off DC-DC system internal clocking and produce signal, the main switch of DC-DC system is in lasting off state, load current is provided by output capacitance completely, and the output voltage VO 1 of DC-DC system declines, and the output signal VC voltage of error amplifier raises; When the output signal VC voltage of error amplifier is more than VLIGHT voltage, the output signal L_EN upset of underloading comparator COMP1 is for low, again enable clock signal, the main switch of DC-DC system is opened, inductive current rises, when sampled voltage VSENSE reaches the output signal VC of error amplifier, the PWM comparator of DC-DC system controls main switch and turns off, output capacitance is charged, the output signal VC of error amplifier declines and lower than after VLIGHT, enter the next cycle of light-load mode, and so forth, realize underloading high efficiency function;

(3) when load current increases, when making the output signal VC of error amplifier more than VCABLE voltage, the output signal C_EN upset of line loss compensation comparator COMP2 is for low, reference voltage VREF changes, the output voltage VO 1 of DC-DC system changes thereupon, make the output voltage VO 2 of actual loading end enter in zone of reasonableness, realize line voltage loss compensate function;

(4) when load current continues to increase, when making the output signal VC of error amplifier more than VPEAK voltage, the output signal P_EN upset of peak current restriction comparator COMP3 is for low, the main switch turning off DC-DC system exports, and controlling DC-DC system chip with module acting in conjunction of having the hiccups enters the pattern of having the hiccups simultaneously, reduce DC-DC system chip average output current, realize peak current limitation function.

Advantageous Effects of the present invention is:

The present invention is sampled with power tube voltage metal by the inner voltage producing a positive temperature coefficient and compares, and can realize the monitoring to output current, determine underloading efficiently, line loss compensation and peak current threshold limit, and threshold value does not vary with temperature.Circuit function principle is simple, and be easy to technique and realize, can reduce chip cost, reliability is high.

Advantage of the present invention provides in the description of embodiment part below, and part will become obvious from the following description, or be recognized by practice of the present invention.

Accompanying drawing explanation

Fig. 1 is onboard charger DC-DC schematic diagram.

Fig. 2 is VC and VSENSE waveform schematic diagram.

Fig. 3 is circuit theory schematic diagram of the present invention.

Fig. 4 is positive temperature coefficient current generating module schematic diagram.

Fig. 5 is that underloading is efficient, line loss compensation, peak current restrictive curve schematic diagram.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further.

As shown in Figure 1, on current sense amplifier detection power pipe path metallic parasitic resistance RM pressure drop and to its amplify, current sense amplifier exports the voltage signal VSENSE after for amplification, this voltage signal has the temperature coefficient identical with metallic resistance RM and is about 3000ppm, this VSENSE signal can be compared by PWM comparator with the output signal VC of internal error amplifier, to control output duty cycle change, each cycle is when VSENSE reaches VC, by switch-off power pipe, power tube is opened, and so forth when waiting for that next clock signal is come.Fig. 2 curve shows the relation of VSENSE and VC signal, the peak value of each like this cycle VSENSE signal can be equal with VC, therefore VC signal has identical variation tendency by with the peak value of VSENSE, and VSENSE comes from the sampling to power tube current, the therefore peak value of VSENSE proportional relation corresponding to inductive current and load current.

Namely the situation of output current can be reacted like this by VSENSE signal, different load current ranks will correspond to different VSENSE signal magnitude, also the output current size that namely the same correspondence of VC voltage amplitude is different, therefore can by selecting different VPTAT magnitudes of voltage and VC voltage compare, realize the control to the output loading different operating stage, and because two comparison signals have approximate temperature coefficient, therefore the control threshold value of this circuit framework to output current has the temperature coefficient close to zero.

Because VC signal is linear change, therefore replace VSENSE as comparison signal with VC.In Fig. 3, COMP1, COMP2 and COMP3 are respectively underloading, line loss compensation and peak current restriction comparator, and the negative end of three comparators is VC, and forward end is then the pressure drop of the different value that a PTAT electric current is formed on POLY resistance.Figure 4 shows that positive temperature coefficient current generating module, wherein POLY resistance has very little temperature coefficient, and finally can about fall, final positive temperature voltage VPEAK, VCABLE and VLIGHT formed has identical temperature coefficient with thermal voltage VT, and temperature coefficient is about 3000ppm.

Wherein COMP1 is that underloading controls comparator, when load current is lower than certain value, corresponding error amplifier output signal VC will lower than VLIGHT voltage, the output signal L_EN upset of COMP1 is for high, system will enter light-load mode, L_EN signal will control to turn off internal clocking and produce signal, because each cycle triggers upper power tube conducting by clock signal trailing edge, therefore clock signal is closed and is had no progeny, upper pipe will be in lasting off state, load current is provided by output capacitance completely, VO1 will decline, then VC voltage can raise, when VC voltage is more than VLIGHT voltage, L_EN upset is for low, again enable clock signal module, power tube is opened, inductive current rises, when VSENSE reaches VC, PWM comparator controls power output pipe and turns off, now output capacitance is charged, then VC will decline and after lower than VLIGHT, enter the next cycle of light-load mode, and so forth, this reduces the operating frequency of system, reduce switching loss.Like this by the setting to VLIGHT magnitude of voltage, can control to enter light-load mode when why load current is worth.

COMP2 is line loss compensation comparator, and when load current exceedes certain value, the output signal VC of error amplifier is more than VCABLE voltage, and C_EN output switching activity is low, control VREF module voltage changed, and the ratio adjusted trims by PAD.In the present embodiment, VREF voltage increases by 6%, such VO1 output voltage becomes 5.3V by from original 5V, then suppose when output current is 2A that the pressure drop loss in cable resistance is 300mV, so the actual output voltage of VO2 will be just 5V, so just compensate for line voltage loss, as long as and output voltage meets in certain limit usually, as 4.8V-5.2V, even if therefore line loss compensation voltage can not just in time coincide with loss voltage, also terminal voltage can be compensated in zone of reasonableness completely.

COMP3 is peak current restriction comparator, when load current is very large, the output signal VC of error amplifier will more than VPEAK voltage, P_EN output switching activity is low, P_EN signal will turn off output, and enter with HICCUP (having the hiccups) module acting in conjunction control chip the pattern of having the hiccups simultaneously, reduce chip average output current, so namely achieve peak current limitation function.

Quantize above-mentioned principle is described below by formula, for line loss compensation threshold calculations, by the derivation of current sense amplifier, can obtain there is following expression at current peak place:

wherein IQH1 is the peak current of the power tube that each cycle detection is arrived, and GCS is that current sense amplifier and metallic resistance RM combine the mutual conductance of deriving and obtaining, rP4 and RP5 is amplifier internal resistance, V _dCfor DC voltage amount, for determining DC working point (also measuring containing identical DC in positive temperature coefficient voltage) below.

Positive temperature coefficient voltage VCABLE is added that the expression formula after DC amount is as follows:

$V_{\mathrm{CABLE}}=\frac{{\mathrm{KV}}_T}{R_{P0}}*(R_{P1}+R_{P2})+V_{\mathrm{DC}}$

Equal by above two formulas, can obtain line loss voltage compensation circuit threshold expression is represent IQH1 with ICABLE:

$I_{\mathrm{CABLE}}=\frac{{\mathrm{KV}}_T}{R_{P0}}*(R_{P1}+R_{P2})*\frac{R_{P4}}{P_M*R_{P5}}=\frac{{\mathrm{KV}}_T}{R_M}*\frac{(R_{P1}+R_{P2})*R_{P4}}{R_{P0}*R_{P5}}=\frac{{\mathrm{KV}}_T}{R_M}*\frac{(K_1+K_2)*R_P*R_{P4}}{R_{P0}*R_{P5}}$

Therefore as can be seen from the above equation, POLY temperature coefficient of resistance can about be fallen, and thermal voltage VT and metallic resistance RM has approximately equalised temperature coefficient, and therefore obtaining ICALBE will have the temperature coefficient being approximately zero.And can find out, the detection to output current different value can be realized by K1, K2 and the K3 changed in Fig. 3, determine the threshold value that underloading high efficiency, line loss compensation and peak current limit.

ICABLE obtained in addition is the peak current of inductance, and is not actual load current value, and according to the operation principle of BUCK type DC-DC, load current is the mean value of inductive current, therefore can show that actual load current is:

wherein when converter steady operation, input voltage VIN, output voltage VO, upper pipe ON time TON and inductance value L are known quantity, and therefore ILOAD can be determined by ICABLE completely.

In sum, by setting internal resistance value, choose suitable VCABLE voltage, can obtain accordingly, when why load ILOAD is worth, adding line loss compensation amount to output voltage.Equally for underloading high efficiency and peak current restriction mode of operation, also can obtain similar result, therefore not repeat here to derive.

As shown in Figure 5, three curves are respectively load current, inductive current and output voltage.Known along with load current rising, inductive current also can follow change, first when load current is lower than 300mA, underloading comparator work, inductive current presents discontinuous operating mode (DCM), namely now chip operation in the light-load mode stage, switching frequency reduces, and reduces system power dissipation; When load current reaches 1A, inner line loss compensation comparator upset, VREF voltage is increased by 6%, and namely output voltage is increased to 5.3V by 5V, realizes line loss compensation function; Load current continues to increase, and when it is more than 5A, will control power output pipe and turn off, inductive current and output voltage all can be reduced to close to null value, and chip finally enters hiccup protections pattern.

Above-described is only the preferred embodiment of the present invention, the invention is not restricted to above embodiment.Be appreciated that the oher improvements and changes that those skilled in the art directly derive without departing from the basic idea of the present invention or associate, all should think and be included within protection scope of the present invention.

Claims (2)

1. the control circuit of an onboard charger DC-DC system, it is characterized in that, comprise a underloading comparator, a line loss compensation comparator, a peak current restriction comparator and a positive temperature coefficient current generating module, described underloading comparator, the negative input of line loss compensation comparator and peak current restriction comparator connects the output signal of described onboard charger DC-DC system internal error amplifier, the voltage of the different value that the positive temperature coefficient electric current that positive input connects the output of described positive temperature coefficient current generating module is respectively formed on the polysilicon resistance of series connection, output exports underloading high effective model respectively, the control signal of line loss voltage compensation and peak current restriction.

2. a control method for onboard charger DC-DC system, is characterized in that, comprises the steps:

(1) underloading comparator COMP1, line loss compensation comparator COMP2 and peak current restriction comparator COMP3 is set; The negative end of described three comparators is all connected the output signal VC of DC-DC system internal error amplifier, forward end then connects positive temperature voltage VPEAK, VCABLE and VLIGHT of the different value that a positive temperature coefficient electric current is formed on polysilicon resistance respectively;

(2) when load current reduces, when making the output signal VC of error amplifier lower than VLIGHT voltage, the output signal L_EN upset of underloading comparator COMP1 is for high, turn off DC-DC system internal clocking and produce signal, the main switch of DC-DC system is in lasting off state, load current is provided by output capacitance completely, and the output voltage VO 1 of DC-DC system declines, and the output signal VC voltage of error amplifier raises; When the output signal VC voltage of error amplifier is more than VLIGHT voltage, the output signal L_EN upset of underloading comparator COMP1 is for low, again enable clock signal, the main switch of DC-DC system is opened, inductive current rises, when sampled voltage VSENSE reaches the output signal VC of error amplifier, the PWM comparator of DC-DC system controls main switch and turns off, output capacitance is charged, the output signal VC of error amplifier declines and lower than after VLIGHT, enter the next cycle of light-load mode, and so forth, realize underloading high efficiency function;

(3) when load current increases, when making the output signal VC of error amplifier more than VCABLE voltage, the output signal C_EN upset of line loss compensation comparator COMP2 is for low, reference voltage VREF changes, the output voltage VO 1 of DC-DC system changes thereupon, make the output voltage VO 2 of actual loading end enter in zone of reasonableness, realize line voltage loss compensate function;

(4) when load current continues to increase, when making the output signal VC of error amplifier more than VPEAK voltage, the output signal P_EN upset of peak current restriction comparator COMP3 is for low, the main switch turning off DC-DC system exports, and controlling DC-DC system chip with module acting in conjunction of having the hiccups enters the pattern of having the hiccups simultaneously, reduce DC-DC system chip average output current, realize peak current limitation function.