CN104767414A - Redundancy control method for ISOP inverter assembly system - Google Patents
Redundancy control method for ISOP inverter assembly system Download PDFInfo
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- CN104767414A CN104767414A CN201510118342.8A CN201510118342A CN104767414A CN 104767414 A CN104767414 A CN 104767414A CN 201510118342 A CN201510118342 A CN 201510118342A CN 104767414 A CN104767414 A CN 104767414A
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- module
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- signaling switch
- moment
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/493—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode the static converters being arranged for operation in parallel
Abstract
The invention discloses a redundancy control method for an ISOP inverter assembly system and belongs to the field of direct current-alternating current converters of electric energy conversion devices. A bypass mode is adopted in the method to make a fault module exit from the system. When a module j# has a fault and exits from the system, a power output relay is disconnected, a power input relay is connected, a bypass of the fault module can be achieved, and a resistor is used for limiting discharging current input into a partial pressure capacitor ; when a new module j# is ready, the power input relay is disconnected, the power output relay is connected, and on-line input of the new module can be achieved. By means of the method, an accurate time sequence control chart is given, hot plug of the distributed ISOP inverter assembly system is completed, and improvement of reliability is realized really.
Description
Technical field
The present invention relates to the redundancy control method of a kind of input series and output parallel (ISOP) inverter combined system, belong to the direct-current-alternating-current converter field of electrical energy changer.
Background technology
Input series and output parallel (ISOP) inverter combined system is applicable to high voltage direct current input, big current exchanges the application scenario exported, the such as electrical system such as boats and ships, high-speed electrified line, it has the following advantages: in ISOP inverter combined system, each module is connected at input, the switching tube stress of module significantly reduces, and conveniently selects more suitably switching tube; The power of each module only has 1/ of system power
n(
nmodule number in system), more easily realize modularization; The connection in series-parallel combination of multimode effectively can improve the reliability of system.
In order to the reliability of real elevator system, the Redundant Control of system will be realized, realizing this target and need follow two steps: the distributed AC servo system that first will realize ISOP inverter combined system, is secondly then will realize its redundancy and warm connection function on the basis of distributed system.
Summary of the invention
In order to solve the redundancy hot plug problem of ISOP inverter combined system, the present invention proposes a kind of redundancy control method of ISOP inverter combined system, the reliability of ISOP inverter combined system can be promoted.
The present invention adopts following technical scheme for solving its technical problem:
A redundancy control method for ISOP inverter combined system, comprises the steps:
(1) when distributed I SOP inverter combined system is normally run, input power relay is disconnected
s j1
, closed power output relay
s j2
, closed three bus signaling switches, i.e. average current bus signaling switch
s j3
, input equalizing busbar signaling switch
s j4
and output voltage reference synchronization bus signaling switch
s j5
;
(2) when certain module of distributed I SOP inverter combined system breaks down, adopt the mode of bypass to realize exiting of this malfunctioning module, adopt redundancy sequential to realize the bypass of malfunctioning module by digital signal processor, namely when
jwhen # module breaks down and needs to be bypassed, disconnect power output relay
s j2
, closed input power relay
s j1
; Disconnect three bus signaling switches, i.e. average current bus signaling switch
s j3
, input equalizing busbar signaling switch
s j4
and output voltage reference synchronization bus signaling switch
s j5
; And block prime DC/DC converter and rear class straight-the switching tube drive singal of AC-AC converter;
(3) when
j# new module is ready, adopts putting into operation of redundancy sequencing control new module by digital signal processor, namely disconnects input power relay
s j1
, closed power output relay
s j2
; Closed bus signaling switch, namely closes
s j3
, input equalizing busbar signaling switch
s j4
and output voltage reference synchronization bus signaling switch
s j5
; And enable prime DC/DC converter and rear class straight-the switching tube drive singal of AC-AC converter.
The bypass that employing redundancy sequential in described step (2) realizes malfunctioning module refers to, when digital signal processor detected in the T1 moment
j# module breaks down, block immediately DC/DC converter and rear class straight-the switching tube drive singal of AC-AC converter; In the T2 moment, close three bus signaling switches, i.e. average current bus signaling switch
s j3
, input equalizing busbar signaling switch
s j4
and output voltage reference synchronization bus signaling switch
s j5
; Provide closed input relay simultaneously
s j1
, disconnect output relay
s j2
control signal; T3 moment power output relay
s j2
disconnect; T4 moment input power relay
s j1
closed, derided capacitors to be entered
c dj discharge off, by-pass procedure terminates.
The finger that puts into operation of the employing redundancy sequencing control new module in described step (3), T5 moment digital signal processor closes output reference synchronizing bus-bar signaling switch
s j5
; The T6 moment provides disconnection input relay
s j1
signal; T7 moment input power relay
s j1
disconnect,
jthe input derided capacitors voltage rise of # new module; The T8 moment provide enable driving prime DC/DC converter and rear class straight-control signal of AC-AC converter,
j# new module exports and builds pressure thereupon; T9 moment digital signal processor just provides power output relay after detecting that output voltage reaches specified sine output
s j2
closed signal; T10 moment power output relay
s j2
closed, give average current bus signaling switch simultaneously
s j3
with input equalizing busbar signaling switch
s j4
signaling switch sends closure signal.
Beneficial effect of the present invention is as follows:
1, the mode of bypass is proposed to adopt to realize exiting of malfunctioning module in distributed I SOP inverter combined system.
2, provide accurate sequencing control figure, complete the hot plug of distributed I SOP inverter combined system, thus really achieve the lifting of reliability.
Accompanying drawing explanation
Fig. 1 is the theory diagram of ISOP inverter combined system of the present invention, wherein:
for system input voltage;
for system input current;
--
for input derided capacitors;
--
for input derided capacitors voltage steady-state value;
--
for the input current steady-state value of each inverter module;
--
for input derided capacitors electric current steady-state value;
--
for the output current of each inverter module;
for system output voltage;
for system output current;
s 11--
s n1
for input power relay,
s j1 be
jthe input power relay of # module;
r 1 --
r n for current-limiting resistance;
s 12--
s n2
for power output relay,
s j2 be
jthe power output relay of # module.Above-mentioned
jspan be 1,2 ...,
n.
Fig. 2 is single module main circuit diagram of the present invention, wherein:
for
j# module input voltage;
for
j# module input current;
q 1-
q 4for the switching tube of prime DC/DC converter;
t j for preceding stage high frequency isolating transformer;
l dcj for
j# module prime filter inductance;
c dcj for
j# module prime filter capacitor;
v dcj for
j# module prime output voltage;
d 1-
d 4for the diode of straight-straight inverter rectification circuit of prime; S
1-S
4for rear class straight-hand over the switching tube of inverter;
l fj for
j# module rear class filter inductance;
c fj for
j# module rear class filter capacitor;
i lfj for
j# module rear class filter inductance electric current;
i cfj for
j# module rear class filter capacitor electric current;
for module output current.Above-mentioned
jspan be 1,2 ...,
n.
Fig. 3 is distributed structure/architecture and the control block diagram of ISOP inverter combined system of the present invention, wherein
s 13--
s n3
for average current bus signaling switch;
s 14--
s n4
for input equalizing busbar signaling switch;
s 15--
s n5
for output voltage reference synchronization bus signaling switch;
for output voltage reference data;
-
for input derided capacitors instantaneous voltage;
for input voltage attenuation coefficient;
for input grading ring proportional controller;
--
for the DC error signal of each inverter module;
for output voltage closed loop downsampling factor;
for output voltage proportional and integral controller;
for input voltage Setting signal;
--
for the output signal of each inverter module output voltage regulator;
for average inductor current Setting signal, it is also the initial inductance given value of current signal of each inverter module;
-
for each module output voltage regulator output signal with
average signal;
-
for each inverter module multiplier output signal;
--
for the inductive current reference signal of each inverter module;
--
for the inverse cascade outputting inductance current instantaneous value of each inverter module;
--
for each inverter module inverse cascade output capacitance current instantaneous value and
;
--
for each module output voltage sampled signal and
;
for current inner loop downsampling factor;
for system load impedance, sC
ffor the admittance of filter capacitor.Above-mentioned
jspan be 1,2 ...,
n.
Fig. 4 is the inside composition of module of the present invention, wherein
s j1
for
j# module input power relay,
s j2
for power output relay,
s j3
for average current bus signaling switch,
s j4
for input equalizing busbar signaling switch,
s j5
for output voltage reference synchronization bus signaling switch,
r j for
j# module current-limiting resistance,
for
j# module input derided capacitors.
The sequential chart that Fig. 5 (a) is bypass, Fig. 5 (b) is the sequential chart dropped into.
Embodiment
Below in conjunction with accompanying drawing, the invention is described in further details.
Distributed I SOP inverter combined system of the present invention, comprises
nthe inverter module of individual input series connection, output-parallel,
nfor being more than or equal to the integer of 2.In system, each module is all be made up of full-bridge direct current converter and full-bridge inverter cascade, and the input of full-bridge direct current converter is as the input of inverter module, and the output of full-bridge inverter is as the output of inverter module.Each inverter module all has oneself independently control loop, communicates each other, achieve system modular and distributed AC servo system by means of only output voltage reference synchronization bus, input equalizing busbar with average current bus bar three buses.
The theory diagram of the input series and output parallel inverter system that the present invention relates to as shown in Figure 1, this system by
nindividual standardized module composition.When
jwhen # module breaks down and needs to be bypassed, disconnect power output relay
s j2
, closed input power relay
s j1
, now use resistance
r j restriction input derided capacitors
c dj discharging current.Drop at needs
jduring # new module, disconnect input power relay
s j1
, closed power output relay
s j2
.
As shown in Figure 2, because module each in ISOP inverter system is cascaded structure, therefore each module must select isolated form topology to the structure chart of each module of input series and output parallel inverter system that the present invention relates to.Here we adopt two-stage type structure as each module topology, and prime is the full-bridge DC-DC converter of high-frequency isolation, and rear class is full-bridge inverter.
Because the module of ISOP inverter combined system is connected at input, so when certain module breaks down, malfunctioning module directly can not excise from input by ISOP system as IPOP system.Here we use the mode of bypass to exit from system to realize malfunctioning module, and therefore each module has an input power relay
s j1
, current-limiting resistance
r j and power output relay
s j2
.When
j#when module breaks down and need log off, disconnect power output relay
s j2
, closed input power relay
s j1
, then the bypass of malfunctioning module can be realized, here resistance
r j for limiting input derided capacitors
c dj on discharging current; When
j#new module is ready, now disconnects input power relay
s j1
, closed power output relay
s j2
, then the online input of new module can be realized.
For realizing the by-pass procedure of malfunctioning module or new module drops into taking over seamlessly of process, need break-make (or block/enable) sequential for associated control signal to carry out appropriate design, these control signals comprise following 7 kinds: input-output power relay (
s j1
with
s j2
) make-and-break signal, bus signaling switch (average current bus signaling switch
s j3
, input equalizing busbar signaling switch
s j4
and output voltage reference synchronization bus signaling switch
s j5
) make-and-break signal, module prime DC/DC converter and rear class straight-hand over the driving blockade/enable signal of inverter.Here by digital signal processor, the sequential of these 7 signals is successively controlled in real time, thus make the hot plug process of ISOP inverter be able to steadily and complete smoothly.
As shown in Figure 3, each module adopts output-voltage loop, current inner loop double-loop control to the distributed AC servo system theory diagram of the ISOP inverter system that the present invention relates to, and wherein current inner loop adopts Hysteresis control.In addition, all press (IVS) for realizing input, each module has input grading ring.Therefore each module has it independently to input grading ring, output-voltage loop, current inner loop, this ensure that the independent equity of intermodule, really achieves modularization.Intermodule realizes information interaction by three buses, namely output voltage reference synchronization bus signal (
v ref synchronous bus), input equalizing busbar (IVS bus) and average current bus (
i ave bus).
v ref voltage reference synchronizing bus-bar signal provides benchmark for each module output voltage, and input equalizing busbar realizes IVS with the input grading ring of each module.The output-voltage loop of each module produces initial inductance current reference signal
i gj , namely this signal obtains average current bus signal after average
i ave , bus signal
i ave with each module initial inductance current reference signal
i gj inductive current benchmark average signal is obtained after average
i gj_ave , this signal produces the inductive current reference signal of each module reality through equiphase AM unit
i refj .
Achieve distributed AC servo system, realize the reliability that redundancy really can promote ISOP inverter combined system on this basis.Here signaling switch is introduced
s j3
,
s j4
with
s j5
(with reference to Fig. 3), together with power relay
s j1
with
s j2
(with reference to Fig. 1) realizes
jthe bypass of # module or input.
As shown in Figure 4, the signaling switch in figure is realized by analog switch CD4051 the inside modules composition of the ISOP inverter system that the present invention relates to, and its response speed is very fast, can think and not postpone.The operation of digital signal processor DSP TMS320F28027 monitoring module, runs hot plug program when fault-signal being detected.Digital signal processor except will input-output power relay be given, except bus signaling switch provides switch controlling signal, also to provide module prime DC/DC converter and rear class straight-hand over the driving blockade/enable signal of inverter.In order to make the hot plug process of ISOP inverter be able to steadily and complete smoothly, need accurate sequencing control.
The process of hot plug is controlled by digital signal processor, comprises two processes: bypass and input.
The hot plug sequencing control figure of the ISOP inverter system that the present invention relates to as shown in Figure 5, when digital signal processor detected in the T1 moment
j# module breaks down, then trigger bypass procedure.First our needs block the driving of prime, rear class immediately in the T1 moment.And then in the T2 moment, for avoiding malfunctioning module to the interference of system busbar, we will close three bus signaling switches in time, i.e. average current bus signaling switch
s j3
, input equalizing busbar signaling switch
s j4
and output voltage reference synchronization bus signaling switch
s j5
.The T2 moment provides closed input relay simultaneously
s j1
, disconnect output relay
s j2
control signal.Due to power relay operating lag, output relay in T3 moment action, input relay in T4 moment action, derided capacitors to be entered
c dj discharge off, system enters new stable state, then by-pass procedure terminates.
When new module is ready, digital signal processor then provides and drops into order.T5 moment first closed output reference synchronizing bus-bar signaling switch
s j5
, make newly to drop into module and bus reference synchronization.The T6 moment provides and disconnects input relay signal, and in the T7 moment, input relay disconnects,
jthe input derided capacitors voltage rise of # module.For accelerating the process dropped into a certain extent, we need the control signal providing enable driving when input capacitance voltage reaches certain voltage grade (lower than module nominal input voltage, i.e. the T8 moment).After having had drive singal, drop into module output and build pressure thereupon, digital signal processor is detecting the sine degree exported always, after detecting that at T9 moment digital signal processor output voltage reaches specified sine output, just provides the signal that output relay is closed.Because action postpones, output relay, finally at T10 time of day response, meanwhile provides closed two signaling switches
s j3
with
s j4
control signal.
The overall process of so far hot plug terminates, and system is normally run again.
Claims (5)
1. a redundancy control method for ISOP inverter combined system, is characterized in that, comprises the steps:
(1) when distributed I SOP inverter combined system is normally run, input power relay is disconnected
s j1
, closed power output relay
s j2
, closed three bus signaling switches, i.e. average current bus signaling switch
s j3
, input equalizing busbar signaling switch
s j4
and output voltage reference synchronization bus signaling switch
s j5
;
(2) when certain module of distributed I SOP inverter combined system breaks down, adopt the mode of bypass to realize exiting of this malfunctioning module, adopt redundancy sequential to realize the bypass of malfunctioning module by digital signal processor, namely when
jwhen # module breaks down and needs to be bypassed, disconnect power output relay
s j2
, closed input power relay
s j1
; Disconnect three bus signaling switches, i.e. average current bus signaling switch
s j3
, input equalizing busbar signaling switch
s j4
and output voltage reference synchronization bus signaling switch
s j5
; And block prime DC/DC converter and rear class straight-the switching tube drive singal of AC-AC converter;
(3) when
j# new module is ready, adopts putting into operation of redundancy sequencing control new module by digital signal processor, namely disconnects input power relay
s j1
, closed power output relay
s j2
; Closed bus signaling switch, namely closes
s j3
, input equalizing busbar signaling switch
s j4
and output voltage reference synchronization bus signaling switch
s j5
; And enable prime DC/DC converter and rear class straight-the switching tube drive singal of AC-AC converter.
2., based on a kind of described in claim 1 redundancy control method of ISOP inverter combined system, it is characterized in that:
The bypass that employing redundancy sequential in described step (2) realizes malfunctioning module refers to, when digital signal processor detected in the T1 moment
j# module breaks down, block immediately DC/DC converter and rear class straight-the switching tube drive singal of AC-AC converter; In the T2 moment, close three bus signaling switches, i.e. average current bus signaling switch
s j3
, input equalizing busbar signaling switch
s j4
and output voltage reference synchronization bus signaling switch
s j5
; Provide closed input relay simultaneously
s j1
, disconnect output relay
s j2
control signal; T3 moment power output relay
s j2
disconnect; T4 moment input power relay
s j1
closed, derided capacitors to be entered
c dj discharge off, by-pass procedure terminates.
3., based on a kind of described in claim 1 redundancy control method of ISOP inverter combined system, it is characterized in that:
The finger that puts into operation of the employing redundancy sequencing control new module in described step (3), T5 moment digital signal processor closes output reference synchronizing bus-bar signaling switch
s j5
; The T6 moment provides disconnection input relay
s j1
signal; T7 moment input power relay
s j1
disconnect,
jthe input derided capacitors voltage rise of # new module; The T8 moment provide enable driving prime DC/DC converter and rear class straight-control signal of AC-AC converter,
j# new module exports and builds pressure thereupon; T9 moment digital signal processor just provides power output relay after detecting that output voltage reaches specified sine output
s j2
closed signal; T10 moment power output relay
s j2
closed, give average current bus signaling switch simultaneously
s j3
with input equalizing busbar signaling switch
s j4
signaling switch sends closure signal.
4. based on a kind of described in claim 1 redundancy control method of ISOP inverter combined system, it is characterized in that, described digital signal processor adopts DSP TMS320F28027.
5. based on a kind of described in claim 1 redundancy control method of ISOP inverter combined system, it is characterized in that, described average current bus signaling switch
s j3
adopt analog switch CD4051.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510118342.8A CN104767414B (en) | 2015-03-18 | 2015-03-18 | A kind of redundancy control method of ISOP inverters combined system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510118342.8A CN104767414B (en) | 2015-03-18 | 2015-03-18 | A kind of redundancy control method of ISOP inverters combined system |
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| Publication Number | Publication Date |
|---|---|
| CN104767414A true CN104767414A (en) | 2015-07-08 |
| CN104767414B CN104767414B (en) | 2017-06-13 |
Family
ID=53649081
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|---|---|---|---|
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| CN105186883A (en) * | 2015-11-06 | 2015-12-23 | 国网上海市电力公司 | Control method of input-series output-parallel (ISOP) converter system |
| CN105720612A (en) * | 2016-04-05 | 2016-06-29 | 全球能源互联网研究院 | Power bypass-based inhibition method for commutation failure of high-voltage DC transmission |
| CN105958828A (en) * | 2016-04-22 | 2016-09-21 | 深圳启雅杰科技有限公司 | DC-DC converting circuit |
| CN107026580A (en) * | 2017-05-19 | 2017-08-08 | 南京理工大学 | A kind of output same-phase control method of ISOP distributed inverters system |
| CN108599607A (en) * | 2018-04-24 | 2018-09-28 | 西安理工大学 | A kind of principal and subordinate's redundancy control method of T-type three-level inverter parallel connection |
| JP7200398B1 (en) * | 2021-04-16 | 2023-01-06 | 東芝三菱電機産業システム株式会社 | Uninterruptible power system |
| WO2023082108A1 (en) * | 2021-11-10 | 2023-05-19 | 宁德时代新能源科技股份有限公司 | Electrical system and electrical device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105186883A (en) * | 2015-11-06 | 2015-12-23 | 国网上海市电力公司 | Control method of input-series output-parallel (ISOP) converter system |
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| CN108599607A (en) * | 2018-04-24 | 2018-09-28 | 西安理工大学 | A kind of principal and subordinate's redundancy control method of T-type three-level inverter parallel connection |
| JP7200398B1 (en) * | 2021-04-16 | 2023-01-06 | 東芝三菱電機産業システム株式会社 | Uninterruptible power system |
| WO2023082108A1 (en) * | 2021-11-10 | 2023-05-19 | 宁德时代新能源科技股份有限公司 | Electrical system and electrical device |
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|---|---|
| CN104767414B (en) | 2017-06-13 |
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