CN104765321B - A variety of field bus protocols in a compatible motion controller - Google Patents

A variety of field bus protocols in a compatible motion controller Download PDF

Info

Publication number
CN104765321B
CN104765321B CN201510030821.4A CN201510030821A CN104765321B CN 104765321 B CN104765321 B CN 104765321B CN 201510030821 A CN201510030821 A CN 201510030821A CN 104765321 B CN104765321 B CN 104765321B
Authority
CN
China
Prior art keywords
interface
core
arm
scheduling module
fpga
Prior art date
Application number
CN201510030821.4A
Other languages
Chinese (zh)
Other versions
CN104765321A (en
Inventor
宋宝
徐高峰
王湘来
陈永道
Original Assignee
镇江同舟螺旋桨有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 镇江同舟螺旋桨有限公司 filed Critical 镇江同舟螺旋桨有限公司
Priority to CN201510030821.4A priority Critical patent/CN104765321B/en
Publication of CN104765321A publication Critical patent/CN104765321A/en
Application granted granted Critical
Publication of CN104765321B publication Critical patent/CN104765321B/en

Links

Abstract

本发明提供的种兼容多种现场总线协议的运动控制器,包括ARM核心及接口、FPGA核心及接口和电源接口模块,ARM核心及接口、FPGA核心及接口和电源接口模块相连,ARM核心及接口包含核心调度模块ARM,FPGA核心及接口包含核心调度模块FPGA,采用核心调度模块ARM与核心调度模块FPGA嵌入式双核体系结构,适用于各种现场总线协议的统软硬件平台,可以兼容大部分的现场总线协议,具有很好的兼容性和广泛的适用性,可以同时连接多种不同协议的设备,提高了运动控制系统的柔性,采用FPGA处理实时链路层数据,提高了链路的稳定性和快速响应性。 The present invention provides various kinds of field bus protocol compatible with a motion controller, and an interface including ARM core, FPGA core, and interface and power interface module, and interface ARM core, FPGA core, and interface and power interface module is connected, and an interface ARM core ARM core comprising a scheduling module, and an interface FPGA core includes a core module FPGA scheduling, scheduling module using ARM core with the core embedded binuclear scheduling module FPGA architecture, the system software and hardware platform for a variety of field bus protocol, is compatible with most of the fieldbus protocol, has good compatibility and broad applicability, multiple devices can be simultaneously connected to different protocols, to improve the flexibility of the motion control system, a data link layer process using FPGA in real time to improve the stability of the link and fast response.

Description

一种兼容多种现场总线协议的运动控制器 A variety of field bus protocols in a compatible motion controller

技术领域 FIELD

[0001]本发明属于现场总线通信领域,具体涉及一种兼容多种现场总线协议的运动控制器。 [0001] The present invention belongs to the field bus communication field, more particularly, to a field bus protocol compatible motion controller.

背景技术 Background technique

[0002] 随着电子和通信技术的进步,工业自动化控制从传统的点对点的模拟量或者脉冲信号的控制方式逐渐发展成为现场总线的全数字化控制。 [0002] With the advancement of electronic and communication technology, industrial automation and control from the control pulse signal or an analog conventional point to point gradually developed into digital control fieldbus. 它将工业现场的控制、监测等设备通过串行信号的方式集成在一个通信网络中,可以构建现场总线控制系统,并且可以通过网络协议建立工业信息化控制管理层。 It industrial site control and monitoring equipment by way of serial signals are integrated in a communication network can be constructed fieldbus control system and may control the establishment of industrial management information through a network protocol. 运动控制器是现场总线控制的核心,其向上可以兼容以太网实现工业的网络化管理,向下可以兼容现场总线网络,因此,运动控制器所兼容的现场总线协议直接决定了整套控制系统的柔性以及适用性。 The motion controller is the core of the field bus control, which can be upwardly compatible with Ethernet network management industry, the field bus network downward compatible, therefore, the motion controller compatible with the Fieldbus protocol will determine the flexibility of the whole control system and applicability.

[0003] 现有的运动控制领域包含的现场总线协议种类繁多,而且基于各种协议开发设备的也层出不穷,但是到目前为止还没有一种能够兼容各种协议的统一软硬件控制平台,造成了各类设备的接口单一、资源浪费,难以实现运动控制器的广泛的兼容性和适用性问题。 [0003] Fieldbus existing motion control field contains a wide range and variety of protocols based on the development of equipment are endless, but so far there is not a unified software and hardware compatible with various protocols control platform, resulting in a single interface to various types of equipment, waste of resources, it is difficult to achieve a wide range of compatibility and applicability of the motion controller.

发明内容 SUMMARY

[0004] 本发明所要解决的问题是提供一种兼容多种现场总线协议的运动控制器,在分析各种现场总线协议类型的相似性和共通性的基础之上,发明了基于ARM+FPGA的嵌入式双核体系结构的运动控制器,并利用各种现场总线协议接口的规范,设计了各种现场总线基于双核体系的解决方案,实现了可以同时兼容多种现场总线协议的运动控制器,解决了目前总线式运动控制器支持协议类型比较单一,难以实现运动控制器的广泛的兼容性和适用性的问题。 [0004] The present invention solves the problem of providing a field bus protocol compatible with a variety of motion controller, based on the analysis of similarity and commonality of various types on the Fieldbus protocol, the invention is based on the ARM + FPGA embedded motion controller dual-core architecture, and using a variety of standardized fieldbus protocol interface, the design of a variety of fieldbus solutions based on dual-core systems, can achieve a variety of field bus protocols compatible with the motion controller, solve the current bus motion controller supports the protocol type is relatively simple, it is difficult to achieve a wide range of motion controller compatibility and applicability problems.

[0005] 为解决以上问题本发明所采用的方案: [0005] The proposal of the present invention is to solve the above problems:

[0006] 一种兼容多种现场总线协议的运动控制器,包括ARM核心及接口、FPGA核心及接口和电源接口模块,所述的ARM核心及接口、FPGA核心及接口和电源接口模块相连,所述的ARM 核心及接口包括运动控制的核心调度模块ARM、SD卡接口、VGA显示接口、Ethernet以太网接口、第一USB接口、第二USB接口、ARM调试串口和CAN总线接口,其功能模块直接由ARM核心及接口运行Linux操作系统进行控制和管理,所述的核心调度模块ARM与所述的如卡接口直接连接,所述的核心调度模块ARM通过一块WiY芯片与Ethernet以太网接口相连,所述的核心调度模块ARM直接与所述第一USB接口相连,所述的核心调度模块ARM直接与所述第二USB接口相连,所述的核心调度模块ARM通过一块RS232驱动芯片与所述ARM调试串口相连,所述的核心调度模块ARM通过一块CAN驱动芯片与所述CAN总线接口相连,所述的核心调 [0006] A motion controller is compatible with a variety of field bus protocol, and an interface including ARM core, FPGA core, and interface and power interface module, coupled to the interface and the ARM core, FPGA core, and interface and power interface module, the ARM core and motion control interfaces comprise said scheduling module ARM core, the SD card interface, VGA display interface, Ethernet Ethernet interface, USB interface, a first, a second USB port, serial port and debugging ARM CAN bus interface, which is a direct function module the card interface connects directly controlled and managed by the ARM core and the interface running the Linux operating system, said core and said scheduling module ARM, the ARM core scheduling module interfaces are connected via an Ethernet and Ethernet chip WiY, the said scheduling module ARM core is connected directly to the first USB interfaces, the second ARM core scheduling module is directly connected to the USB interface, the scheduling module ARM core by an RS232 driver chip and the ARM debug serial port, the scheduling module ARM core is connected with the CAN bus via a CAN driver chip interfaces, the adjusting core 模块ARM 通过一块VGA驱动芯片与VGA显示接口相连,所述的即以核心及接口包括核心调度模块FPGA、JTAG调式接口、第一工业以太网接口、第二工业以太网接口、光纤接口、RS485接口、 RS232接口,所述的FPGA核心及接口作为运动控制核心调度模块ARM的现场总线扩展部分, 通过FPGA核心及接口内部的IP核进行并行处理,对相应的接口进行数据链路层的处理,并通过GPMC总线与中断信号控制同运动控制核心调度模块ARM进行数据交互,所述的核心调度模块FPGA与所述的第一工业以太网口通过PHY芯片+隔离变压器相连,所述的核心调度模块FPGA与所述的第二工业以太网口通过PHY芯片+隔离变压器相连,所述的核心调度模块FPGA与所述的光纤接口通过PHY芯片+光电转换器相连,所述的核心调度模块FPGA与所述的RS485接口通过RS485驱动芯片相连,所述的核心调度模块FPGA与所述的RS232 ARM interface module is connected by a VGA display with VGA driver chip, i.e., the core and the interface comprises a core dispatch module FPGA, JTAG debug interface, the first industrial Ethernet interfaces, the second industrial Ethernet interface, optical interface, RS485 interfaces , RS232 interface, said interface is used as an FPGA core and control core motion field bus extension portion of ARM scheduling module, parallel processing by the FPGA IP core internal and core interface, the corresponding interface processes the data link layer, and GPMC interrupt signal via the control bus with the motion control module ARM core dispatch to exchange data, the scheduling module FPGA core with said first port is connected to the industrial Ethernet + PHY chip by an isolation transformer, the scheduling module FPGA core + PHY chip by an isolating transformer connected to the second industrial Ethernet port, the scheduling module FPGA core of the optical interface through the PHY chip + photoelectric conversion device connected to said core and said scheduling module FPGA RS485 interface are connected via RS485 driver chip, said core and said scheduling module FPGA RS232 口通过RS232驱动芯片相连,所述的核心调度模块FPGA与所述的JTAG调式接口直接相连,所述的核心调度模块FPGA通过GPMC总线协议以及中断信号等控制与核心调度模块ARM相连。 Connected via port RS232 driver chip, the scheduling module FPGA core is directly connected to the JTAG debug interface, the scheduling module FPGA core GPMC connected via the interrupt bus protocol and control signals with the core scheduling module ARM.

[0007]上述的一种兼容多种现场总线协议的运动控制器,其中,所述的核心调度模块FPGA作为现场总线可扩展模块,其功能是处理从现场总线网络中所识别的信号,进行数据链路层的处理,包括与ARM的数据接口部分、数据链路层和物理层链路选择,所述的物理层链路选择包括网口自动拓扑识别转发模块和串口链路选择模块,用来分别处理网口数据和串口数据,所述的数据链路层包括网口数据链路层数据处理和串口数据链路层数据处理, 用来分别处理网口的数据链路层和串口的数据链路层,所述的与ARM的数据接口部分包括网口数据帧缓冲区和串口数据帧缓冲区,用来分别缓存发送和接受的网口通信帧和串口通信帧,并与核心调度模块ARM进行数据交互。 [0007] The one field bus protocol compatible with a variety motion controller, wherein said scheduling module FPGA core extensible field bus module, whose function is to process the identified signal from the fieldbus network, data link layer processing, ARM portion comprises a data interface, the data link layer and the physical layer link selection, the physical layer includes a link selection automatic topology network port forwarding module identification and serial link selection module, for each data processing network and the serial data port, the data link layer comprising a data link layer network interface data link layer processing and data processing serial data, respectively, for processing data and serial data link layer link of network interface path layer, and the data interface comprises a network interface portion ARM frame buffer data and the serial data frame buffer, buffers for respectively receiving and transmitting network port and serial communication frame communication frame, and scheduling module ARM core Data interaction.

[0008]本方案的有益效果: [0008] Advantageous effects of the program:

[0009] 1. ARM核心及接口上运行Linux操作系统,应用程序根据人机交互所产生的控制需求和执行器的实时状态反馈计算出给执行器的指令数据,通过执行器所兼容的现场总线协议接口通过通信电缆传输给各个运动执行器,同时也通过通信电缆将反馈的数据和状态给应用程序,实现运控,支持程序运行显示VGA接口以及调试口,同时还支持USB设备、串口设备等的外围扩展。 Running the Linux operating system, the application calculates the feedback data to the instruction execution unit in accordance with the state of the real-time interactive control requirements generated and the actuator, the actuator is compatible through the fieldbus [0009] 1. ARM core and Interface protocol interface to the respective actuator which is a communication transmitted by cable, also via the communication cable feedback data and status to the application, to achieve transport control, supports a program run VGA interface and debug port, and also support USB devices, serial devices, etc. the external expansion.

[0010] 2. FPGA核心及接口内部支持现有的大部分总线的物理层接口,包括串口通信和网口通信物理层,通过不同通信协议物理层的驱动芯片进行通信电平转换实现不同的总线接口,如RS4S5接口和RS232接口等,对于同一个总线接口,也可以通过改变现场总线通信应用层来实现不同种类现场总线通信的协议,例如,工业以太网接口可以构造相同的网口链路层,通过不同的应用层协议驱动可以实现EtherCAT、Powerlink等众多基于实时工业以太网物理层的协议,因此,通过软件重构的方法可以充分实现运动控制器的柔性以及广泛的适用性,另外,由于基于FPGA的现场总线IP核扩展模块可以充分利用FPGA并行操作的优势, 可以在一个控制周期内同时控制多个现场总线协议网络,可以真正实现同时兼容多个现场总线网络协议。 [0010] 2. FPGA core support and the internal interface most of the existing physical layer interface bus, the network comprising a serial communication port and communication physical layer communication driver chip level conversion by different physical layer protocols implement different communications bus interfaces, such as interfaces and RS4S5 RS232 interface, a bus interface for the same, or different kinds of protocols can be implemented by changing the fieldbus communication fieldbus communication application layer, e.g., the industrial Ethernet interface may be configured the same link layer network port driving can be realized EtherCAT, Powerlink based real-time, and many other industrial Ethernet physical layer protocols through different application layer protocols, therefore, can be fully realized flexibility and broad applicability of the motion controller software reconstituted by the method, additionally, since the FPGA-based fieldbus IP core extension module may take advantage of FPGA operating in parallel, can simultaneously control a plurality of field bus protocols in a network control period, you can realize a plurality of fieldbus compatible network protocols.

[0011 ] 3 •核心调度模块FPGA通过GPMC总线协议以及中断信号等控制与核心调度模块ARM相连,实现现场总线扩展IP核与ARM的数据交互和控制功能,用户可以根据不同的控制需要,选择不同的运动控制器中现场总线接口进行控制系统的连线,然后通过应用程序调用不同协议的驱动接口对相应的总线进行操作,从而实现根据需要构建的不同的现场总线网络。 [0011] 3 • core dispatch module FPGA via GPMC bus protocol and the interrupt signals controlling the core scheduling module ARM, realizes the data exchange and control local bus extension IP core with ARM, the user according to different control requirement, in field bus interface connection of the control system motion controller, and then invoke different applications protocol operating the drive interface corresponding bus, in order to achieve different field bus network constructed in accordance with needs.

[0012] 4•采用核心调度模块ARM与核心调度模块FPGA嵌入式双核体系结构,适用于各种现场总线协议的统一软硬件平台,可以兼容大部分的现场总线协议,具有很好的兼容性和广泛的适用性,可以同时连接多种不同协议的设备,提高了运动控制系统的柔性,采用FPGA 处理实时链路层数据,提高了链路的稳定性和快速响应性。 [0012] 4 • scheduling module using ARM core and core scheduling module FPGA embedded dual-core architecture for a variety of fieldbus protocols unified hardware and software platform, is compatible with most fieldbus protocol, and has good compatibility broad applicability, multiple devices can be simultaneously connected to different protocols, to improve the flexibility of the motion control system, a data link layer using FPGA real-time processing, improve the stability and quick response of the link.

附图说明_ BRIEF DESCRIPTION _

[0013] 图1是本发明的运动控制器的总体结构示意图。 [0013] FIG. 1 is an overall schematic view of the motion controller of the present invention.

[0014] 图2是本发明各个功能模块之间的连接示意图。 [0014] FIG. 2 is a schematic view of the connection between the various functional modules of the present invention.

[0015] 图3是本发明FPGA模块和外设的具体信号流向示意图。 [0015] FIG. 3 is a signal flow diagram showing a specific FPGA module of the present invention and peripherals.

[0016] 图4是本发明FPGA模块内部的结构示意图。 [0016] FIG. 4 is a schematic diagram of the FPGA internal module of the present invention.

[0017] 图5是本发明ARM模块和外设的具体信号流向示意图。 [0017] FIG. 5 is a schematic diagram of the present invention, particularly the flow of the ARM signal and peripherals.

[0018] 图6是本发明ARM模块内部的结构示意图。 [0018] FIG. 6 is a schematic diagram of the internal module of the present invention ARM.

具体实施方式 Detailed ways

[0019] 如图所示,一种兼容多种现场总线协议的运动控制器,包括ARM核心及接口1、FPGA 核心及接口2和电源接口模块3,所述的ARM核心及接口1、FPGA核心及接口2和电源接口模块3相连,所述的ARM核心及接口1包括运动控制的核心调度模块ARM11、SD卡接口16、VGA显示接口17、Ethernet 以太网接口12、第一USB 接口131、第二USB 接口132、ARM 调试串口14 和CAN 总线接口15,其功能模块直接由ARM核心及接口1运行Linux操作系统进行控制和管理,所述的核心调度模块ARM11与所述的SD卡接口16直接连接,所述的核心调度模块ARM11通过一块PHY芯片121与Ethernet以太网接口12相连,所述的核心调度模块ARM11直接与所述的第一USB接口131相连,所述的核心调度模块ARM11直接与所述的第二USB接口132相连,所述的核心调度模块ARM11通过一块RS232驱动芯片141与所述ARM调试串口14相连,所述的核心调度模块ARM11 [0019] As shown, the motion controller in a compatible more field bus protocol, and an interface including ARM core 1, FPGA core 2 and power interface, and an interface module 3, and the interface of the ARM core 1, FPGA core and an interface 2 and a power module 3 is connected to the interface, the interface and the ARM core 1 comprises a core dispatch motion control module ARM11, SD card interface 16, VGA display interface 17, Ethernet Ethernet interface 12, a first USB interface 131, two USB interface 132, the serial debug ARM CAN bus interface 14 and 15, which function modules and managed directly by the control and interface ARM core 1 Linux operating system to run said scheduling module ARM11 core and the SD card interface 16 is directly connecting said core ARM11 by scheduling module 121 and an Ethernet PHY chip 12 is connected to the Ethernet interface, the scheduling module ARM11 core is directly connected to the first USB interface 131, the scheduling module ARM11 core directly coupled to said second USB interface 132, the scheduling module ARM11 core connected via a RS232 driver 141 and the ARM chip debug port 14, the scheduling module core ARM11 通过一块CAN驱动芯片151与所述的CAN总线接口15相连,所述的核心调度模块ARM11通过一块VGA驱动芯片171与VGA显示接口17相连,所述的FPGA核心及接口2包括核心调度模块FPGA2UJTAG调式接口26、第一工业以太网接口221、第二工业以太网接口222、光纤接口23、RS485接口24、RS232接口25,所述的FPGA核心及接口2作为运动控制核心调度模块ARM11的现场总线扩展部分,通过FPGA核心及接口2内部的IP核进行并行处理,对相应的接口进行数据链路层的处理,并通过GPMC总线与中断信号控制同运动控制核心调度模块ARM11进行数据交互,所述的核心调度模块FPGA21与所述的第一工业以太网口221通过PHY 芯片+隔离变压器211相连,所述的核心调度模块FPGA21与所述的第二工业以太网口222通过PHY芯片+隔离变压器211相连,所述的核心调度模块FPGAM与所述的光纤接口23通过PHY 芯片+光电转换器231相连,所 CAN chip 151 by a driving of the CAN bus interface 15 is connected to the interface 17 is connected to the core by a scheduling module ARM11 VGA display driver chip 171 and the VGA, the FPGA core includes a core 2 and a scheduling module interfaces modal FPGA2UJTAG interface 26, a first industrial Ethernet interface 221, Ethernet interface 222 industrial second optical interface 23, RS485 interfaces 24, RS232 interface 25, and an interface of the FPGA core 2 as a motion control module ARM11 core dispatch fieldbus extension part, parallel processing by the FPGA IP core internal and core interface 2, the corresponding interface processes the data link layer, and an interrupt signal via the control bus GPMC with motion control ARM11 core dispatch module to exchange data, the FPGA21 core dispatch module with said first port 221,211 industrial Ethernet PHY chip + is connected via an isolation transformer, the scheduling module is connected to the core 211 through the PHY chip + isolation transformer and said second FPGA21 industrial Ethernet port 222 the scheduling module FPGAM core of the optical interface through the PHY chip connected 23231 + photoelectric conversion, the 的核心调度模块FPGA21与所述的RS4S5接口24通过RS485驱动芯片241相连,所述的核心调度模块FPGA21与所述的RS232接口25通过RS232驱动芯片251 相连,所述的核心调度模块FPGA21与所述的JTAG调式接口26直接相连,所述的核心调度模块FPGA21通过GPMC总线协议以及中断信号等控制与核心调度模块ARM11相连。 The core of the scheduling module FPGA21 RS4S5 RS485 interface 24 are connected through the driver chip 241, the scheduling module FPGA21 core and the RS232 interface 25 via RS232 driver chip 251 is connected to the core with the scheduling module FPGA21 the JTAG debug interface 26 is directly connected to the core by the scheduling module FPGA21 GPMC bus protocol control signals and interrupt scheduling module is connected to the core ARM11.

[0020] 上述的一种兼容多种现场总线协议的运动控制器,其中,所述的核心调度模块FPGA21作为现场总线可扩展模块,其功能是处理从现场总线网络中所识别的信号,进行数据链路层的处理,包括与ARM的数据接口部分211、数据链路层212和物理层链路选择213,所述的物理层链路213选择包括网口自动拓扑识别转发模块2131和串口链路选择模块2132, 用来分别处理网口数据和串口数据,所述的数据链路层212包括网口数据链路层数据处理21以和串口数据链路层数据处理2122,用来分别处理网口的数据链路层和串口的数据链路层,所述的与ARM的数据接口部分211包括网口数据帧缓冲区2111和串口数据帧缓冲区2112,用来分别缓存发送和接受的网口通信帧和串口通信帧,并与核心调度模块ARM进行数据交互。 [0020] The one field bus protocol compatible with a variety motion controller, wherein said scheduling module core can FPGA21 field bus extension module, whose function is to process the identified signal from the fieldbus network, data link layer processing, including data and ARM interface section 211, a data link layer 212 and physical layer link selection 213, the physical layer includes a link 213 to select automatic topology network port forwarding identification module 2131 and serial links selection module 2132, for respectively processing network data and serial data port, the data link layer 212 includes a network interface data link layer 21 of data processing and data processing serial data link layer 2122, respectively, for processing network port serial data link layer and the data link layer, the data ARM interface portion 211 includes a network interface 2111 and a data frame buffer serial data frame buffer 2112, transmit and receive buffers for each port communication network frame and the frame serial communication, and exchanging data with the core dispatch module ARM.

[0021] ARM核心及接口1运行Linux操作系统进行控制和管理,Ethernet以太网口12可以全双工同时接受和发送以太网数据帧,经过PHY芯片121的处理后进入核心调度模块ARM11 的系统底层TCP/IP驱动程序,使之能够兼容以太网,第一USB接口m、第二USB接口132与核心调度模块ARM11通过差分信号直接进行数据的交互,ARM调试串口14经过RS232驱动芯片141转换成为ARM兼容TTL电平的232信号供ARM调试或者作为现场总线通信口用,CAN总线接口15通过CAN驱动芯片151与核心调度模块ARM11进行交互,可以集成运动控制器的CAN总线接口。 [0021] ARM core and 1 Linux operating system interface operates to control and manage, Ethernet full-duplex Ethernet port 12 can simultaneously receive and transmit Ethernet data frame, the PHY chip 121 after treatment of the underlying kernel scheduling module into the system of ARM11 TCP / IP driver, so that it can be compatible with Ethernet, USB interface, the first m, USB interface 132 and the second core ARM11 scheduling module interacts directly by the differential data signal, ARM debug RS232 serial port 14 through the driver chip 141 is converted into ARM TTL compatible signal 232 for debugging ARM or with a fieldbus communication port, cAN bus via the cAN interface 15 interacts with the core driver chip 151 scheduling module ARM11, cAN bus interface may be integrated motion controller.

[0022] 核心调度模块FPGA21可以在外围扩充网口、串口和光口等接口接受第一工业以太网接口221、第二工业以太网接口222中的数据,同时也可以向网络中发送数据,实现全双工的网络通信,网络中的电信号经过隔离变压器2212转换为差分信号与PHY芯片Mil相连,用于屏蔽网络中的干扰,提高通信的稳定性,PHY芯片2211通过RMII或者Mil方式与核心调度模块FPGA21进行数据交换;光纤接口23同样工作在全双工模式下,光电转换器2312对光纤通信网络中的光信号进行处理,转换为差分电信号供PHY芯片2311处理,通过RMII或者MII 方式与核心调度模块FPGA21进行数据交换;RS485接口24,RS485网络中的通信信号通过RS485驱动芯片241转换核心调度模块FPGAW所兼容TTL232信号进行数据的交换;RS232接口25,RS232网络中的通信信号通过RS232驱动芯片251转换核心调度模块FPGA21所兼容TTL 232信号进行数据 [0022] The scheduling module FPGA21 core network can be expanded in the peripheral port, serial port and other optical interfaces industrial Ethernet interface 221 receives the first, second industrial Ethernet interface data 222 can also send data to the network, to achieve full duplex network communication, electrical network via isolation transformer 2212 into a differential signal and Mil PHY chip connected to the network for interference shielding, increase the stability of communication, the PHY chip 2211 by way RMII core dispatch or Mil data exchange module FPGA21; optical interface 23 the same work in full duplex mode, the photoelectric conversion signal 2312 pairs of optical fiber communications network is processed, converted into differential electrical signals PHY chip 2311 for processing, by way of MII and RMII or core dispatch module FPGA21 data exchange; RS485 interface 24, a communication signal RS485 network TTL232 signal compatible data exchange conversion core dispatch module FPGAW through the RS485 driver chip 241; RS232 interface 25, a communication signal RS232 network via RS232 driver conversion chip core dispatch module 251 FPGA21 TTL 232 is compatible for data signals 的交换。 Exchange.

[0023] 核心调度模块ARM11内部的结构包括ARM运动控制程序111、应用程序接口层112和设备驱动层113,ARM运动控制程序111为控制系统的核心,将应用程序接口层112的有效控制数据和反馈数据根据控制需求进行相应的计算迭代处理,以实现整个现场总线运动控制系统的功能实现,另外,应用程序的控制指令可以通过人机交互接口进行输入;应用程序接口层112实现了各类设备驱动的一个总的集成的接口库,其中包括了运动控制器所支持的所有现场总线接口操作的驱动接口,向上为应用程序提供操作入口,向下直接可以搭建应用程序与硬件设备通信的桥梁,包含三类,一类是Linux支持的驱动,有Ethernet应用层接口1121和CAN应用层接口1122,另一类是基于IP核网口扩展的设备驱动,包括EtherCAT应用程序接口1123、Powerlink应用层接口1124和其余工业以太网的应用层接口1125,用户 Internal structure [0023] core dispatch module ARM11 including ARM motion control program 111, application program interface layer 112 and the device driver layer 113, ARM motion control program 111 as the core control system will effectively control the application program interface layer 112 and feedback data according to the respective control requirements iterative calculation processing to realize the functions fieldbus entire motion control system to achieve additional control command application can be input via the man-machine interactive interface; application program interface layer 112 implements various types of equipment driving a total integrated interface library, which includes motion drive interface controller supports all fieldbus interface operation, the operation up to provide an inlet for the application can directly down to bridge applications to communicate with a hardware device, consists of three types, one is a driving support Linux, Ethernet application layer interface with a CAN application layer interface 1121 and 1122, the other is based on the IP core network interface extension device drivers, application program interface comprising EtherCAT 1123, Powerlink application layer interface 1124 industrial Ethernet and the rest of the application layer interface 1125, the user 可以根据自身需要来扩充不同种类的现场总线协议网口的应用层接口,最后一类是基于IP和串口扩展的设备驱动,包括Modbus应用层接口1126和各类串口通信协议应用层接口1127,用户可以根据自身需要来扩充不同种类的现场总线协议串口的应用层接口;设备驱动层113 包括Linux支持的驱动1131、IP核FPGA网口扩展驱动1132和IP核串口扩展驱动1133,其主要功能是运行驱动程序,直接驱动板级的硬件设备,进行硬件设备的驱动任务。 The application layer interface itself may need to expand the different types of Fieldbus network port, the last one is based on IP and serial device driver extensions, Modbus application layer interface 1126 includes various types of serial communication protocols and application layer interface 1127, the user can serial application layer interfaces according to their need to expand the different kinds of field bus protocols; 113 including Linux supported drive 1131 device driver layer, IP core FPGA network port extended drive 1132 and IP cores serial extended drive 1133, whose main function is to run driver direct drive board level hardware device, hardware device driving task.

[0024] ARM核心及接口上运行Linux操作系统,应用程序根据人机交互所产生的控制需求和执行器的实时状态反馈计算出给执行器的指令数据,通过执行器所兼容的现场总线协议接口通过通信电缆传输给各个运动执行器,同时也通过通信电缆将反馈的数据和状态给应用程序,实现运控,支持程序运行显示VGA接口以及调试口,同时还支持USB设备、串口设备等的外围扩展。 Running the Linux operating system, the application calculates the feedback data to the instruction execution unit in accordance with the state of the real-time interactive control requirements generated and the actuator, the actuator is compatible by the Fieldbus protocol interface [0024] interfaces and the ARM core peripheral to the respective actuator which is a communication transmitted by cable, also via the communication cable feedback data and status to the application, to achieve transport control, supports a program run VGA interface and debug port, and also support USB devices, serial devices, etc. extension.

[0025] FPGA核心及接口内部支持现有的大部分总线的物理层接口,包括串口通信和网口通信物理层,通过不同通信协议物理层的驱动芯片进行通信电平转换实现不同的总线接口,如RS485接口和RS232接口等,对于同一个总线接口,也可以通过改变现场总线通信应用层来实现不同种类现场总线通信的协议,例如,工业以太网接口可以构造相同的网口链路层,通过不同的应用层协议驱动可以实现EtherCAT、Powerlink等众多基于实时工业以太网物理层的协议,因此,通过软件重构的方法可以充分实现运动控制器的柔性以及广泛的适用性,另外,由于基于FPGA的现场总线IP核扩展模块可以充分利用FPGA并行操作的优势,可以在一个控制周期内同时控制多个现场总线协议网络,可以真正实现同时兼容多个现场总线网络协议。 [0025] FPGA core support and the internal interface most of the existing physical layer interface bus, and a serial communication network comprising a physical layer of communication ports for communicating different level conversion implemented by the bus interface driver chip different physical layer communication protocol, interfaces such as RS485 and RS232 interface, a bus interface for the same, or different kinds of protocols can be implemented by changing the fieldbus communication fieldbus communication application layer, e.g., the industrial Ethernet interface may be configured the same link layer network port, by different application layer protocol driver may be implemented EtherCAT, Powerlink based real-time, and many other industrial Ethernet physical layer protocol, therefore, can be fully realized flexibility and broad applicability of the motion controller software reconstituted by the method, additionally, since the FPGA based fieldbus IP core extension module may take advantage of FPGA operating in parallel, can simultaneously control a plurality of field bus protocols in a network control period, you can realize a plurality of fieldbus compatible network protocols.

[0026] 核心调度模块FPGA通过GPMC总线协议以及中断信号控制与核心调度模块ARM相连,实现现场总线扩展IP核与ARM的数据交互和控制功能,用户可以根据不同的控制需要, 选择不同的运动控制器中现场总线接口进行控制系统的连线,然后通过应用程序调用不同协议的驱动接口对相应的总线进行操作,从而实现根据需要构建的不同的现场总线网络。 [0026] The core dispatch module FPGA via GPMC bus protocol and the interrupt signal control are connected with the core scheduling module ARM, Fieldbus extended IP core and ARM data exchange and control functions, users according to different control needs, to select a different motion control field bus interface unit to connect the control system, and then invoke different applications protocol operating the drive interface corresponding bus, in order to achieve different field bus network constructed in accordance with needs. [0027]采用核心调度模块ARM与核心调度模块FPGA嵌入式双核体系结构,适用于各种现场总线协议的统一软硬件平台,可以兼容大部分的现场总线协议,具有很好的兼容性和广泛的适用性,可以同时连接多种不同协议的设备,提高了运动控制系统的柔性,采用FPGA处理实时链路层数据,提高了链路的稳定性和快速响应性。 [0027] The scheduling module ARM core and core scheduling module FPGA embedded dual-core architecture for a variety of fieldbus protocols unified hardware and software platform, is compatible with most fieldbus protocol, and has good compatibility with a wide range of applicability, multiple devices can be simultaneously connected to different protocols, to improve the flexibility of the motion control system, a data link layer using FPGA real-time processing, improve the stability and quick response of the link.

[0028]仅为本发明较佳的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明掲露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围内。 [0028] DETAILED only preferred embodiments of the invention, but the scope of the present invention is not limited thereto, any skilled in the art in the art within the technical scope of the present invention kei exposed, readily conceivable variations or Alternatively, it shall fall within the protection scope of the present invention. 因此,本发明的保护范围应该以权利要求书的保护范围为准。 Accordingly, the scope of the present invention, the scope of the claims should prevail.

Claims (2)

  1. L 一种兼容多种现场总线协议的运动控制器,包括ARM核心及接口)FPGA核及接口和电源接口模块,其特征为,所述的ARM核心及接口、FPGA核心及接口和电源g 口模块相连,所述的ARM核心及接口包括运动控制的核心调度模块ARM、SD卡接口、VGA显示接口;_Ethernet 以太网接口、第一USB接口、第二USB接口、ARM调试串口和CAN总线接口,其功能模块直接由ARM核心及接口运行Linux操作系统进行控制和管理,所述的核心调度模块ARM与所述的如卡接口直接连接,所述的核心调度模块ARM通过一块PHY芯片与Ethernet以太网接口相连, 所述的核心调度模块ARM直接与所述第一US峨口相连,所述的核心调度模块歷直接与所述第二USB接口相连,所述的核心调度模块ARM通过一块RS232驱动芯片与所述ARM调试串口相连,所述的核心调度模块ARM通过一块CAN驱动芯片与所述CAN总线接口相连,所述的核 L more Fieldbus protocol in a compatible motion controller, and an interface including ARM core) and the FPGA core interface and power interface module, wherein said ARM core and interface, FPGA core, and interface and power interface module g connected to the ARM core and motion control interface comprises a scheduling module ARM core, the SD card interface, VGA display interface; _Ethernet Ethernet interface, USB interface, a first, a second USB port, serial port and debugging ARM CAN bus interface control and management functional module directly by the ARM core and the interface running the Linux operating system, the scheduling module ARM core and as a direct connection to the card interface, said scheduling module ARM core by an Ethernet PHY chip and an Ethernet interface connected to the core of the first scheduling module ARM US Ekou directly connected to said core calendar scheduling module is directly connected to the second USB interface, the scheduling module ARM core driven by an RS232 chip and the ARM debug serial port, the scheduling module ARM core is connected with the CAN bus via a CAN driver chip interfaces, the core 调度模块ARM通过一块VGA驱动芯片与VGA显示接口相连,所述的FPGA核心及接口包括核心调度模块FPGA、JTAG调式接口、第一工业以太网接口、第二工业以太网接口、光纤接口、 RS485接口、RS232接口,所述的FPGA核心及接口作为运动控制核心调度模块ARM的现场总线扩展部分,通过FPGA核心及接口内部的IP核进行并行处理,对相应的接口进行数据链路层的处理,并通过GPMC总线与中断信号控制同运动控制核心调度模块ARM进行数据交互,所述的核心调度模块FPGA与所述的第一工业以太网口通过PHY芯片+隔离变压器相连,所述的核心调度模块FPGA与所述的第二工业以太网口通过PHY芯片+隔离变压器相连,所述的核心调度模块FPGA与所述的光纤接口通过PHY芯片+光电转换器相连,所述的核心调度模块FPGA与所述的RS485接口通过RS485驱动芯片相连,所述的核心调度模块FPGA与所述的RSM2 Scheduling module interface connected by ARM display and a VGA driver VGA chip, FPGA core and said interface includes a scheduling module FPGA core, the JTAG debug interface, the first industrial Ethernet interfaces, the second industrial Ethernet interface, optical interface, RS485 interfaces , RS232 interface, said interface is used as an FPGA core and control core motion field bus extension portion of ARM scheduling module, parallel processing by the FPGA IP core internal and core interface, the corresponding interface processes the data link layer, and GPMC interrupt signal via the control bus with the motion control module ARM core dispatch to exchange data, the scheduling module FPGA core with said first port is connected to the industrial Ethernet + PHY chip by an isolation transformer, the scheduling module FPGA core + PHY chip by an isolating transformer connected to the second industrial Ethernet port, the scheduling module FPGA core of the optical interface through the PHY chip + photoelectric conversion device connected to said core and said scheduling module FPGA RS485 interface are connected via RS485 driver chip, said core and said scheduling module FPGA RSM2 接口通过RS232驱动芯片相连,所述的核心调度模块FPGA与所述的JTAG调式接口直接相连,所述的核心调度模块FPGA通过GPMC总线协议以及中断信号控制与核心调度模块ARM相连。 Interfaces RS232 driver chip connected to the FPGA core scheduling module directly connected to the JTAG debug interface, the scheduling module FPGA core GPMC via bus protocol interrupt signal and a control module connected to the core dispatch ARM.
  2. 2.如权利要求1所述的一种兼容多种现场总线协议的运动控制器,其特征为,所述的核心调度模块FPGA作为现场总线可扩展模块,其功能是处理从现场总线网络中所识别的信号,进行数据链路层的处理,包括与ARM的数据接口部分、数据链路层和物理层链路选择,所述的物理层链路选择包括网口自动拓扑识别转发模块和串口链路选择模块,用来分别处理网口数据和串口数据,所述的数据链路层包括网口数据链路层数据处理和串口数据链路层数据处理,用来分别处理网口的数据链路层和串口的数据链路层,所述的与ARM的数据接口部分包括网口数据帧缓冲区和串口数据帧缓冲区,用来分别缓存发送和接受的网口通信帧和串口通信帧,并与核心调度模块ARM进行数据交互。 2. one of the claim 1, the motion controller is compatible with a variety of field bus protocol, wherein said scheduling module FPGA core extensible field bus module, which is a processing function from the fieldbus network identification signal, the data link layer processes, including ARM data interface part, the data link layer and physical layer link selection, the physical layer includes a link selection automatic topology network port forwarding module identification and serial chain path selection module, respectively, for processing network data and serial data port, said network interface comprises a data link layer of data processing and data link layer serial data link layer of data processing, processing for each network interface data link layer and serial data link layer, and the data interface comprises a network interface portion ARM frame buffer data and the serial data frame buffer, buffers for respectively receiving and transmitting network port and serial communication frame communication frame, and data exchange with the core scheduling module ARM.
CN201510030821.4A 2015-01-22 2015-01-22 A variety of field bus protocols in a compatible motion controller CN104765321B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510030821.4A CN104765321B (en) 2015-01-22 2015-01-22 A variety of field bus protocols in a compatible motion controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510030821.4A CN104765321B (en) 2015-01-22 2015-01-22 A variety of field bus protocols in a compatible motion controller

Publications (2)

Publication Number Publication Date
CN104765321A CN104765321A (en) 2015-07-08
CN104765321B true CN104765321B (en) 2018-09-28

Family

ID=53647230

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510030821.4A CN104765321B (en) 2015-01-22 2015-01-22 A variety of field bus protocols in a compatible motion controller

Country Status (1)

Country Link
CN (1) CN104765321B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105099845A (en) * 2015-09-16 2015-11-25 成都比善科技开发有限公司 Communication management machine
CN105426331A (en) * 2015-11-13 2016-03-23 上海斐讯数据通信技术有限公司 PHY chip management system and PHY chip management method
CN105955204A (en) * 2016-05-13 2016-09-21 镇江同舟螺旋桨有限公司 High-compatibility multifunctional various field bus protocol motion control system
CN106200561B (en) * 2016-07-31 2019-03-29 上海新时达电气股份有限公司 Coder controller and configuration method
CN106357617A (en) * 2016-08-28 2017-01-25 上海新时达电气股份有限公司 Adaptive method, device, elevator communication system of the communication protocol
CN107124405A (en) * 2017-04-21 2017-09-01 杭州知物数据科技有限公司 Method and device for realizing industrial field bus protocol conversion based on FPGA

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004078904A (en) * 1995-05-30 2004-03-11 Roy G Biv Corp Motion Control System
CN101013312A (en) * 2007-01-15 2007-08-08 大连光洋科技工程有限公司 Private chip for implementing bus controller function in ring bus numerical control system
CN101261512A (en) * 2008-04-17 2008-09-10 上海交通大学 Embedded movement control card based on ARM
CN203133571U (en) * 2013-05-10 2013-08-14 成都鑫科瑞数控技术有限公司 Dual-core processing control circuit of numerical control system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6275741B1 (en) * 1998-10-05 2001-08-14 Husky Injection Molding Systems Ltd. Integrated control platform for injection molding system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004078904A (en) * 1995-05-30 2004-03-11 Roy G Biv Corp Motion Control System
CN101013312A (en) * 2007-01-15 2007-08-08 大连光洋科技工程有限公司 Private chip for implementing bus controller function in ring bus numerical control system
CN101261512A (en) * 2008-04-17 2008-09-10 上海交通大学 Embedded movement control card based on ARM
CN203133571U (en) * 2013-05-10 2013-08-14 成都鑫科瑞数控技术有限公司 Dual-core processing control circuit of numerical control system

Also Published As

Publication number Publication date
CN104765321A (en) 2015-07-08

Similar Documents

Publication Publication Date Title
CN100461140C (en) Method and system for supporting multiple graphic processing unit
US9047222B2 (en) Unified multi-transport medium connector architecture
CN101310266A (en) Modular avionics system of an aircraft
CN100514233C (en) EPA on-site controller based on SOPC
CN101626351A (en) Multiprotocol data acquisition gateway
CN101345629B (en) Double on-site bus interface converter
CN102281254B (en) Design system and method of server serial port
CN1901569B (en) Remote regulating method and system
CN102170430B (en) Multi-port multi-network protocol converter
CN1335558A (en) Combined simulation system across platforms
CN102710478B (en) Integration slave node device of Profibus-DP (profibus-data processing) and Modbus
US20080155124A1 (en) Apparatus, system, and method for remote multi-user kvm switching
CN103631190A (en) Monitoring system based on EtherCAT network
CN103248526B (en) External monitoring and management implemented with a communication device, method
CN102594627A (en) Gigabit Ethernet field bus communication device based on FPGA
CN101789171B (en) Method and system for changing data transfer bus
CN103023739B (en) EtherCAT communication management device for dual-core based power electronic equipment
CN203734702U (en) General data collection module based on OPC UA
CN101179576A (en) Multi-protocol industry Ethernet adapter
CN1801020A (en) Embedded field bus protocol interface device and implementation method
CN101986613B (en) All-purpose asynchronous serial communication controller
CN103425106A (en) Linux-based Ethercat maser/slave station control system and method
CN1964363B (en) Having a plurality of bus interface can be configured to i / o modules
CN103248537B (en) Based fc-ae-1553 hybrid avionics system tester
Ruimei et al. Design of ARM-based embedded Ethernet interface

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
GR01