CN104753535A

CN104753535A - High-speed and low-power-consumption circuit based on Pipeline-ADC (analog-to-digital converter)

Info

Publication number: CN104753535A
Application number: CN201310742059.3A
Authority: CN
Inventors: 张震
Original assignee: Nanjing University of Science and Technology Changshu Research Institute Co Ltd
Current assignee: Nanjing University of Science and Technology Changshu Research Institute Co Ltd
Priority date: 2013-12-30
Filing date: 2013-12-30
Publication date: 2015-07-01

Abstract

The invention relates to integrated circuit technologies, and particularly relates to a high-speed and low-power-consumption circuit based on a Pipeline-ADC (analog-to-digital converter). The circuit comprises a sampling capacitor Cs, a load capacitor CL connected between the output and the ground and an OTA operational amplifier, and is characterized in that input signals Vinp, input signals Vinn and the sampling capacitor Cs are connected to the input end of the OTA operation amplifier, a sampling control time sequence Phi 1 is used for controlling sampling for the input signals, a sampling control time sequence Phi 1' and fixed voltage Vcm are used for ensuring the integrity of sampled signals, and a signal maintaining time sequence Phi 2 is connected to the input end and the output end of the OTA operational amplifier and used for completing a sampling/maintaining function. According to the invention, the sampling/maintaining circuit is a capacitor turning type, has the advantages of more stable signal input common-mode range, ability of using a small capacitor and chip area, low power consumption and good stability in the maintaining stage, and is suitable for being applied to the front end of the Pipeline-ADC.

Description

Based on the high-speed low-power-consumption circuit of Pipeline-ADC

Technical field

The present invention relates to integrated circuit technique, particularly based on the high-speed low-power-consumption circuit of Pipeline-ADC.

Background technology

In recent years, along with the fast development of Digital Signal Processing, Digital Signal Processing is widely used in every field, therefore more and more higher requirement be it is also proposed to the performance of the analog to digital converter (Analog-to-Digital Converter, ADC) as bridge between analog-and digital-system.Low voltage, high-speed ADC is a key component in the application of many electronic devices.Due to other structures, such as two step flash structures or interpolation type structure are all difficult to provide low harmonics distortion under high incoming frequency, and therefore pipeline organization also becomes a structure relatively commonly used in the ADC application of high-speed low-power-consumption.

High accuracy and the high speed of sample/hold circuit are most important to realizing high performance analog to digital converter.In the application, it can reduce the dynamic error of analog-to-digital conversion device, comprises the error that non-linear input capacitance, comparator and clock delay etc. cause.But the continuous reduction of supply voltage and device minimum dimension, brings difficulty to design high speed, high resolution low-power consumption sample/hold circuit.

Summary of the invention

Based on above consideration, the present invention, on the basis analyzing electric capacity flip type sample/hold circuit principle, proposes a kind of low-voltage based on Pipeline-ADC for production line analog-digital converter front end, low-power consumption, high-speed sample and hold.

The technical solution realizing the object of the invention is:

Based on the high-speed low-power-consumption circuit of Pipeline-ADC, comprise: sampling capacitance Cs, be connected to the load capacitance CL between output and ground and OTA amplifier, input signal Vinp, input signal Vinn and sampling capacitance Cs are connected to OTA amplifier input, controlling of sampling sequential Φ 1 is for the sampling of control inputs signal, controlling of sampling sequential Φ 1 ' and output common mode voltage Vcm is for ensureing the integrality of sampled signal, signal keeps sequential Φ 2 to be connected to OTA amplifier input and output two ends, for completing sampling/maintenance function.

Further, when controlling of sampling sequential Φ 1 is high level, circuit enters sampling configuration, and the voltage on sampling capacitance Cs is followed consistent with the voltage on input signal.

Further, when signal keeps sequential Φ 2 to start, under sampling capacitance Cs, OTA amplifier output linked by step, and output voltage equals controlling of sampling sequential Φ 1 ' and to sample the input voltage obtained.

Further, described sampling capacitance Cs is 0.9pF, and described load capacitance comprises next stage sampling capacitance and sampling keeps output parasitic capacitance Cp to be 1.2pF.

The invention has the advantages that: sample/hold circuit is electric capacity flip type, there is signal input common-mode range more stablize, use less electric capacity, chip area and low-power consumption, the good advantage of maintenance stage stability, be suitable in production line analog-digital converter front end.

Accompanying drawing explanation

Fig. 1 is electric capacity flip type sampling hold circuit;

Fig. 2 is folded common source and common grid secondary amplifier;

Fig. 3 is continuous time common-mode feedback;

Fig. 4 is switched-capacitor CMFB circuit.

Embodiment

Below in conjunction with accompanying drawing, the invention will be further described.

Fig. 1 is electric capacity flip type sample/hold circuit of the present invention.Wherein, Φ 1, Φ 1 ' are controlling of sampling sequential, and Φ 2 is signal maintenance sequential.When controlling of sampling sequential Φ 1 is high level, circuit enters sampling configuration, and the voltage now on sampling capacitance Cs is followed consistent with the voltage on input signal.At the end of controlling of sampling sequential Φ 1, controlling of sampling sequential Φ 1 ' turns off the switch be connected with OTA amplifier in advance, makes sampling capacitance Cs no longer include DC channel; When controlling of sampling sequential Φ 1 turns off, do not have charge injection and clock feedthrough affects sampled voltage.When signal keeps sequential Φ 2 to start, under sampling capacitance Cs, OTA amplifier output linked by step, and output voltage equals controlling of sampling sequential Φ 1 ' and sample the input voltage obtained, thus completes sampling maintenance function.

According to the consideration limited thermal noise and the coupling of switch conducting resistance, sampling capacitance Cs is 0.9pF, and load capacitance comprises next stage sampling capacitance and sampling keeps the parasitic capacitance Cp exported to be 1.2pF.Common mode feedback circuit is requisite circuit in fully differential OTA, continuous time common-mode feedback and switched-capacitor CMFB be two kinds of conventional modes, they are applied to the first order and the second level of two stage OTA respectively, carry out stable output common mode voltage.

OTA amplifier is very important at the Static and dynamic aspect of performance of sampling hold circuit.Two stage amplifer has large DC current gain, the feature of large voltage swing, but needs compensation to make circuit stability.

Fig. 2 adopts fully differential folded common source and common grid as the fully differential two stage amplifer of the first order, and have the miller-compensated structure of cascade, this structure does not produce zero point and GBW is higher.This structure is double-width grinding both-end export structure, and its basic thought is applied to by cascade metal-oxide-semiconductor to export differential centering.Wherein M3, M4, M5, M6, M7, M8, M9, M10 pipe composition first order telescoping structure, for the requirement providing high-gain to meet design, M0 is tail current pipe, M11, M12, M13, M14 pipe is second level common source configuration, promotes the output voltage swing of amplifier, wherein Vcmfb1, Vcmfb2, Vcmfb3 are the voltage bias provided by biasing circuit, C3, C4 is compensating circuit, and C1, C2 are load capacitance.

Signal to be divided into large-signal settling time and small-signal settling time settling time, and determined by parameter SR and GBW respectively, rule of thumb large-signal is generally 1/3 ~ 1/4 of the sampling time settling time.When sample frequency is 150MHz, single-ended peak-to-peak voltage is 0.5V, by obtaining switching rate is 600V/us.The feedback factor of flip type sampling hold circuit is (1)

In formula (1), Cs is sampling capacitance, and Cp is the parasitic capacitance of OTA amplifier input, .The output voltage of sampling hold circuit is

(2)

(2) in formula, A is OTA amplifier open-loop gain, because finite gain is limited, causes gain error to be , in order to keep precision, bounded errors should be less than 1/2LSB:

(3)

(4)

N is the resolution of ADC, and formula (4) can determine the open-loop gain of OTA amplifier.Can be determined the settling time of small-signal by the bandwidth of OTA amplifier, for the OTA amplifier of closed loop, setting up error is

(5)

for the unity gain bandwidth of OTA amplifier, setting up error should be less than 1/2LSB:

(6)

Unity gain bandwidth is:

(7)

Consider sufficient surplus, gain should be greater than 72dB, and unity gain bandwidth should be greater than 640MHz.

Common mode feedback circuit is requisite circuit in fully differential OTA amplifier.Fig. 3 is continuous time common-mode feedback, and Fig. 4 is switched-capacitor CMFB circuit, and as shown in Figure 3, m19, m20 are pmos pipe, and m15, m16, m17, m18 are nmos pipe.The grid leak of m19 and m20 is connected; M15 and m18 grid end is connected to fixed voltage V4 and Vcm; The source and drain of m16 and m17 is connected.As shown in Figure 4, wherein Vout+ and Vout-is respectively OTA amplifier output voltage, Vcm equals to need stable output common mode voltage, Vbias is the electric capacity initial voltage that biasing circuit produces, Vcmfb2 for this reason common-mode feedback produce regulation voltage, φ 1 and φ 2 is two-phase non-overlapping clock, and C2 is induction output voltage electric capacity, and C1 is the switching capacity being used as resistance.Continuous time common-mode feedback fast response time, but output voltage swing is restricted, and power consumption is large, is applied in the first order and carrys out stable output common mode voltage.Switched-capacitor CMFB circuit output voltage swing is unrestricted, and low in energy consumption, but needs periodic refresh, is applied in the second level to improve output voltage swing.

Claims

1. based on the high-speed low-power-consumption circuit of Pipeline-ADC, it is characterized in that: comprise sampling capacitance Cs, be connected to the load capacitance CL between output and ground and OTA amplifier, input signal Vinp, input signal Vinn and sampling capacitance Cs are connected to OTA amplifier input, controlling of sampling sequential Φ 1 is for the sampling of control inputs signal, controlling of sampling sequential Φ 1 ' and fixed voltage Vcm is for ensureing the integrality of sampled signal, signal keeps sequential Φ 2 to be connected to OTA amplifier input and output two ends, for completing sampling/maintenance function.

2. the high-speed low-power-consumption circuit based on Pipeline-ADC according to claim 1, is characterized in that: when controlling of sampling sequential Φ 1 is for high level, circuit enters sampling configuration, and the voltage on sampling capacitance Cs is followed consistent with the voltage on input signal.

3. the high-speed low-power-consumption circuit based on Pipeline-ADC according to claim 1, it is characterized in that: when signal keeps sequential Φ 2 to start, under sampling capacitance Cs, OTA amplifier output linked by step, and output voltage equals controlling of sampling sequential Φ 1 ' and to sample the input voltage obtained.

4. the high-speed low-power-consumption circuit based on Pipeline-ADC according to claim 1, is characterized in that: described sampling capacitance Cs is 0.9pF, and described load capacitance comprises next stage sampling capacitance and sampling keeps output parasitic capacitance Cp to be 1.2pF.