CN104753345A - Technology for improving transient response of BUCK circuit - Google Patents
Technology for improving transient response of BUCK circuit Download PDFInfo
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- CN104753345A CN104753345A CN201310745599.7A CN201310745599A CN104753345A CN 104753345 A CN104753345 A CN 104753345A CN 201310745599 A CN201310745599 A CN 201310745599A CN 104753345 A CN104753345 A CN 104753345A
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Abstract
The invention discloses an improved error amplifier for a BUCK step-down conversion circuit. The error amplifier is capable of effectively relieving the degree of a differential pair MOS tube in a linear region when the input voltage is changed rapidly due to transient jump, the time for returning to a saturation region is greatly shortened (even eliminated), the conversion speed rate of the error amplifier is effectively improved, and accordingly the transient response performance of the whole BUCK circuit system is improved.
Description
Technical field
The application's relate generally to error amplifier, particularly for improving the modified model error amplifier of BUCK circuit transient response.
Background technology
At present, Switching Power Supply obtains apply more and more widely because it has the features such as input range is wide, efficiency is high, volume is little, and its stability and high efficiency directly affects the service behaviour of electronic product.Switching Power Supply of a great variety, wherein, in switching mode dc-dc main circuit, modally opens up that to mend structure be exactly BUCK type, BOOST type and BUCK-BOOST type.BUCK type circuit and buck change-over circuit, be mainly used in the decompression transformation of DC-to-DC (DC-DC), is usually applicable to low-voltage, high-current application.
In the current widely used BUCK type circuit of institute, error amplifier is used for, to carrying out Difference Calculation between the output voltage feedback signal Vfb of DC-DC converter and reference signal Vref and error signal being amplified, producing control voltage with the duty ratio of adjustment System.Error amplifier is the important component part of Voltage Feedback control loop, has conclusive effect to the stability of DC switch transformation system, adjustment of load and response speed.
Usually, be exactly the compensation policy by suitable Select Error amplifier to the compensation of whole loop, the frequency response of alignment error amplifier realizes.Object corrects whole closed-loop system, to provide suitable bandwidth, makes closed-loop system steady operation and have good dynamic response.
Study for a long period of time and show, the transient response of switching rate (also claiming Slew Rate) on the BUCK circuit of entirety of error amplifier has conclusive impact.The switching rate improving error amplifier effectively can strengthen the transient response performance of BUCK circuit, makes the transient process of whole system shorter.
According to prior art, a kind of conventional error amplifier is generally made up of two-stage calculation amplifier.The first order is Differential Input, and the second level is that cascade exports.This structure can provide very high amplifier gain.
Find through research, under emergency case, when the voltage feedback signal Vfb that error amplifier inputs and reference signal Vref transient state saltus step occur and sharply reduce, the metal-oxide-semiconductor of first order Differential Input can fall saturation region and enter linear work district.Need to expend the regular hour owing to coming back to saturation region, this significantly reduces the switching rate of error amplifier, thus adversely have impact on the transient response of BUCK circuit.
Therefore, current pole needs a kind of technology effectively can resisted input voltage saltus step, effectively improve the switching rate of error amplifier.
Summary of the invention
For the defect of above prior art, the object of the application is at least to provide a kind of error amplifier for BUCK circuit with the switching rate of improvement.
According to the first aspect of the application, propose a kind of error amplifier for BUCK circuit, it is characterized in that, comprise: the first PMOS (M1) and the second PMOS (M2), described first PMOS and the second PMOS common source, and being coupled to current source, the grid of described first PMOS connects the first voltage input, and the grid of described second PMOS connects the second voltage input; 9th PMOS (M9) and the tenth PMOS (M10), and the 3rd NMOS tube (M3) and the 4th NMOS tube (M4), the source electrode of described 9th PMOS and the tenth PMOS is all coupled to voltage Vdd, the drain coupled of described 9th PMOS is to the source electrode of the 7th PMOS (M7), the drain coupled of described tenth PMOS is to the source electrode of the 8th PMOS (M8), the drain coupled of described 7th PMOS is to the drain electrode of the 3rd NMOS tube, and the drain coupled of described 8th PMOS is to the drain electrode of the 4th NMOS tube; 5th NMOS tube (M5) and the 6th NMOS tube (M6), the source electrode of described 5th NMOS tube and the 6th NMOS tube is all coupled to earth terminal (GND), the drain coupled of described 5th NMOS tube is to the source electrode of described 3rd NMOS tube, and the drain coupled of described 6th NMOS tube is to the source electrode of described 4th NMOS tube; Wherein, the drain electrode of described first PMOS is coupled to the drain electrode of the 5th NMOS tube and the source electrode of the 3rd NMOS tube further, and the drain electrode of described second PMOS is coupled to the drain electrode of the 6th NMOS tube M6 and the source electrode of the 4th NMOS tube further; The drain electrode of described first PMOS is connected to the grid of the 5th NMOS tube and the 6th NMOS tube further via the first current control device, and the drain electrode of the second PMOS is connected to the grid of the 5th NMOS tube and the 6th NMOS tube further via the second current control device.
According to the second aspect of the application, first voltage input is reference voltage input Vref, second voltage input is feedback voltage input Vfb, and the switching node of the drain electrode of described 4th NMOS tube and the drain electrode of described 8th PMOS provides the output voltage Vout of described error amplifier.
According to the third aspect of the application, the grid of described 9th PMOS and described tenth PMOS meets external bias voltage Vb3; The grid of described 7th PMOS and described 8th PMOS meets external bias voltage Vb2; The grid of described 5th NMOS tube and the 6th NMOS tube meets external bias voltage Vb4; The grid of described 3rd PMOS and the 4th PMOS meets external bias voltage Vb1, and described external bias voltage Vb3 is coupled to the switching node of the drain electrode of described 3rd NMOS tube M3 and the drain electrode of described 7th PMOS further.
According to the fourth aspect of the application, described first current control device is the 11 PMOS (M11), and described second current control device is the 12 PMOS (M12).
According to the 5th aspect of the application, the drain coupled of described first PMOS is to the source electrode of the 11 PMOS, grid and the drain electrode of described 11 PMOS are all coupled to the grid of the 5th NMOS tube and the 6th NMOS tube together with external bias voltage Vb4, the drain coupled of described second PMOS to the source electrode of described 12 PMOS, the grid of described 12 PMOS and drain all be coupled to the grid of the 5th NMOS tube and the 6th NMOS tube together with external bias voltage Vb4.
According to the 6th aspect of the application, described first current control device and described second current control device are diodes.
According to the 7th aspect of the application, described first current control device and described second current control device are diodes.
According to the eighth aspect of the application, propose a kind of BUCK decompression converting circuit, it is characterized in that, comprise: the first PMOS (Mp0), second PMOS (Mp1), 3rd NMOS tube (Mn1), the source electrode of described first PMOS is coupled to voltage Vdd by the first resistance (R1), the drain coupled of described first PMOS is to the drain electrode of the 3rd NMOS tube, the sources connected in parallel of described second PMOS is coupled to voltage Vdd, the drain electrode of described second PMOS is coupled in parallel to the drain electrode of the 3rd NMOS tube, the source ground (GND) of described 3rd NMOS tube; The inductor (L) be connected in series and capacitor (C).One end of described inductor and one end of capacitor are connected in series, the other end of described inductor is coupled to the drain electrode of described 3rd NMOS tube, the other end ground connection of described capacitor, namely the series connection node between described inductor and capacitor forms the output end vo ut of described BUCK decompression converting circuit; The second resistance (R2) be connected in series and the 3rd resistance (R3), be coupled between described output end vo ut and ground connection, from the series connection node output feedack voltage signal Vfb between described second resistance and the 3rd resistance to feed back to the inverting input (-) of error amplifier (110); Error amplifier (110), described error amplifier receives reference voltage signal Vref at its non-inverting input (+), at its output, error amplification signal is supplied to the non-inverting input (+) of comparator (108); Clock generator (112), clock signal is to current sense and compensating module (102) and PWM device (104); Described current sense and compensating module are connected across the first resistance (R1) two ends, and for sensing output current and affording redress, the output of described current sense and compensating module is coupled to the reverse input end (+) of described comparator (108); Comparator (108), the error amplification signal from error amplifier received from the compensating signal input noninverting with it of current sense and compensating module that its inverting input receives is compared, compare result signal is exported to the first input of described PWM device; PWM device (104), receives the clock signal from clock generator in the input of its clock, and receives the comparison signal from comparator in its first input, also receives the detection signal at zero point from zero detector in its second input.First export at it and produce suitable the first pwm control signal grid to described first PMOS and described second PMOS, and second export at it and produce the grid that the 2nd suitable PMW controls signal to described 3rd NMOS tube; Wherein, described error amplifier (110) is the error amplifier as described in claim 1-7.
According to the 9th aspect of the application, further cross-over connection diode (D) between the source electrode and drain electrode of described 3rd PMOS.
Modified model error amplifier according to the above-mentioned various aspects of the application sharply changes (such as in input voltage generation transient state saltus step, reduce) time, effectively can alleviate the degree that differential pair metal-oxide-semiconductor enters linear zone, greatly shorten the time that (even eliminating) revert to saturation region, effectively improve the switching rate of error amplifier, and then improve the transient response performance of whole BUCK Circuits System.
In this article, term " connection " or " coupling " are defined as the connection between two main bodys, but not necessarily directly connect, and also can comprise the indirect annexation realized by other intermediate nodes or equipment.
Term used herein " comprises ", " having ", " comprising " and " containing " be open connection verb.Therefore, one method or device " comprise ", " having ", " comprising " or " containing " one or more steps or assembly refer to: the method or device have those one or more steps or assemblies, but be not that only there is those one or more steps or assemblies, can comprise other one or more steps NM or assembly herein yet.
Should be appreciated that the generality of more than the application describes and the following detailed description is all exemplary and explanat, and be intended to for the application as claimed in claim provides further explanation.
Accompanying drawing is sketched
Comprising accompanying drawing is further understand the application for providing, and they are included and form a application's part, and accompanying drawing shows the embodiment of the application, and plays the effect explaining the application's principle together with this specification.After the embodiment to specific non-limiting the application by reference to the accompanying drawings and below having read, other features of the application and advantage will become apparent.Wherein:
Fig. 1 is the block diagram of the BUCK circuit of an aspect according to the application;
Fig. 2 is the concrete structure schematic diagram of the modified model error amplifier for BUCK circuit of an aspect according to the application.
Embodiment
With reference to non-limiting example that is shown in the drawings and that describe in detail in the following description, multiple technical characteristic and the Advantageous details of the application is more completely described.Further, the description that have ignored known original material, treatment technology, assembly and equipment is below described, in order to avoid unnecessarily obscure the technical essential of the application.But it will be understood by those skilled in the art that, when describing the embodiment of the application hereinafter, only as explanation, unrestriced mode provides for description and particular example.
In the case of any possible, in all of the figs the identical mark of use is represented same or analogous part.In addition, although the term used in the application selects from public term, but some terms mentioned in present specification may be that applicant selects by his or her judgement, its detailed meanings illustrates in the relevant portion of description herein.In addition, require not only to pass through used actual terms, but the meaning that also will be contained by each term understands the application.
Fig. 1 show according to the embodiment of the application the block diagram of BUCK type DC-DC circuit.As shown in Figure 1, this BUCK circuit 100 mainly comprises input Vdd, feedback loop, clock generator 112, current sense and compensating module 102, error amplifier 110, comparator 108, PWM device 104, zero detector 106, first PMOS Mp0, the second PMOS Mp1, the 3rd NMOS tube Mn1.
The source electrode of the first PMOS Mp0 is coupled to Vdd by resistance R1, and drain coupled is to the logic of the 3rd NMOS tube Mn1.The source electrode of the second PMOS Mp1 is coupled in parallel to Vdd equally, and drain electrode is coupled in parallel to the drain electrode of the 3rd NMOS tube Mn1.The source ground (GND) of the 3rd NMOS tube Mn1.
Output network comprises the inductor L and capacitor C that are connected in series.One end (being not attached to that end of inductance C) of inductor LX is coupled to the drain electrode of the 3rd NMOS tube Mn1, and one end of the other end and capacitor C is connected in series, the other end ground connection of capacitor C.Namely series connection node between inductor LX and capacitor C forms the output end vo ut of BUCK circuit.
The BUCK circuit 100 of Fig. 1 also comprises feedback loop.This feedback loop comprises and is connected in series resistance R2 and R3.The coupled one end of resistance R2 is to output end vo ut, and the other end is connected in series in resistance R3, the other end ground connection of resistance R3.The voltage divider that resistance R2 and R3 is formed, by the information of voltage dividing potential drop at BUCK circuit output end Vout place, from the series connection node output feedack voltage signal Vfb between resistance R2 and R3, feeds back to the inverting input (-) of error amplifier 110.Error amplifier 110 receives reference voltage signal Vref at non-inverting input (+).Error amplification signal is supplied to the non-inverting input (+) of comparator 108 by error amplifier 110 at its output.
Clock generator 112 clock signal is to current sense and compensating module 102 and PWM device 104.Current sense and compensating module 102 are connected across resistance R1 two ends, for sensing output current and affording redress.The output of current sense and compensating module 102 is coupled to the reverse input end (+) of comparator 108.
The error amplification signal from error amplifier 110 received from the compensating signal input noninverting with it of current sense and compensating module 102 that its inverting input receives compares by comparator 108, compare result signal is exported to the first input of PWM device 104.
This PWM device 104 receives the clock signal from clock generator 112 in the input of its clock, and receives the comparison signal from comparator 108 in its first input, also receives the detection signal at zero point from zero detector 106 in its second input.PWM device 104 produces the grid of suitable pwm control signal to the first PMOS Mp0 and the second PMOS Mp1 in its first output; And produce in its second output the grid that suitable PMW controls signal to the 3rd NMOS tube Mn1.
Fig. 2 is the concrete structure schematic diagram of the modified model error amplifier for BUCK circuit of an aspect according to the application.This error amplifier 200 can be the error amplifier 110 in Fig. 1.
As shown in Figure 2, the differential input stage of error amplifier 200 is formed primarily of PMOS M1 and M2, M1 and M2 common source, and is coupled to current source ISS.The grid that the grid of PMOS M1 meets voltage input Vin1, PMOS M2 meets voltage input Vin2.In one embodiment, Vin1 meets reference voltage input Vref, Vin2 and meets feedback voltage input Vfb.
The cascade output stage of error amplifier 200 comprises NMOS tube M3 to M6 and PMOS M7 to M10.The source electrode of PMOS M9 and M10 is all coupled to voltage Vdd, and the drain coupled of M9 is to the source electrode of M7, and the drain coupled of M10 is to the source electrode of M8.The drain coupled of M7 is to the drain electrode of NMOS tube M3, and the drain coupled of M8 is to the drain electrode of NMOS tube M4.
The source electrode of NMOS tube M5 and M6 is all coupled to earth terminal GND, and the drain coupled of M5 is to the source electrode of M3, and the drain coupled of M6 is to the source electrode of M4.As above, the drain coupled of M3 is to the drain electrode of PMOS M7, and the drain coupled of M4 is to the drain electrode of PMOS M8.
The grid of M9 and M10 meets external bias voltage Vb3.The grid of M7 and M8 meets external bias voltage Vb2.The grid that the grid of M5 and M6 meets external bias voltage Vb4, M3 and M4 meets external bias voltage Vb1.
Wherein, further, the drain electrode of the PMOS M1 of differential input stage is coupled to the switching node X of the drain electrode of NMOS tube M5 and the source electrode of NMOS tube M3 further, and the drain electrode of PMOS M2 is coupled to the switching node Y of the drain electrode of NMOS tube M6 and the source electrode of NMOS tube M4 further.And external bias voltage Vb3 is coupled to the switching node A of the drain electrode of NMOS tube M3 and the drain electrode of PMOS M7 further.And the switching node B of the drain electrode of NMOS tube M4 and the drain electrode of PMOS M8 provides the output voltage Vout of error amplifier.
According at least one embodiment of the present invention, the drain electrode of PMOS M1 is connected to the grid of NMOS tube M5 and M6 further via a PMOS M11, and the drain electrode of PMOS M2 is connected to the grid of NMOS tube M5 and M6 further via a PMOS M12.Specifically, the drain coupled of PMOS M1 is to the source electrode of PMOS M11, and the grid of PMOS M11 and drain electrode are all coupled to the grid of NMOS tube M5 and M6 together with external bias voltage Vb4.Accordingly, the drain coupled of PMOS M2 is to the source electrode of PMOS M12, and the grid of PMOS M12 and drain electrode are all coupled to the grid of NMOS tube M5 and M6 together with external bias voltage Vb4.
The operation principle of the modified model error amplifier of Fig. 2 is: M11 and M12 works alone separately.For M11, when (or when becoming very low relative to the feedback voltage Vfb that Vin2 inputs) when saltus step becomes low especially occurs for reference voltage V ref that Vin1 inputs, M1 can fall and saturation region, enters linear zone.Now, the drain potential of M1 can raise, and makes M11 conducting.Two effects is brought: the first has directly dragged down the drain voltage of M1 after M11 conducting; It two is that the bias current of M5 is increased, and causes the voltage drop of switching node X place (i.e. the drain electrode of M1) further.Above double effects combines, and has significantly dragged down the drain voltage of M1, has prevented M1 penetration depth linear zone, make M1 get back to saturation region more quickly.The operating effect of M12 is also similar.
In another embodiment, PMOS M11 and M12 is replaced during other can being used.According at least one aspect of the present invention, various current control devices available in this area all can be used to alternative M11 and M12.Specifically, everyly can work as M1(or M2) drain potential can the current control device of grid (or conducting M2 and drain and the grid of M5 and M6) of forward conduction M1 and drain electrode and M5 and M6 can be used to herein when raising.In another embodiment, the diode of forward conduction is adopted.Also having in an embodiment, bipolar junction transistor BJT can be adopted.
Therefore, by M11 and M12, effectively can alleviate the degree that differential pair metal-oxide-semiconductor enters linear zone, greatly shorten the time that (even eliminating) revert to saturation region, effectively improve the switching rate of error amplifier, and then improve the transient response performance of whole BUCK Circuits System.
In view of present disclosure, all methods open and claimed in the application can be performed when not carrying out undo experimentation.Although describe the apparatus and method of the application according to the preferred embodiment, but those of ordinary skill in the art can be apparent, multiple modification can be applied to the step of the method described in the application and method or sequence of steps, and not deviate from concept, the spirit and scope of the application.In addition, amendment can be made to disclosed device, and get rid of the assembly that can describe from the application or substitute multiple assembly, and realize same or analogous result.To those of ordinary skill in the art apparent all these similar to substitute and amendment is regarded as within the spirit of the application limited by claims, scope and concept.
Claims (8)
1. for an error amplifier for BUCK circuit, it is characterized in that, comprising:
First PMOS (M1) and the second PMOS (M2), described first PMOS and the second PMOS common source, and being coupled to current source, the grid of described first PMOS connects the first voltage input, and the grid of described second PMOS connects the second voltage input;
9th PMOS (M9) and the tenth PMOS (M10), and the 3rd NMOS tube (M3) and the 4th NMOS tube (M4), the source electrode of described 9th PMOS and the tenth PMOS is all coupled to voltage Vdd, the drain coupled of described 9th PMOS is to the source electrode of the 7th PMOS (M7), the drain coupled of described tenth PMOS is to the source electrode of the 8th PMOS (M8), the drain coupled of described 7th PMOS is to the drain electrode of the 3rd NMOS tube, and the drain coupled of described 8th PMOS is to the drain electrode of the 4th NMOS tube;
5th NMOS tube (M5) and the 6th NMOS tube (M6), the source electrode of described 5th NMOS tube and the 6th NMOS tube is all coupled to earth terminal (GND), the drain coupled of described 5th NMOS tube is to the source electrode of described 3rd NMOS tube, and the drain coupled of described 6th NMOS tube is to the source electrode of described 4th NMOS tube;
Wherein, the drain electrode of described first PMOS is coupled to the drain electrode of the 5th NMOS tube and the source electrode of the 3rd NMOS tube further, and the drain electrode of described second PMOS is coupled to the drain electrode of the 6th NMOS tube M6 and the source electrode of the 4th NMOS tube further;
The drain electrode of described first PMOS is connected to the grid of the 5th NMOS tube and the 6th NMOS tube further via the first current control device, and the drain electrode of the second PMOS is connected to the grid of the 5th NMOS tube and the 6th NMOS tube further via the second current control device.
2. error amplifier as claimed in claim 1, it is characterized in that, first voltage input is reference voltage input Vref, second voltage input is feedback voltage input Vfb, and the switching node of the drain electrode of described 4th NMOS tube and the drain electrode of described 8th PMOS provides the output voltage Vout of described error amplifier.
3. error amplifier as claimed in claim 2, it is characterized in that, the grid of described 9th PMOS and described tenth PMOS meets external bias voltage Vb3; The grid of described 7th PMOS and described 8th PMOS meets external bias voltage Vb2; The grid of described 5th NMOS tube and the 6th NMOS tube meets external bias voltage Vb4; The grid of described 3rd PMOS and the 4th PMOS meets external bias voltage Vb1, and described external bias voltage Vb3 is coupled to the switching node of the drain electrode of described 3rd NMOS tube M3 and the drain electrode of described 7th PMOS further.
4. error amplifier as claimed in claim 3, it is characterized in that, described first current control device is the 11 PMOS (M11), and described second current control device is the 12 PMOS (M12).
5. error amplifier as claimed in claim 4, it is characterized in that, the drain coupled of described first PMOS is to the source electrode of the 11 PMOS, grid and the drain electrode of described 11 PMOS are all coupled to the grid of the 5th NMOS tube and the 6th NMOS tube together with external bias voltage Vb4, the drain coupled of described second PMOS to the source electrode of described 12 PMOS, the grid of described 12 PMOS and drain all be coupled to the grid of the 5th NMOS tube and the 6th NMOS tube together with external bias voltage Vb4.
6. error amplifier as claimed in claim 3, it is characterized in that, described first current control device and described second current control device are diodes.
7. error amplifier as claimed in claim 3, it is characterized in that, described first current control device and described second current control device are diodes.
8. a BUCK decompression converting circuit, is characterized in that, comprising:
First PMOS (Mp0), second PMOS (Mp1), 3rd NMOS tube (Mn1), the source electrode of described first PMOS is coupled to voltage Vdd by the first resistance (R1), the drain coupled of described first PMOS is to the drain electrode of the 3rd NMOS tube, the sources connected in parallel of described second PMOS is coupled to voltage Vdd, and the drain electrode of described second PMOS is coupled in parallel to the drain electrode of the 3rd NMOS tube, the source ground (GND) of described 3rd NMOS tube;
The inductor (L) be connected in series and capacitor (C).One end of described inductor and one end of capacitor are connected in series, the other end of described inductor is coupled to the drain electrode of described 3rd NMOS tube, the other end ground connection of described capacitor, namely the series connection node between described inductor and capacitor forms the output end vo ut of described BUCK decompression converting circuit;
The second resistance (R2) be connected in series and the 3rd resistance (R3), be coupled between described output end vo ut and ground connection, from the series connection node output feedack voltage signal Vfb between described second resistance and the 3rd resistance to feed back to the inverting input (-) of error amplifier (110);
Error amplifier (110), described error amplifier receives reference voltage signal Vref at its non-inverting input (+), at its output, error amplification signal is supplied to the non-inverting input (+) of comparator (108);
Clock generator (112), clock signal is to current sense and compensating module (102) and PWM device (104);
Described current sense and compensating module are connected across the first resistance (R1) two ends, and for sensing output current and affording redress, the output of described current sense and compensating module is coupled to the reverse input end (+) of described comparator (108);
Comparator (108), the error amplification signal from error amplifier received from the compensating signal input noninverting with it of current sense and compensating module that its inverting input receives is compared, compare result signal is exported to the first input of described PWM device;
PWM device (104), receives the clock signal from clock generator in the input of its clock, and receives the comparison signal from comparator in its first input, also receives the detection signal at zero point from zero detector in its second input.First export at it and produce suitable the first pwm control signal grid to described first PMOS and described second PMOS, and second export at it and produce the grid that the 2nd suitable PMW controls signal to described 3rd NMOS tube;
Wherein, described error amplifier (110) is the error amplifier as described in claim 1-7.
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| CN109212350B (en) * | 2018-09-11 | 2020-07-31 | 电子科技大学 | Transient jump detection circuit for buck voltage converter |
| US10819213B2 (en) | 2018-11-06 | 2020-10-27 | Nxp Usa, Inc. | Zero-current detector for voltage converter |
| CN111245232A (en) * | 2020-02-12 | 2020-06-05 | 西安电子科技大学 | Quick-response synchronous buck DC-DC converter |
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