CN104752515B - A kind of thin film transistor (TFT) and its manufacturing method - Google Patents
A kind of thin film transistor (TFT) and its manufacturing method Download PDFInfo
- Publication number
- CN104752515B CN104752515B CN201310737218.0A CN201310737218A CN104752515B CN 104752515 B CN104752515 B CN 104752515B CN 201310737218 A CN201310737218 A CN 201310737218A CN 104752515 B CN104752515 B CN 104752515B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal oxide
- metal
- oxide semiconductor
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 125
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 124
- 229910052751 metal Inorganic materials 0.000 claims abstract description 97
- 239000002184 metal Substances 0.000 claims abstract description 96
- 239000004065 semiconductor Substances 0.000 claims abstract description 86
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 23
- 230000003647 oxidation Effects 0.000 claims abstract description 23
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 23
- 239000001301 oxygen Substances 0.000 claims abstract description 23
- 238000009413 insulation Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000000137 annealing Methods 0.000 claims description 21
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 229910052725 zinc Inorganic materials 0.000 claims description 8
- 229910052742 iron Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 2
- 239000010931 gold Substances 0.000 claims 2
- 229910052737 gold Inorganic materials 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000002360 preparation method Methods 0.000 abstract description 7
- -1 oxonium ion Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 278
- 238000012360 testing method Methods 0.000 description 22
- 230000000052 comparative effect Effects 0.000 description 9
- 239000011701 zinc Substances 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 150000002739 metals Chemical class 0.000 description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 229910052593 corundum Inorganic materials 0.000 description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- NIPNSKYNPDTRPC-UHFFFAOYSA-N N-[2-oxo-2-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 NIPNSKYNPDTRPC-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000005300 metallic glass Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A kind of thin film transistor (TFT) of the present invention, including stacking gradually metal oxide semiconductor layer, the first insulating layer, grid layer, second insulating layer and the source/drain electrode layer of setting on substrate, wherein the first insulating layer and/or second insulating layer are the metal oxide layer by being obtained after metal layer, which has insulation performance.Metal layer can absorb the part oxonium ion in metal oxide semiconductor layer in oxidation process, can reduce the oxygen content in metal oxide semiconductor layer, improve its electric conductivity, effectively reduce the contact resistance of metal oxide semiconductor layer and source drain contact area.Meanwhile the present invention also provides a kind of preparation methods of thin film transistor (TFT), and the contact resistance of metal oxide semiconductor layer and source drain contact area can be effectively reduced by the oxidation of metal layer, it is not only simple for process, and greatly reduce production cost.
Description
Technical field
The present invention relates to a kind of organic light emitting displays.More particularly to a kind of thin film transistor (TFT) and its manufacturing method.
Background technology
Organic electroluminescent refers to the phenomenon that luminous organic material shines under the excitation of electric current or electric field.Organic hair
Light display device（Organic Lighting Emitting Display, abbreviation OLED）, with traditional liquid crystal display
（Liquid Crystal Display, abbreviation LCD）Display mode is different, has self luminous characteristic, is not necessarily to backlight.OLED
Have many advantages, such as thickness is thin, visual angle is wide, contrast is high, fast response time, low in energy consumption, flexibility, be current flat panel display
In concerned most one of technology, and have become most be hopeful replace LCD next-generation flat panel display.
One of Primary Component as organic light emitting display, thin film transistor (TFT)（Thin-filmtransistor, referred to as
TFT）Performance directly affect display quality quality, at present TFT-LCD largely use silica-base material thin film transistor (TFT), such as
Polysilicon（p-Si）TFT, but with the demand of the continuous development of OLED and flexible display technologies, need a kind of carrier mobility
Active layer semi-conducting material that is higher and can manufacturing at low temperature, and the p-Si of high carrier mobility large area systems at low temperature
It makes relatively difficult.Transparent amorphous metal oxide has the advantages that light transmittance and carrier mobility are high, can not only prepare
Transparent TFT, but also TFT can be greatly improved to the charge-discharge velocity of pixel electrode and the corresponding speed of pixel, it has also become mesh
Cutting edge technology in preceding OLED.
Current metal oxide thin-film transistor mainly uses bottom grating structure, grid layer and source/drain electrode in the structure
Layer easy tos produce larger parasitic capacitance, so that generating big storage capacitance in pixel circuit, influences the property of display device
Energy.Therefore, the thin film transistor (TFT) of top gate structure becomes an important research direction, but metal oxide half in top gate structure
The electric conductivity of conductor layer is poor, and metal oxide semiconductor layer and source/drain electrode layer contact area are small, easily cause metal
Oxide semiconductor layer and the big problem of source/drain electrode layer contact resistance.
Chinese patent literature CN103076703A discloses a kind of top gate type metal oxide thin-film transistor, such as Fig. 1 institutes
Show, including underlay substrate 10, the metal oxide semiconductor layer 20 on underlay substrate, be located at metal oxide semiconductor layer
On source electrode 61 and drain electrode 62, the gate insulating layer 30 on source electrode and drain electrode and between source electrode and drain electrode, be located at
Grid 40 on gate insulating layer, the Al on grid2O3Insulating layer 50 is located at Al2O3Insulating film on insulating layer
70 and positioned at top data line 80.The program, by being laid with Al layers, is passed through during forming thin film transistor (TFT)
Pyroreaction in oxygen atmosphere makes part of the metal oxide semiconductor layer react to form source electrode and drain electrode, while by Al film layers
Reaction generates Al2O3Insulating layer so that the parasitic capacitance of liquid crystal display panel is reduced to 1/5 of conventional panels or so, to reduce crystalline substance
Body pipe storage capacitance improves aperture opening ratio.But metal oxide semiconductor layer oxygen content is relatively high in the transistor arrangement, conductive
Ability is poor, can not effectively solve the problems, such as that contact resistance is big between metal oxide semiconductor layer and source/drain.
Invention content
For this purpose, it is to be solved by this invention be in the prior art top gate type metal oxide thin-film transistor semiconductor layer and
The larger problem of source/drain electrode layer contact resistance, to propose metal oxide semiconductor layer and source/drain electrode layer contact resistance
A kind of small thin film transistor (TFT) and its manufacturing method.
In order to solve the above technical problems, technical scheme is as follows：
A kind of thin film transistor (TFT) of the present invention, including stack gradually the metal-oxide semiconductor (MOS) of setting on substrate
Layer, the first insulating layer, grid layer, second insulating layer and source/drain electrode layer, which is characterized in that first insulating layer and/or
Two insulating layers are the metal oxide layer by being obtained after metal layer, and the metal oxide layer has insulation performance.
The metal layer is one or more combinations in Al, Zn, Fe, Cu.
First insulating layer be in insulating metal oxide layer, silicon nitride layer or the silicon oxide layer directly formed one layer or
The stack layer of multilayer, thickness 50nm-350nm.
The thickness of the second insulating layer is 100nm-500nm.
The second insulating layer is formed directly on first insulating layer, and covers the grid layer.
The second insulating layer is formed directly on the metal oxide semiconductor layer, and covers the grid layer.
The manufacturing method of the thin film transistor (TFT), includes the following steps：
S11, metal oxide semiconductor layer is formed on substrate；
S12, the metal layer for forming covering metal oxide semiconductor layer on substrate, form after the metal layer is oxidized
Metal oxide layer have insulation performance；And anaerobic annealing is carried out to metal oxide semiconductor layer and metal layer；
S13, under oxygen atmosphere, oxidation processes are carried out to metal layer, until metal layer is all aoxidized, first is made and insulate
Layer；
S14, grid, second insulating layer and source/drain electrode layer are directly formed on the first insulating layer.
The manufacturing method of the thin film transistor (TFT), includes the following steps：
S21, metal oxide semiconductor layer is formed on substrate；
S22, the first insulating layer is centrally formed above metal oxide semiconductor layer, along metal oxide semiconductor layer ditch
Road length direction, the length of the first insulating layer are less than the length of metal oxide semiconductor layer, on the first insulating layer direct shape
At grid layer；
S23, the metal layer that covering grid layer is directly formed on metal oxide semiconductor layer, the metal layer are oxidized
The metal oxide layer formed afterwards has insulation performance；And to each layer progress anaerobic annealing on substrate is arranged；
S24, under oxygen atmosphere, oxidation processes are carried out to metal layer, until metal layer is all aoxidized, second is made and insulate
Layer；
S25, source/drain electrode layer is directly formed over the second dielectric.
The manufacturing method of the thin film transistor (TFT), includes the following steps：
S31, metal oxide semiconductor layer is formed on substrate；
S32, the first metal layer is centrally formed above metal oxide semiconductor layer, after the first metal layer is oxidized
The metal oxide layer of formation has insulation performance；Along metal oxide semiconductor layer orientation, the first metal layer
Length is less than the length of metal oxide semiconductor layer, directly forms grid layer on the first metal layer；
S33, the second metal layer that covering grid layer is directly formed on metal oxide semiconductor layer, second metal
The metal oxide layer formed after layer is oxidized has insulation performance；And to being arranged at each layer progress anaerobic annealing on substrate
Reason；
S34, under oxygen atmosphere, oxidation processes are carried out to the first metal layer and second metal layer, until metal layer whole quilt
The first insulating layer and second insulating layer is made in oxidation；
S35, source/drain electrode layer is directly formed over the second dielectric.
The second insulating layer in step S14 and the first insulating layer described in step S22 are independent selected from nitridation
Silicon layer or silicon oxide layer.
The above technical solution of the present invention has the following advantages over the prior art:
1. a kind of thin film transistor (TFT) of the present invention and its manufacturing method, the first insulating layer and/or second insulating layer
For by the metal oxide layer obtained after metal layer, the metal oxide layer has insulation performance.The metal layer is
One or more combinations in Al, Zn, Fe, Cu.High annealing forms metal oxide to the metal layer under anaerobic
During layer, the oxygen in metal-oxide semiconductor (MOS) can be absorbed, this can effectively reduce the metal oxide half of source/drain region
Oxygen content in conductor reduces metal-oxide semiconductor (MOS) to improve the electric conductivity of contact zone metal-oxide semiconductor (MOS)
With the contact resistance of source/drain electrode interlayer.
2. a kind of thin film transistor (TFT) of the present invention and its manufacturing method, the formation of metal layer and metal oxide layer
Same sputtering equipment can be used to realize, it is simple for process, and reduce equipment cost and production cost.
3. a kind of thin film transistor (TFT) of the present invention and its manufacturing method, without making one again on second insulating layer
Layer insulating can reach ideal technique effect, reduce one-pass film-forming technique, when can save machine in manufacture craft and at
This.
Description of the drawings
In order to make the content of the present invention more clearly understood, it below according to specific embodiments of the present invention and combines
Attached drawing, the present invention is described in further detail, wherein
The structural schematic diagram of the top-grate structure thin film transistor of Fig. 1 prior arts；
Fig. 2 is the structural schematic diagram of the top-grate structure thin film transistor of the present invention.
Reference numeral is expressed as in figure：90- substrates, 91- metal oxide semiconductor layers, the first insulating layers of 92-, 93- grid
Pole layer, 94- second insulating layers, 95a- source electrodes, 95b- drain electrode.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the reality of the present invention
The mode of applying is described in further detail.
The present invention can be embodied in many different forms, and should not be construed as limited to embodiment set forth herein.
On the contrary, providing these embodiments so that the disclosure will be thorough and complete, and the design of the present invention will be fully conveyed to
Those skilled in the art, the present invention will only be defined by the appended claims.In the accompanying drawings, for clarity, the areas Ceng He can be exaggerated
The size and relative size in domain.It should be understood that when element such as layer, region or substrate are referred to as " being formed in " or " setting
" another element "upper" when, which can be arranged directly on another element, or there may also be intermediary elements.
On the contrary, when element is referred to as on " being formed directly into " or " being set up directly on " another element, intermediary element is not present.
Embodiment 1
The present embodiment provides a kind of thin film transistor (TFT)s, as shown in Fig. 2, including stacking gradually the metal being arranged on substrate 90
Oxide semiconductor layer 91, the first insulating layer 92, grid layer 93, second insulating layer 94 and it is arranged in the source at second insulating layer both ends
Pole 95a, drain electrode 95b.
Wherein the metal oxide semiconductor layer 91 can be selected from but not limited to indium gallium zinc oxide（Indium
Gallium Zinc Oxide abbreviations IGZO）, indium-zinc oxide（Indium Zinc Oxide abbreviations IZO）, aluminium doped indium oxide
Zinc（Al-IZO）One kind in equal materials, the present embodiment is preferably IGZO materials, and thickness can be 20nm-400nm, this implementation
Example is preferably 300nm.
First insulating layer 92 is the metal oxide layer by being obtained after metal layer, the metal oxide layer tool
There are insulation performance, the metal layer that can be selected from but not limited to one or more combinations in Al, Zn, Fe, Cu, the present embodiment
Preferably obtained Al is aoxidized by Al layers2O3Layer, thickness be can be 50nm-350nm, the present embodiment is preferably 150nm.
It is preferably Mo that the grid layer 93, which can be selected from but not limited to metal or alloy material, the present embodiment such as MoW, Mo,
Layer, thickness can be 50nm-500nm, and the present embodiment is preferably 350nm；
The second insulating layer 94 can be selected from silicon nitride layer or silicon oxide layer, and thickness can be 100nm-500nm, this
Embodiment is preferably 400nm；The second insulating layer 94 is formed directly on first insulating layer 92, and covers the grid
Layer 93；The second insulating layer 94 is formed directly on the metal oxide semiconductor layer 91, and covers the grid layer 93.
The present embodiment also provides the manufacturing method of the thin film transistor (TFT), includes the following steps：
S11, metal oxide semiconductor layer 91 is formed on substrate 90；
S12, the metal layer that covering metal oxide semiconductor layer 91 is formed on substrate 90, after the metal layer is oxidized
The metal oxide layer of formation has insulation performance；And metal oxide semiconductor layer 91 and metal layer are carried out at anaerobic annealing
Reason, annealing temperature are 100-400 DEG C, annealing time 30min-4h；
S13, under oxygen atmosphere, oxidation processes are carried out to metal layer, until metal layer is all aoxidized, first is made and insulate
Layer 92, in oxidation process, a concentration of 0-0.5ppm of O2, oxidizing temperature is 100-400 DEG C, oxidization time 30min-4h；Oxidation
After the completion, the white space that body is shielded on TFT mother matrixs and is shielded between body makes test cell：The test cell is sandwich knot
The capacitance of structure, levels are torpescence metal, and such as MoW, middle layer is the metal/metal oxide of required test, the present embodiment
Described in metal be Al, the metal oxide be Al2O3, capacity area is that 200um*200um is not fully oxidized in Al metals
The capacitance of Shi Suoshu test cells is 0pF, and the capacitance of the test cell is 1-20pF when being aoxidized completely, can pass through survey
The capacitance for trying the test cell judges whether Al metals are complete by oxidation.
S14, grid 93, second insulating layer 94, source electrode 95a and drain electrode 95b are directly formed on the first insulating layer 92.
The preparation method of first insulating layer 92 in the present embodiment, by the way of high-temperature oxydation metal layer, the metal layer
High annealing can absorb the oxygen in metal oxide semiconductor layer 91 under anaerobic, can reduce source electrode 95a, the areas drain electrode 95b
The oxygen content of the metal oxide semiconductor layer 91 in domain can improve the conductive energy of contact zone metal oxide semiconductor layer 91
Power, to effectively reduce the contact resistance between metal oxide semiconductor layer 91 and source electrode 95a, drain electrode 95b.
Embodiment 2
On the basis of embodiment 1, the structure of the thin film transistor (TFT) in the present embodiment is as shown in Figure 2.
Wherein, first insulating layer 92 can be selected from insulating metal oxide layer, silicon nitride layer or the oxygen directly formed
The stack layer of one or more layers in SiClx layer, the present embodiment are preferably the Al that directly sputtering is formed2O3Layer, thickness can be
50nm-350nm, the present embodiment are preferably 150nm.
The second insulating layer 94 is for by the metal oxide layer obtained after metal layer, the metal oxide layer
With insulation performance, the metal layer can be selected from but not limited to one or more combinations in Al, Zn, Fe, Cu, this implementation
Example preferably aoxidizes obtained Al by Al layers2O3Layer, thickness can be 100nm-500nm, and the present embodiment is preferably 400nm.Institute
It states second insulating layer 94 to be formed directly on first insulating layer 92, and covers the grid layer 93；The second insulating layer
94 are formed directly on the metal oxide semiconductor layer 91, and cover the grid layer 93.
The present embodiment also provides the manufacturing method of the thin film transistor (TFT), includes the following steps：
S21, metal oxide semiconductor layer 91 is formed on substrate 90；
S22, the first insulating layer 92 is centrally formed above metal oxide semiconductor layer 91, along metal-oxide semiconductor (MOS)
91 orientation of layer, the length of the first insulating layer 92 are less than the length of metal oxide semiconductor layer 91, in the first insulation
Grid layer 93 is directly formed on layer 92；
S23, the metal layer that covering grid layer 93 is directly formed on metal oxide semiconductor layer 91, the metal layer warp
The metal oxide layer formed after oxidation has insulation performance；And each layer to being arranged on substrate 90 carries out at anaerobic annealing
Reason, annealing temperature are 100-400 DEG C, annealing time 30min-4h；
S24, under oxygen atmosphere, oxidation processes are carried out to metal layer, until metal layer is all aoxidized, second is made and insulate
Layer 94, in oxidation process, O2A concentration of 0-0.5ppm, oxidizing temperature are 100-400 DEG C, oxidization time 30min-4h；Oxidation
After the completion, the white space that body is shielded on TFT mother matrixs and is shielded between body makes test cell：The test cell is sandwich knot
The capacitance of structure, levels are torpescence metal, and such as MoW, middle layer is the metal/metal oxide of required test, the present embodiment
Described in metal be Al, the metal oxide be Al2O3, capacity area is that 200um*200um is not fully oxidized in Al metals
The capacitance of Shi Suoshu test cells is 0pF, and the capacitance of the test cell is 1-20pF when being aoxidized completely, can pass through survey
The capacitance for trying the test cell judges whether Al metals are complete by oxidation.
S25, source electrode 95a and drain electrode 95b are directly formed in second insulating layer 94.
The preparation method of second insulating layer 94 in the present embodiment, by the way of high-temperature oxydation metal layer, the metal layer
High annealing can absorb the oxygen in metal oxide semiconductor layer 91 under anaerobic, can reduce source electrode 95a, the areas drain electrode 95b
The oxygen content of the metal oxide semiconductor layer 91 in domain can improve the conductive energy of contact zone metal oxide semiconductor layer 91
Power, to effectively reduce the contact resistance between metal oxide semiconductor layer 91 and source electrode 95a, drain electrode 95b.
Embodiment 3
On the basis of embodiment 1 or embodiment 2, the structure of the thin film transistor (TFT) in the present embodiment is as shown in Figure 2.
Wherein, the first insulating layer 92 is the metal oxide layer by being obtained after metal layer, the metal oxide layer
With insulation performance, the metal layer can be selected from but not limited to one or more combinations in Al, Zn, Fe, Cu, this implementation
Example preferably aoxidizes obtained Al by Al layers2O3Layer, thickness can be 50nm-350nm, and the present embodiment is preferably 150nm.
Second insulating layer 94 is the metal oxide layer by being obtained after metal layer, and the metal oxide layer has exhausted
Edge performance, the metal layer can be selected from but not limited to one or more combinations in Al, Zn, Fe, Cu, and the present embodiment is preferred
To aoxidize obtained Al by Al layers2O3Layer, thickness can be 100nm-500nm, and the present embodiment is preferably 400nm.Described second
Insulating layer 94 is formed directly on first insulating layer 92, and covers the grid layer 93；The second insulating layer 94 is direct
It is formed on the metal oxide semiconductor layer 91, and covers the grid layer 93.
The manufacturing method of thin film transistor (TFT) described in the present embodiment, includes the following steps：
S31, metal oxide semiconductor layer 91 is formed on substrate；
S32, the first metal layer is centrally formed above metal oxide semiconductor layer 91, the first metal layer is oxidized
The metal oxide layer formed afterwards has insulation performance；Along metal oxide semiconductor layer orientation, the first metal layer
Length be less than metal oxide semiconductor layer 91 length, on the first metal layer directly formation grid layer 93；
S33, the second metal layer that covering grid layer 93 is directly formed on metal oxide semiconductor layer 91, described second
The metal oxide layer formed after metal layer is oxidized has insulation performance；And each layer to being arranged on substrate 90 carries out anaerobic
Annealing, annealing temperature are 100-400 DEG C, annealing time 30min-4h；
S34, under oxygen atmosphere, oxidation processes are carried out to the first metal layer and second metal layer, until metal layer whole quilt
It aoxidizes, obtained first insulating layer 92 and second insulating layer 94, in oxidation process, O2A concentration of 0-0.5ppm, oxidizing temperature are
100-400 DEG C, oxidization time 30min-4h；After the completion of oxidation, body is shielded on TFT mother matrixs and shields the white space system between body
Make test cell：The test cell is the capacitance of sandwich structure, and levels are torpescence metal, and such as MoW, middle layer is institute
The metal/metal oxide that need to be tested, metal described in the present embodiment are Al, and the metal oxide is Al2O3, capacity area
For 200um*200um, when Al metals are not fully oxidized, the capacitance of the test cell is 0pF, when being aoxidized completely described in
The capacitance of test cell is 1-20pF, can judge whether Al metals have been aoxidized by testing the capacitance of the test cell
Entirely.
S35, source electrode 95a and drain electrode 95b are directly formed in second insulating layer 94.
The preparation of the first insulating layer 92 and second insulating layer 94, is all made of the side of high-temperature oxydation metal layer in the present embodiment
Formula, high annealing can absorb the oxygen in metal oxide semiconductor layer 91 to the metal layer under anaerobic, can reduce source electrode
95a, drain electrode 95b regions metal oxide semiconductor layer 91 oxygen content, contact zone metal-oxide semiconductor (MOS) can be improved
The conductive capability of layer 91, to effectively reduce the contact resistance between metal oxide semiconductor layer 91 and source electrode 95a, drain electrode 95b.
In order to further embody a kind of advantage of thin film transistor (TFT) provided by the present invention, ad hoc meter simultaneously implements comparative example 1-
3。
Comparative example 1
This comparative example provides a kind of thin film transistor (TFT), concrete structure and the preparation method is the same as that of Example 1, it is unique unlike institute
It is the Al that directly sputtering is formed to state the first insulating layer2O3Layer.
Comparative example 2
This comparative example provides a kind of thin film transistor (TFT), concrete structure and the preparation method is the same as that of Example 1, it is unique unlike institute
It is the Al that directly sputtering is formed to state second insulating layer2O3Layer.
Comparative example 3
This comparative example provides a kind of thin film transistor (TFT), concrete structure and the preparation method is the same as that of Example 1, it is unique unlike institute
It is directly to sputter the Al formed to state the first insulating layer and second insulating layer2O3Layer.
By being tested for the property to the thin film transistor (TFT) provided in above-described embodiment and comparative example, test method and survey
Test result is as follows：
Using semiconductor parametric tester（Purchased from Agilent, model 4156C）Source/drain region is carried out to thin film transistor (TFT)
Contact resistance test between metal oxide semiconductor layer：Specially 360 are made in source/drain region and metal semiconductor interlayer
A 5 μm * 5 μm of the contact hole being connected in series with each other draws two engagement pads in contact hole periphery, I- is carried out to all contact holes
V is tested.
Test data is as shown in the table：
As can be seen from the above data, the first insulating layer and/or second insulating layer are prepared using the method for embodiment 1-3
When, since high annealing can absorb the oxygen in metal oxide semiconductor layer to metal layer under anaerobic, source electrode, leakage can be reduced
The oxygen content of the metal oxide semiconductor layer in polar region domain can improve the conductive energy of contact zone metal oxide semiconductor layer
Power, reduce contact resistance, test result show using embodiment 1-3 method prepare thin film transistor (TFT) source/drain region with
Contact resistance between metal oxide semiconductor layer reduces ten times or more compared with the method for comparative example 1-3, so as to effectively improve
The performance of thin film transistor (TFT).
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And it is extended from this it is obvious variation or
It changes still within the protection scope of the invention.
Claims (11)
1. a kind of thin film transistor (TFT), including stack gradually setting metal oxide semiconductor layer on substrate, the first insulating layer,
Grid layer, second insulating layer and source/drain electrode layer, which is characterized in that first insulating layer and/or second insulating layer is by gold
Belong to the metal oxide layer obtained after layer oxidation, at least partly described metal oxide layer makes annealing treatment to obtain by anaerobic, institute
Stating metal oxide layer has insulation performance.
2. thin film transistor (TFT) according to claim 1, which is characterized in that the metal layer is one in Al, Zn, Fe, Cu
Kind or a variety of combinations.
3. thin film transistor (TFT) according to claim 1, which is characterized in that first insulating layer is the insulation directly formed
The stack layer of one or more layers in metal oxide layer, silicon nitride layer or silicon oxide layer, thickness 50nm-350nm.
4. thin film transistor (TFT) according to claim 1, which is characterized in that the thickness of the second insulating layer is 100nm-
500nm。
5. according to any thin film transistor (TFT)s of claim 1-4, which is characterized in that the second insulating layer is formed directly into
On first insulating layer, and cover the grid layer.
6. according to any thin film transistor (TFT)s of claim 1-4, which is characterized in that the second insulating layer is formed directly into
On the metal oxide semiconductor layer, and cover the grid layer.
7. a kind of manufacturing method of any thin film transistor (TFT)s of claim 1-6, which is characterized in that include the following steps：
S11, metal oxide semiconductor layer is formed on substrate；
S12, the metal layer for forming covering metal oxide semiconductor layer on substrate, the gold formed after the metal layer is oxidized
Belonging to oxide skin(coating) has insulation performance；And anaerobic annealing is carried out to metal oxide semiconductor layer and metal layer；
S13, under oxygen atmosphere, oxidation processes are carried out to metal layer, until metal layer is all aoxidized, obtained first insulating layer；
S14, grid, second insulating layer and source/drain electrode layer are directly formed on the first insulating layer.
8. the manufacturing method of thin film transistor (TFT) according to claim 7, which is characterized in that described in step S14
Two insulating layers are selected from silicon nitride layer or silicon oxide layer.
9. a kind of manufacturing method of any thin film transistor (TFT)s of claim 1-6, which is characterized in that include the following steps：
S21, metal oxide semiconductor layer is formed on substrate；
S22, the first insulating layer is centrally formed above metal oxide semiconductor layer, along metal oxide semiconductor layer ditch Taoist priest
Direction is spent, the length of the first insulating layer is less than the length of metal oxide semiconductor layer, directly forms grid on the first insulating layer
Pole layer；
S23, the metal layer that covering grid layer is directly formed on metal oxide semiconductor layer, shape after the metal layer is oxidized
At metal oxide layer have insulation performance；And to each layer progress anaerobic annealing on substrate is arranged；
S24, under oxygen atmosphere, oxidation processes are carried out to metal layer, until metal layer is all aoxidized, obtained second insulating layer；
S25, source/drain electrode layer is directly formed over the second dielectric.
10. the manufacturing method of thin film transistor (TFT) according to claim 9, which is characterized in that first described in step S22
Insulating layer is selected from silicon nitride layer or silicon oxide layer.
11. a kind of manufacturing method of any thin film transistor (TFT)s of claim 1-6, which is characterized in that include the following steps：
S31, metal oxide semiconductor layer is formed on substrate；
S32, it is centrally formed the first metal layer above metal oxide semiconductor layer, is formed after the first metal layer is oxidized
Metal oxide layer have insulation performance；Along metal oxide semiconductor layer orientation, the length of the first metal layer
Less than the length of metal oxide semiconductor layer, grid layer is directly formed on the first metal layer；
S33, the second metal layer that covering grid layer is directly formed on metal oxide semiconductor layer, the second metal layer warp
The metal oxide layer formed after oxidation has insulation performance；And to each layer progress anaerobic annealing on substrate is arranged；
S34, under oxygen atmosphere, oxidation processes are carried out to the first metal layer and second metal layer, until metal layer is all aoxidized,
The first insulating layer and second insulating layer is made；
S35, source/drain electrode layer is directly formed over the second dielectric.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310737218.0A CN104752515B (en) | 2013-12-27 | 2013-12-27 | A kind of thin film transistor (TFT) and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310737218.0A CN104752515B (en) | 2013-12-27 | 2013-12-27 | A kind of thin film transistor (TFT) and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104752515A CN104752515A (en) | 2015-07-01 |
| CN104752515B true CN104752515B (en) | 2018-11-13 |
Family
ID=53591908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310737218.0A Active CN104752515B (en) | 2013-12-27 | 2013-12-27 | A kind of thin film transistor (TFT) and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104752515B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001284600A (en) * | 2000-04-04 | 2001-10-12 | Matsushita Electric Ind Co Ltd | Thin-film transistor and manufacturing method thereof |
| CN1622337A (en) * | 2003-11-27 | 2005-06-01 | 三星Sdi株式会社 | Thin film transistor and method of manufacturing the same |
| CN1738070A (en) * | 2004-08-07 | 2006-02-22 | 三星Sdi株式会社 | Thin film transistor and method of fabricating the same |
| CN102347335A (en) * | 2010-07-23 | 2012-02-08 | 三星电子株式会社 | Display substrate and method of manufacturing same |
-
2013
- 2013-12-27 CN CN201310737218.0A patent/CN104752515B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001284600A (en) * | 2000-04-04 | 2001-10-12 | Matsushita Electric Ind Co Ltd | Thin-film transistor and manufacturing method thereof |
| CN1622337A (en) * | 2003-11-27 | 2005-06-01 | 三星Sdi株式会社 | Thin film transistor and method of manufacturing the same |
| CN1738070A (en) * | 2004-08-07 | 2006-02-22 | 三星Sdi株式会社 | Thin film transistor and method of fabricating the same |
| CN102347335A (en) * | 2010-07-23 | 2012-02-08 | 三星电子株式会社 | Display substrate and method of manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104752515A (en) | 2015-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6982040B2 (en) | Semiconductor device | |
| JP6246307B2 (en) | Semiconductor device | |
| CN105573549B (en) | Array substrate, touch screen and touch control display apparatus and preparation method thereof | |
| CN103403850B (en) | Thin film transistor (TFT) and manufacture method thereof and display unit | |
| CN104508808B (en) | Semiconductor device and method for producing same | |
| CN102859670B (en) | film forming method | |
| CN207381400U (en) | Display device | |
| CN104272463B (en) | Thin film transistor (TFT) and display device | |
| CN103972298B (en) | Thin Film Transistor And Method For Fabricating The Same | |
| CN102709326B (en) | Thin film transistor (TFT) and its manufacture method, array base palte and display device | |
| JP2009533884A (en) | Semiconductor device and manufacturing method thereof | |
| CN103872060B (en) | Array base palte and manufacture method thereof | |
| CN107004721A (en) | Thin-film transistor array base-plate | |
| JP2013232619A (en) | Display device, array substrate, thin film transistor, and manufacturing method thereof | |
| TW200845397A (en) | Thin-film transistor and method of manufacturing same | |
| TW201005950A (en) | Thin film transistor and method of manufacturing the same | |
| CN103325841A (en) | Thin-film transistor and manufacturing method and display device thereof | |
| CN108140675A (en) | Semiconductor device and its manufacturing method | |
| CN104362179B (en) | Thin-film transistor, manufacturing method of thin-film transistor, array substrate and display device | |
| CN104218063A (en) | Organic light emitting display device and method of manufacturing the same | |
| US20140103334A1 (en) | Oxide Semiconductor Thin Film Transistor, Manufacturing Method, And Display Device Thereof | |
| CN106941121A (en) | A kind of thin film transistor (TFT) and preparation method thereof, array base palte and display device | |
| CN104040724B (en) | The manufacture method of semiconductor device, display device and semiconductor device | |
| CN110246900A (en) | Semiconductor device and its manufacturing method | |
| JP2012028481A (en) | Field-effect transistor and manufacturing method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201211 Address after: No.146 Tianying Road, high tech Zone, Chengdu, Sichuan Province Patentee after: Chengdu CHENXIAN photoelectric Co.,Ltd. Address before: NO.320 Fuchunjiang Road, Optoelectronic Industrial Park, Kunshan Development Zone, Suzhou City, Jiangsu Province Patentee before: Kunshan New Flat Panel Display Technology Center Co.,Ltd. Patentee before: KunShan Go-Visionox Opto-Electronics Co.,Ltd. |