CN104752315B - Semiconductor element and its manufacture method - Google Patents
Semiconductor element and its manufacture method Download PDFInfo
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- CN104752315B CN104752315B CN201310727475.6A CN201310727475A CN104752315B CN 104752315 B CN104752315 B CN 104752315B CN 201310727475 A CN201310727475 A CN 201310727475A CN 104752315 B CN104752315 B CN 104752315B
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Abstract
The invention relates to a kind of semiconductor element and its manufacture method.The manufacture method of the semiconductor element.First, dielectric layer is formed on substrate, the dielectric layer includes Part I and Part II, and Part I is adjacent to substrate, and Part II is adjacent to Part I.Then, dielectric layer is handled with Nitrogen trifluoride, removes the Part II of dielectric layer, expose the Part I of dielectric layer.Present invention also offers a kind of semiconductor element manufactured in this way in addition.By the manufacture method of the semiconductor element of the present invention, the surface defect of dielectric layer can be effectively removed, the roughness of dielectric layer surface is greatly reduced, and promotes the degree of adhesion between stacks of thin films.In other words, semiconductor element of the invention can form the dielectric layer that few surface defects, roughness are low and degree of adhesion between other materials layer is high, so that the efficiency of element is substantially improved.
Description
Technical field
The present invention relates to a kind of semiconductor element and its manufacture method.
Background technology
With metal-oxide semiconductor (MOS)（MOS）Transistor unit size constantly reduces, the requirement to dielectric layer quality
It is more and more high.Existing known when forming dielectric layer, dielectric layer surface often produces defect, such as raised or defect etc., makes Jie
The roughness on electric layer surface（roughness）Rise.In the Patternized techniques such as follow-up lithographic, etching, dielectric layer surface
High roughness may cause the degree of adhesion between stacks of thin films bad, even result in the bridge defects of element（bridge defect）,
Or cause to be cracked（crack）, peel off（peeling）And the problems such as electric leakage.
As can be seen here, above-mentioned existing semiconductor element and its manufacture method are upper with using in product structure, manufacture method,
Obviously inconvenience and defect have been still suffered from, and has urgently been further improved.In order to solve above-mentioned problem, relevant manufactures are not
Do not seek solution painstakingly, but have no that applicable design is developed completing always for a long time, and common product and
Method can solve the problem that above mentioned problem without appropriate structure and method again, and this is clearly the problem of related dealer is suddenly to be solved.Cause
How this founds one of a kind of new semiconductor element and its manufacture method, the real current important research and development problem of category, also turns into and works as
Preceding industry pole needs improved target.
The content of the invention
It is an object of the present invention to the defects of overcoming existing semiconductor element and its manufacture method to exist, and provide one
The new semiconductor element of kind and its manufacture method, technical problem to be solved are to make wherein form few surface defects, surface
The dielectric layer that roughness is low and degree of adhesion between other materials layer is high, is very suitable for practicality.
The object of the invention to solve the technical problems is realized using following technical scheme.Itd is proposed according to the present invention
A kind of semiconductor element manufacture method, be included on substrate and form dielectric layer, the dielectric layer includes Part I and the
Two parts, the Part I are adjacent to the substrate, and the Part II is adjacent to the Part I.Then, with trifluoro
Change nitrogen and handle the dielectric layer, remove the Part II of the dielectric layer, expose described first of the dielectric layer
Point.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
The manufacture method of foregoing semiconductor element, wherein the material of the dielectric layer includes silica, silicon nitride, nitrogen oxygen
SiClx or its combination.
The manufacture method of foregoing semiconductor element, wherein the dielectric layer includes inner layer dielectric layer, metal interlevel dielectric
Layer or protective layer.
The manufacture method of foregoing semiconductor element, wherein the step of processing dielectric layer with Nitrogen trifluoride includes
Nitrogen and fluorine are implanted into the surface portion of the Part I of the dielectric layer, to form the part of surface implantation nitrogen and fluorine.
The manufacture method of foregoing semiconductor element, wherein part and the dielectric layer of surface implantation nitrogen and fluorine
The thickness ratio of the Part I is 1/150 to 1/14.
The manufacture method of foregoing semiconductor element, wherein the thickness of the part of surface implantation nitrogen and fluorine is 1 to 250
Angstrom.
The manufacture method of foregoing semiconductor element, wherein the thickness of the Part II is 50 angstroms to 1000 angstroms.
The manufacture method of foregoing semiconductor element, wherein the step of handling the dielectric layer with Nitrogen trifluoride includes regulation and control
An at least technological parameter, the technological parameter include：Radio-frequency power, gas of nitrogen trifluoride flow, carrier gas flow, ammonia gas
Body flow, argon gas flow or its combination.
The manufacture method of foregoing semiconductor element, wherein the vector gas include helium.
The manufacture method of foregoing semiconductor element, wherein the radio-frequency power is 20 to 200W.
The manufacture method of foregoing semiconductor element, wherein the gas of nitrogen trifluoride flow is 35 to 250sccm
（standard cubic centimeter per minute）.
The manufacture method of foregoing semiconductor element, wherein the carrier gas flow is 20 to 2,400sccm.
The manufacture method of foregoing semiconductor element, wherein the ammonia gas flow is 0 to 300sccm.
The manufacture method of foregoing semiconductor element, wherein the argon gas flow is 100 to 1,000sccm.
The manufacture method of foregoing semiconductor element, in addition to the shape on the Part I of the exposed dielectric layer
Into an at least material layer.
The manufacture method of foregoing semiconductor element, wherein an at least material layer includes reflection coating layer, photoresistance
Layer or its combination.
The object of the invention to solve the technical problems is also realized using following technical scheme.According to proposed by the present invention
A kind of semiconductor element, including substrate and dielectric layer.The dielectric layer is located on the substrate, and the dielectric layer includes surface element
Point, the surface portion is implanted with nitrogen and fluorine, and part and the thickness ratio of the dielectric layer of surface implantation nitrogen and fluorine
For 1/150 to 1/14.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
Foregoing semiconductor element, wherein the material of the dielectric layer includes silica, silicon nitride, silicon oxynitride or its group
Close.
Foregoing semiconductor element, wherein the dielectric layer includes inner layer dielectric layer, dielectric layer between metal layers or protective layer.
Foregoing semiconductor element, in addition to an at least material layer, on the dielectric layer.
Foregoing semiconductor element, wherein an at least material layer includes reflection coating layer, photoresist layer or its combination.
The present invention has clear advantage and beneficial effect compared with prior art.By above-mentioned technical proposal, the present invention
Semiconductor element and its manufacture method at least have following advantages and beneficial effect：Pass through the manufacture of the semiconductor element of the present invention
Method, the surface defect of dielectric layer can be effectively removed, be greatly reduced between the roughness of dielectric layer surface, and enhancement stacks of thin films
Degree of adhesion.In other words, semiconductor element of the invention can be formed few surface defects, roughness it is low and with other materials layer it
Between the high dielectric layer of degree of adhesion, so that the efficiency of element is substantially improved.
In summary, the invention relates to a kind of semiconductor element and its manufacture method.The manufacture of the semiconductor element
Method.First, dielectric layer is formed on substrate, the dielectric layer includes Part I and Part II, and Part I is adjacent to
Substrate, Part II are adjacent to Part I.Then, dielectric layer is handled with Nitrogen trifluoride, removes the Part II of dielectric layer, cruelly
Expose the Part I of dielectric layer.Present invention also offers a kind of semiconductor element manufactured in this way in addition.By this hair
The manufacture method of bright semiconductor element, the surface defect of dielectric layer can be effectively removed, the coarse of dielectric layer surface is greatly reduced
Degree, and promote the degree of adhesion between stacks of thin films.In other words, semiconductor element of the invention can form few surface defects, coarse
The high dielectric layer of low and between other materials layer degree of adhesion is spent, so that the efficiency of element is substantially improved.The present invention is in technology
On have significant progress, and there is obvious good effect, be really a new and innovative, progressive, practical new design.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, and in order to allow the above and other objects, features and advantages of the present invention can
Become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail as follows.
Brief description of the drawings
Figure 1A to 1E is the flow profile according to the manufacture method of the semiconductor element depicted in one embodiment of the invention.
Fig. 2 is the flow chart according to the manufacture method of the semiconductor element depicted in one embodiment of the invention.
The defects of Fig. 3 A are the silicon oxide layers not with Nitrogen trifluoride processing distribution map（defect map）.
The defects of Fig. 3 B are the silica after being handled with Nitrogen trifluoride distribution map.
Fig. 4 is the SIMS figure of the dielectric layer after being handled with Nitrogen trifluoride（SIMS）.
100：Substrate 102,102d：Dielectric layer
102a：Part I 102b：Part II
102c：Surface portion 102d：Pattern dielectric layer
102e：Surface portion 104：Surface defect
104a：Raised 104b：Defect
110、110a：Material layer 210,220,230,240：Step
Embodiment
Further to illustrate the present invention to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to according to semiconductor element proposed by the present invention and its manufacture method its embodiment, structure,
Method, step, feature and its effect, describe in detail as after.
For the present invention foregoing and other technology contents, feature and effect, in the following preferable reality coordinated with reference to schema
Applying in the detailed description of example to clearly appear from.By the explanation of embodiment, the present invention can should be reached predetermined
The technological means and effect that purpose is taken obtain one and more go deep into and specifically understand, but institute's accompanying drawings are only to provide reference
With purposes of discussion, not it is used for being any limitation as the present invention.
Figure 1A to 1E is the flow profile according to the manufacture method of the semiconductor element depicted in one embodiment of the invention.
Fig. 2 is the flow chart according to the manufacture method of the semiconductor element depicted in one embodiment of the invention.
Refer to shown in Figure 1A and Fig. 2, carry out step 210, form dielectric layer 102 on the substrate 100.Substrate 100 includes
Semiconductor substrate, such as silicon substrate.Substrate 100 can also be silicon-on-insulator（SOI）Substrate.Dielectric layer 102 can be interior
Layer dielectric layer, dielectric layer between metal layers or protective layer.Dielectric layer 102 can be individual layer or multilayer.The material bag of dielectric layer 102
Include silica, silicon nitride, silicon oxynitride or its combination.The forming method of dielectric layer 102 is, for example, chemical vapour deposition technique or painting
Cloth method.
In one embodiment, dielectric layer 102 includes Part I 102a and Part II 102b.Part I 102a is abutted
In substrate 100.Part II 102b is adjacent to Part I 102a.In this embodiment, Part II 102b is located at first
Divide on 102a.The Part II 102b of dielectric layer 102 surface has surface defect 104.Surface defect 104 is, for example, projection
104a or defect 104b.Raised 104a or defect 104b is probably to form the deposition process or coating process of dielectric layer 102
Middle generation.In the drawings, dielectric layer 102 directly contacts with substrate 100, however, the present invention is not limited thereto.Other real
Apply in example, an at least intermediate layer is also possible that between dielectric layer 102 and substrate 100.Intermediate layer can be insulating barrier, conductor
Layer, semiconductor layer or its combination.
Then, refer to shown in Figure 1B, Fig. 1 C and Fig. 2, carry out step 220, dielectric layer 102 is handled with Nitrogen trifluoride（Figure
1B）, the Part II 102b of dielectric layer 102 is removed to expose the Part I 102a of dielectric layer 102（Fig. 1 C）.Remove dielectric
In the step of Part II 102b of layer 102, the silicon atom in dielectric layer 102 and the Fluorine atom from Nitrogen trifluoride, with
SiF4 is formed to remove the Part II 102b of dielectric layer 102.In addition, the step of removing the Part II 102b of dielectric layer 102
Part II 102b surface defect 104 can be removed simultaneously.The Part II 102b removed thickness be, for example, 50 angstroms extremely
1000 angstroms.
Above-mentioned the step of handling dielectric layer 102 with Nitrogen trifluoride, includes a regulation and control at least technological parameter, such as：Radio frequency work(
Rate, gas of nitrogen trifluoride flow, carrier gas flow, ammonia gas flow, argon gas flow or its combination.In an embodiment
In, radio-frequency power is 20 to 200W；Gas of nitrogen trifluoride flow is 35 to 250sccm；Vector gas include inert gas（Such as
Helium, argon gas）, helium gas flow is 20 to 2400sccm, and argon gas flow is 100 to 1,000sccm；And ammonia gas flow
For 0 to 300sccm.
Thereafter, refer to shown in Figure 1B and Fig. 1 C, in one embodiment, dielectric layer 102 is handled with Nitrogen trifluoride, not only will
Nitrogen is implanted in the Part II 102b of dielectric layer 102 with fluorine, and nitrogen and fluorine are also implanted in the Part I 102a of dielectric layer 102
In.Therefore, after the Part II 102b of dielectric layer 102 and surface defect 104 is removed, Part I 102a surface portion
102c is still implanted with nitrogen and fluorine.Surface portion 102c and the Part I 102a of dielectric layer 102 thickness ratio are, for example, 1/150
To 1/14.In one embodiment, it is 1 to 250 angstrom that surface portion 102c thickness, which is, for example,.Nitrogen in surface portion 102c it is dense
Degree is, for example, 1 × 1017To 2 × 1018Atom/cubic centimetre.The concentration of fluorine in surface portion 102c is, for example, 8 × 1019To 3
×1020Atom/cubic centimetre.
Then, refer to shown in Fig. 1 D and Fig. 2, step 230 is carried out, in the Part I of the dielectric layer 102 exposed
An at least material layer 110 is formed on 102a.Material layer 110 can be single or multiple lift.In an embodiment, material layer 110 can be
Reflection coating layer, photoresist layer or its combination.In one embodiment, material layer 110 can be insulating barrier, conductor layer, metal level
Or its combination.
Afterwards, refer to shown in Fig. 1 E and Fig. 2, carry out step 240, pattern the material layer 110 and dielectric layer
102, to form patterned material layer 110a and pattern dielectric layer 102d.Pattern the material layer 110 and dielectric layer 102
Method can use lithographic and etch process.
Herein, by with reference to figure 1E come illustrate the present invention semiconductor element.As referring to figure 1E, semiconductor element of the invention
Pattern dielectric layer 102d including substrate 100 and on substrate 100.Pattern dielectric layer 102d includes surface portion
102e, surface portion 102e are implanted with nitrogen and fluorine.In addition, surface portion 102e and pattern dielectric layer 102d thickness ratio are
1/150 to 1/14.
The defects of Fig. 3 A are the silicon oxide layers not with Nitrogen trifluoride processing distribution map.Fig. 3 B are after being handled with Nitrogen trifluoride
Silica the defects of distribution map.
Refer to shown in Fig. 3 A and Fig. 3 B, not using number the defects of the silicon oxide layer surface of Nitrogen trifluoride processing as 4193；
And the defects of silicon oxide layer surface after being handled using Nitrogen trifluoride number is 145.This result, which shows to handle with Nitrogen trifluoride, to be situated between
Electric layer can effectively reduce surface defect really.
Fig. 4 is the SIMS figure of the dielectric layer after being handled with Nitrogen trifluoride（SIMS）.
Refer to shown in Fig. 4, after Nitrogen trifluoride is handled, left next dielectric layer is with sims analysis, and result is shown
It is to detect nitrogen and fluorine at 1 to 250 angstrom in case depth.In other words, handled via the Nitrogen trifluoride of the present invention, dielectric can be made
Layer it is thinning to remove surface the defects of, while also have a small amount of nitrogen-atoms and fluorine atom remain in it is left come dielectric layer it
In.Above-mentioned a small amount of nitrogen-atoms does not interfere with the property of dielectric layer with fluorine atom（Such as dielectric constant or hardness）, therefore also not
The efficiency of element can be influenceed.
In summary, in the manufacture method of the semiconductor element of the present invention, the surface defect of dielectric layer can be effectively removed,
The roughness of dielectric layer surface is greatly reduced.Therefore, the Patternized technique such as follow-up lithographic, etching nargin can improve, to reduce
The problems such as bridge defects of element, cracking, stripping and electric leakage.The present invention semiconductor element manufacture method can also promote with
Degree of adhesion between subsequent film.In other words, surface defect is formed as by the method for the present invention, the dielectric layer of semiconductor element
Dielectric layer few, that roughness is low and degree of adhesion between other materials layer is high, so that the efficiency of element is substantially improved.
The above described is only a preferred embodiment of the present invention, any formal limitation not is made to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people
Member, without departing from the scope of the present invention, when method and technology contents using the disclosure above make it is a little more
Equivalent embodiment that is dynamic or being modified to equivalent variations, as long as being the content without departing from technical solution of the present invention, according to the present invention's
Any simple modification, equivalent change and modification that technical spirit is made to above example, still falls within technical solution of the present invention
In the range of.
Claims (9)
1. a kind of manufacture method of semiconductor element, it is characterised in that it comprises the following steps：
One substrate is provided；
A dielectric layer is formed over the substrate, and the dielectric layer includes Part I and Part II, and the Part I is adjacent to this
Substrate, the Part II are adjacent to the Part I；And
The dielectric layer is handled with Nitrogen trifluoride, removes the Part II of the dielectric layer, exposes this first of the dielectric layer
Point；
Wherein, the step of should handling the dielectric layer with Nitrogen trifluoride, is included in a surface portion of the Part I of the dielectric layer
Nitrogen and fluorine are implanted into, to form the part of surface implantation nitrogen and fluorine；
Wherein, the part of surface implantation nitrogen and fluorine and the thickness ratio of the Part I of the dielectric layer are 1/150 to 1/14.
2. the manufacture method of semiconductor element according to claim 1, it is characterised in that the wherein material bag of the dielectric layer
Include silica, silicon nitride, silicon oxynitride or its combination；The dielectric layer includes inner layer dielectric layer, dielectric layer between metal layers or protection
Layer.
3. the manufacture method of semiconductor element according to claim 1, it is characterised in that wherein surface implantation nitrogen and fluorine
Part thickness be 1 to 250 angstrom.
4. the manufacture method of semiconductor element according to claim 1, it is characterised in that the wherein thickness of the Part II
For 50 angstroms to 1000 angstroms.
5. the manufacture method of semiconductor element according to claim 1, it is characterised in that wherein being handled with Nitrogen trifluoride should
The step of dielectric layer, includes a regulation and control at least technological parameter, and the technological parameter includes radio-frequency power, gas of nitrogen trifluoride flow, carried
Body gas flow, ammonia gas flow, argon gas flow or its combination；
Wherein, the vector gas include helium；The radio-frequency power is 20 to 200W；The gas of nitrogen trifluoride flow be 35 to
250sccm；The carrier gas flow is 20 to 2,400sccm；The ammonia gas flow is 0 to 300sccm；The argon gas stream
Measure as 100 to 1,000sccm.
6. the manufacture method of semiconductor element according to claim 1, it is characterised in that it is additionally included in exposed Jie
An at least material layer is formed on the Part I of electric layer；An at least material layer include reflection coating layer, photoresist layer or its
Combination.
7. a kind of semiconductor element, it is characterised in that it includes：
One substrate；And
One dielectric layer, on the substrate, the dielectric layer includes a surface portion, and the surface portion is implanted with nitrogen and fluorine, and should
It is 1/150 to 1/14 that surface, which is implanted into nitrogen and the part of fluorine with the thickness ratio of the dielectric layer,.
8. semiconductor element according to claim 7, it is characterised in that wherein the material of the dielectric layer includes silica, nitrogen
SiClx, silicon oxynitride or its combination；The dielectric layer includes inner layer dielectric layer, dielectric layer between metal layers or protective layer.
9. semiconductor element according to claim 7, it is characterised in that it also includes an at least material layer, positioned at the dielectric
On layer；An at least material layer includes reflection coating layer, photoresist layer or its combination.
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| CN201310727475.6A CN104752315B (en) | 2013-12-25 | 2013-12-25 | Semiconductor element and its manufacture method |
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| CN104752315A CN104752315A (en) | 2015-07-01 |
| CN104752315B true CN104752315B (en) | 2018-03-06 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540739A (en) * | 2003-04-22 | 2004-10-27 | 旺宏电子股份有限公司 | Method for preparing shallow grooved-isolation layer |
| CN1758421A (en) * | 2004-10-07 | 2006-04-12 | 海力士半导体有限公司 | Method of forming dielectric layer in semiconductor device |
| CN101416293A (en) * | 2006-03-31 | 2009-04-22 | 应用材料股份有限公司 | Method to improve the step coverage and pattern loading for dielectric films |
| CN102768955A (en) * | 2012-07-03 | 2012-11-07 | 上海华力微电子有限公司 | Method for forming low-loading-effect thin film |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080135953A1 (en) * | 2006-12-07 | 2008-06-12 | Infineon Technologies Ag | Noise reduction in semiconductor devices |
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2013
- 2013-12-25 CN CN201310727475.6A patent/CN104752315B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540739A (en) * | 2003-04-22 | 2004-10-27 | 旺宏电子股份有限公司 | Method for preparing shallow grooved-isolation layer |
| CN1758421A (en) * | 2004-10-07 | 2006-04-12 | 海力士半导体有限公司 | Method of forming dielectric layer in semiconductor device |
| CN101416293A (en) * | 2006-03-31 | 2009-04-22 | 应用材料股份有限公司 | Method to improve the step coverage and pattern loading for dielectric films |
| CN102768955A (en) * | 2012-07-03 | 2012-11-07 | 上海华力微电子有限公司 | Method for forming low-loading-effect thin film |
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