CN104752259B - To the sorting technique of the chip with yield unbecoming with technological level - Google Patents
To the sorting technique of the chip with yield unbecoming with technological level Download PDFInfo
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Abstract
A kind of sorting technique to the chip with yield unbecoming with technological level, product of the present invention based on personalization is in itself, according to the test result of each test item in the chip electrical testing, correlation analysis is carried out with making technological parameter used in chip to test item, if test item is uncorrelated to the technological parameter, judge that yield unbecoming with technological level possessed by chip is not belonging to special, systematic problem；In addition, to avoid a large amount of computings, efficiency is improved, correlation analysis is not carried out to each test item, but correlation analysis is carried out with technological parameter to the minimum test item of yield in every group of correlation.Above-mentioned classification can be special, system sex chromosome mosaicism with the producing cause of accurate judgement chip yield unbecoming with technological level, manpower and materials can be avoided to waste.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to it is a kind of to yield unbecoming with technological level
The sorting technique of chip.
Background technology
Field of semiconductor manufacture, yield is for the product after volume production（Including at least a chip）It is most important.Wherein, yield
Mainly it is divided to two kinds：First, the yield to match with technological level, another is and the disproportionate yield of technological level.If in the presence of with
The disproportionate yield of technological level, then manufacturer can consider the yield it is relatively low whether be special, systematic problem, if so,
Can then put into a large amount of manpower and materials be used for for the product yield raising.If it is not, then can be according to other productions on the production line
Method as category integrally improves the yield of product.
In the prior art, the yield of some product is obtained by defect concentration（Defect Density, D0）Calculate
Arrive.Compared with same type other products in same production line, if density is relatively large the defects of the product, then it is assumed that the product
Special, systematic problem be present.It is this to judge that product is asked with the presence or absence of special, systematic compared with other products
Topic can be present.First, this comparison have ignored the particularity of each product, thus it is inaccurate.Second, some situations
Under, the homotype product with production line does not make reference.Third, the flow-through product defects density made reference is inherently asked
Topic, i.e., reference product with the presence or absence of special, systematic problem in itself to having erroneous judgement.
Based on drawbacks described above, when classifying to the chip with yield unbecoming with technological level, it is likely that miss
Judge, by the yield as caused by such as product existing defects itself, design are not perfect etc. enough it is too low be classified as it is special, systemic
The problem of, effect is little when this can cause the manufacturer to spend a large amount of manpower and materials to improve the yield of the product.
Thus, semicon industry is needed badly and a kind of accurately the chip with yield unbecoming with technological level can classified
Method.
The content of the invention
The purpose that the present invention realizes is that more accurately the chip with yield unbecoming with technological level is classified.
To achieve the above object, the present invention provides a kind of classification side to the chip with yield unbecoming with technological level
Method, including：Obtain the test result of each test item in the electrical testing of some chips at least in a wafer；According to above-mentioned test knot
Fruit obtains the yield loss of each test item corresponding to the wafer；The yield loss pair of each test item according to corresponding to the wafer
Each test item carries out correlation analysis；According to each test item, whether above-mentioned all test items are grouped by correlation；Find every group
The test item of middle yield loss most serious；Phase is carried out with making technological parameter used in chip to the test item of yield loss most serious
The analysis of closing property, if the test item is uncorrelated to technological parameter used, yield unbecoming with technological level possessed by chip
It is not belonging to special, systematic problem.
Alternatively, some chips include the extreme chip of an at least test item test result in electrical testing.
Alternatively, if the coefficient correlation of test item and technological parameter is less than 0.3, the test item and the technological parameter not phase
Close.
Alternatively, yield loss is obtained by calculating, and if each the test result of each test item of chip uses some
Test item is unqualified, the method for continuing to test remaining test item.
Alternatively, the test result of each test item is " 0 " or " 1 ".
Alternatively, the test result of each test item is concrete numerical value.
Alternatively, in the 3sigma sections of test item and the coefficient correlation of technological parameter, if the yield damage of the test item
Lose and be less than 1%, then the test item is uncorrelated to the technological parameter.
Alternatively, find in every group after the test item of yield loss most serious, if most serious yield loss is less than in the group
1%, abandon carrying out correlation analysis with making technological parameter used in chip to the test item of the group.
Alternatively, obtain in yield loss, if the test result of each test item of each chip uses some test item not
Qualified, stopping continues to test the method for remaining test item.
Alternatively, the test result of each test item is the yield loss of the wafer corresponding to the test item.
Alternatively, in the 3sigma sections of test item and the coefficient correlation of technological parameter, if the yield damage of the test item
Lose and be less than 0.5%, then the test item is uncorrelated to the technological parameter.
Alternatively, find in every group after the test item of yield loss most serious, if most serious yield loss is less than in the group
0.5%, abandon carrying out correlation analysis with making technological parameter used in chip to the test item of the group.
Alternatively, after obtaining test result, in addition to：Progress correlation between making each technological parameter used in chip is divided
Analysis；According to each technological parameter, whether above-mentioned all technological parameters are grouped by correlation；Wherein, test item is with making used in chip
Technological parameter is carried out in correlation analysis, and technological parameter used is a technological parameter in every group.
Alternatively, each test item of the electrical testing includes：Caching function test, video memory velocity test.
Alternatively, each technological parameter used in the making chip includes：Critical size after development, critical size after etching,
Source-drain area ion implantation concentration, sacrificial oxide layer thickness.
Compared with prior art, technical scheme has advantages below：1）Through analysis, the D0 of prior art is calculated
Method, although it is contemplated that product（Including at least a chip）Technological level, but do not consider the individual character of product in itself, for
The chip of yield unbecoming with technological level, its producing cause are probably special, system sex chromosome mosaicism, it is also possible to which product is in itself
Problem, thus whether classify accurate very crucial.This is special, system sex chromosome mosaicism refers to that improvement technique can be so that yield reaches
The chip problem to match with technological level, for this is special, system sex chromosome mosaicism is opposing product self problem, the latter for example sets
The problems such as counting defect, complex process, larger chip, refer to that manufacturer can not be so that chip yield reaches and technique by improving technique
Level matches.For accurate judgement, its producing cause is special, system sex chromosome mosaicism, avoids manpower and materials from wasting, the present invention is based on
Personalized product in itself, according to the test result of each test item in the chip electrical testing, to test item and makes chip institute
Correlation analysis is carried out with technological parameter, if test item is uncorrelated to technological parameter used, judges the possessed of chip
Yield unbecoming with technological level（Yield is relatively low）It is not belonging to special, systematic problem；In addition, to avoid test item and work
Skill parameter carries out the macrooperation amount in correlation analysis, improves efficiency, and correlation analysis is not carried out to each test item, but
Correlation analysis is carried out with technological parameter to yield loss highest test item in every group of correlation, if the yield loss highest
Test item and make chip used in technological parameter it is uncorrelated, then with the slightly lower test item of other yield loss in group certainly also with
Those technological parameters are uncorrelated.
2）In alternative, the chip electrical test results of collection are not only the conventional chip of test result, in addition to survey
The extreme chip of test result, with enlarged sample capacity, cover more situations so that final classification is more accurate.
3）It is above-mentioned that test item and technological parameter are carried out in correlation analysis in alternative, can be a certain by changing
Technological parameter, the whether qualified probability of a test item of multiple chips is counted, that is, analyzes which technological parameter to test result
Have a significant impact；Experience have shown that smaller in test sample, i.e. the number of chip is less, and error is there may be based on test result,
When the coefficient correlation of test item and technological parameter is only not 0, both are just uncorrelated, but both coefficient correlations be less than it is a certain
During value, both are just uncorrelated, and above-mentioned value can be 0.3；It is larger in test sample, i.e. when the number of chip is enough, test item
When coefficient correlation with technological parameter is also only not 0, both are just uncorrelated, because when coefficient correlation is less than certain value
When, reduction limited extent of the technological parameter to yield loss is improved, based on cost consideration, above-mentioned coefficient correlation can set one
Empirical value, above-mentioned empirical value can be 0.3.
4）In alternative, yield loss is obtained by calculating, and the test result of each test item of each chip uses
If some test item is unqualified, the method for continuing to test remaining test item, such scheme is also referred to as COF（Continue On
Fail）Test pattern.The pattern is not unqualified because of some test item of some chip, without going to continue to survey remaining test item,
All test items of each chip can be thus tested, test result is comprehensive.For some test item, the test knot of each chip
Fruit can all obtain, then count underproof core number, divided by total core number, you can obtain the test item corresponding to the wafer
Yield loss.
5）In alternative, for 4）Alternative, the result using this kind of pattern test typically has two kinds of outputs, a kind of
It is for " 0 " or " 1 ", i.e., qualified（Pass）With it is unqualified（Fail）；Another kind is concrete numerical value, such as current value, 1 ampere, 2 peaces
Training, after setting acceptance line, you can know whether the test result is qualified.
6）In alternative, for above-mentioned 4）Alternative and 5）Alternative is related to technological parameter in test item
The 3sigma sections of coefficient（99.73%）It is interior, if the yield loss of the test item is less than 1%, the test item and the technological parameter
It is uncorrelated；In other words, the coefficient correlation is fallen into【0,1】Interior probability is 100%, if in the case of 99.73%, the yield loss is all
Less than 1%, then it is assumed that improve technological parameter and low yield improvement is not helped, i.e., the low yield is not belonging to special, systemic
The problem of.
7）In alternative, for above-mentioned 4）Alternative, find in every group after the test item of yield loss most serious, if
Most serious yield loss in the group（Highest yield loss）Less than 1%, abandon to the test item of the group with making technique used in chip
Parameter carries out correlation analysis, in other words, if the yield loss of each test item in this group of test item is below 1%, then it is assumed that
Test item in the group is insensitive to technological parameter, thus modified technique parameter is not helped low yield improvement, i.e., this is low
Special, systematic problem that yield is not belonging to.
8）In alternative, with 4）Alternative is arranged side by side, obtains in yield loss, each test item of each chip
If test result uses some test item unqualified, stopping continues to test the method for remaining test item, and such scheme is also referred to as SOF
（Stop On Fail）Test pattern.As long as a certain test item of the pattern chip is unqualified, other test items are not just continued to
Test, in other words, this kind of pattern only have recorded underproof first test item of chip, thus this kind of method cost is relatively low,
Test is time-consuming short.
9）In alternative, for 8）The SOF patterns of alternative, the test result of each test item are corresponding for the test item
The wafer yield loss, in other words, for this kind of pattern, the yield loss of the wafer corresponding to each test item is directly logical
The test result for crossing each test item obtains.
10）In alternative, for above-mentioned 8）Alternative and 9）Alternative is related to technological parameter in test item
The 3sigma sections of coefficient（99.73%）Interior, if the yield loss of the test item is less than 0.5%, the test item is joined with the technique
Number is uncorrelated；In other words, the coefficient correlation is fallen into【0,1】Interior probability is 100%, if in the case of 99.73%, the yield loss
Both less than 0.5%, then it is assumed that improve technological parameter the low yield improved and does not help, i.e., the low yield be not belonging to it is special, be
The problem of system property.
11）In alternative, find in every group after the test item of yield loss most serious, if most serious yield damages in the group
Lose（Highest yield loss）Less than 0.5%, abandon carrying out correlation point with making technological parameter used in chip to the test item of the group
Analysis, in other words, if the yield loss of each test item in this group of test item is below 0.5%, then it is assumed that the test item in the group
It is insensitive to technological parameter, thus modified technique parameter is not helped low yield improvement, i.e., the low yield is not belonging to special
, systematic problem.
12）In alternative, after obtaining test result, in addition to：To being carried out between each technological parameter used in making chip
Correlation analysis；According to each technological parameter, whether above-mentioned all technological parameters are grouped by correlation；Wherein, test item is with making
Technological parameter used in chip is carried out in correlation analysis, and technological parameter used is a technological parameter in every group, in other words, is
Reduce the operand in correlation analysis, not only test item is simplified, also technological parameter simplified.
13）In alternative, each test item of electrical testing includes：Caching function test, video memory velocity test.
14）In alternative, each technological parameter used in making chip includes：Critical size after development（After Develop
Critical Dimension, ADCD）, critical size after etching（After Etch Critical Dimension, AECD）、
Source-drain area ion implantation concentration, sacrificial oxide layer thickness.
Brief description of the drawings
Fig. 1 is the stream of the sorting technique to the chip with yield unbecoming with technological level in one embodiment of the invention
Cheng Tu；
Fig. 2 is to the sorting technique of the chip with yield unbecoming with technological level in another embodiment of the present invention
Flow chart；
Fig. 3 is to the sorting technique of the chip with yield unbecoming with technological level in further embodiment of the present invention
Flow chart.
Embodiment
As stated in the Background Art, in the prior art, when classifying to the chip with yield unbecoming with technological level,
It is likely to erroneous judgement occur, will yield be too low is classified as caused by such as product existing defects itself, design are not perfect etc. enough
Special, systematic problem, effect when this can cause the manufacturer to spend a large amount of manpower and materials to improve the yield of the product
Less.In view of the above-mentioned problems, the present invention proposes the product based on personalization in itself, according to each test item in the chip electrical testing
Test result, correlation analysis is carried out with making technological parameter used in chip to test item, if test item and technique used are joined
Number is uncorrelated, then judges that the yield of chip is relatively low and be not belonging to special, systematic problem；In addition, for avoid test item with
Technological parameter carries out the macrooperation amount in correlation analysis, improves efficiency, and correlation analysis is not carried out to each test item, and
It is that correlation analysis is carried out with technological parameter to yield loss highest test item in every group of correlation, if the yield loss highest
Test item and to make technological parameter used in chip uncorrelated, then it is certain with the slightly lower test item of other yield loss in group
It is uncorrelated to those technological parameters.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 is the sorting technique to the chip with yield unbecoming with technological level that one embodiment of the invention provides
Flow chart.The sorting technique is specifically introduced below in conjunction with Fig. 1.
Step S10 is first carried out, obtains the test knot of each test item in the electrical testing of some chips at least in a wafer
Fruit.
In specific implementation process, the chip electrical test results of collection are not only the conventional chip of test result, also wrap
The extreme chip of test result, such as the king-sized chip of transistor saturation current are included, it is more susceptible with enlarged sample capacity, covering
Condition so that final classification is more accurate.
In semicon industry, the test result of each test item can consult from the file of " stdf " form（Stdf forms
It is the general data format in semiconductor die testing field, the model with test equipment, brand, manufacturer etc. is unrelated）.In addition,
Some test items have an output result, such as output " 0 " represents that the chip test item is unqualified, and it is qualified that " 1 " represents, such as table
Test item 1 to 3 in 1, some directly export the test item 4 in concrete numerical value, such as table 1.Some do not have output result then.
For the test with output result, it can be tested using two ways.A kind of mode is as shown in table 1,
With the chip of three software and hardwares that can realize the Image Coding in remote real-time monitoring system（ASDP）1,2,3（Each ASDP cores
Piece includes three cachings）, a display chip 4, totally four chips, first caching（cache）Functional test（Corresponding test
Item 1）, second caching functional test（Corresponding test item 2）, the 3rd caching functional test（Corresponding test item 3）, one
The velocity test of video memory（Corresponding test item 4）, exemplified by totally four test items, the test result of each test item of each chip uses
If some test item is unqualified, the method for continuing to test remaining test item, such scheme is also referred to as COF（Continue On
Fail）Test pattern.The pattern is not unqualified because of some test item of some chip, without going to continue to survey remaining test item,
All test items of each chip can be thus tested, test result can reflect the performance of chip comprehensively.
Table 1
| Chip 1 | Chip 2 | Chip 3 | Chip 4 | |
| Test item 1 | 0 | 1 | 0 | 1 |
| Test item 2 | 1 | 1 | 1 | 1 |
| Test item 3 | 1 | 1 | 0 | 1 |
| Test item 4 | 500MHZ | 300MHZ | 900MHZ | 500GHZ |
Another way is as shown in table 2, still can realize the soft or hard of the Image Coding in remote real-time monitoring system with three
The chip of part（ASDP）1,2,3, display chip 4, totally four chips, three cachings（cache）Functional test（It is corresponding to survey
Try item 1,2,3）, video memory velocity test（Corresponding test item 4）, exemplified by totally four test items, each test of each chip
If the test result of item uses some test item unqualified, stopping continues to test the method for remaining test item, and such scheme is also referred to as
SOF（Stop On Fail）Test pattern.As long as a certain test item of the pattern chip is unqualified, other tests are not just continued to
Test, in other words, this kind of pattern only have recorded underproof first test item of chip, thus this kind of method cost compared with
Low, test is time-consuming short.
Table 2
| Chip 1 | Chip 2 | Chip 3 | Chip 4 | |
| Test item 1 | 0 | 1 | 1 | 1 |
| Test item 2 | 0 | 1 | 1 | |
| Test item 3 | 0 | 1 | ||
| Test item 4 | 500GHZ |
Perform step S20, the yield loss of each test item according to corresponding to above-mentioned test result obtains the wafer.
As described above, COF patterns can reflect the performance of each chip comprehensively, thus the present embodiment uses the above method to core
Piece carries out electrical testing.Accordingly, the yield loss of each test item is as shown in table 3 corresponding to wafer in table 1.
Table 3
| Chip 1 | Chip 2 | Chip 3 | Chip 4 | Wafer yield loss | |
| Test item 1 | 0 | 1 | 0 | 1 | 50% |
| Test item 2 | 1 | 1 | 1 | 1 | 0% |
| Test item 3 | 1 | 1 | 0 | 1 | 25% |
| Test item 4 | 500MHZ | 300MHZ | 900MHZ | 500GHZ | 0 |
For test item 1 to 3, unqualified core number, divided by total core number are counted, you can obtain corresponding to the wafer
The yield loss of the test item.
Test item 4, set acceptance line（It is as qualified higher than the acceptance line）, such as be 250MHZ for chip 1,2,3, it is right
In chip 4 be 400GHZ, you can know whether the test result of each chip qualified.Unqualified core number is counted, divided by
Total core number, you can obtain the yield loss of the test item corresponding to the wafer.
In addition, if test item does not have output result, " stdf " formatted file content is consulted, can learn should corresponding to the wafer
The yield loss of test item.
Step S30 is performed, the yield loss of each test item carries out correlation to each test item according to corresponding to the wafer
Analysis.
If above-mentioned correlation analysis can be qualified by a test item of the multiple chips of statistics, another test item is
No certain qualified probability, if or the multiple chips of statistics a test item it is unqualified when, necessarily not whether another test item
Qualified probability.Certainly, above-mentioned correlation analysis can also be used in semiconductor technology, tested in existing electrical testing
Correlation analysis between.In addition, above-mentioned correlation analysis is applied equally to the correlation between technological parameter
Property analysis, and the correlation analysis between technological parameter and test result, so as to finally learn, which technological parameter is for final
Test result have significant impact.
Experience have shown that based on there may be error in test process, when two test item coefficient correlations are only not 1, two
Person just thinks related, but when both coefficient correlations are more than a certain empirical value, both just think correlation, and above-mentioned empirical value can be
0.98。
In one embodiment, the coefficient correlation of test item 1 and test item 2 is 0.99, and test item 2 is related to test item 3
Coefficient is 0.99, and the coefficient correlation of test item 1 and test item 3 is 0.98, and the coefficient correlation of test item 4 and test item 1,2,3 is equal
For 0.35.
Step S40 is performed, whether above-mentioned all test items are grouped by correlation according to each test item.
Wherein, test item 1, test item 2 are related to the three of test item 3, then three is divided into one group（Hereinafter referred to as first group）, and
Test item 4 and test item 1,2,3 are uncorrelated, then test item 4 is independent one group（Hereinafter referred to as second group）.
It is understood that test item 1, test item 2 are the performance test each cached with test item 3, the performance is slow
The access correctness deposited, due to three cachings of ASDP chips it is roughly the same, thus first group of three test item correlations.Second
The test item 4 of group is the velocity test of video memory, that is, surveys the degree of video memory access speed speed, due to test item 4 and test item 1,
2nd, 3 test purpose is different, thus test item 4 is all uncorrelated to first three test item.
Step S50 is performed, finds the test item of yield loss most serious in every group.
As can be seen that in first group, yield loss most serious test item is test item 1.
The test item effect that yield loss most serious in every group is found in this step is：In step S60, not to each
Test item carries out correlation analysis, but related to technological parameter progress to yield loss highest test item in every group of correlation
Property analysis.Because：If the yield loss highest test item is uncorrelated to making technological parameter used in chip, same group
In the slightly lower test item of other yield loss it is certainly also uncorrelated to those technological parameters.This step can carry out essence to test item
Letter, avoid test item from carrying out the macrooperation amount in correlation analysis with technological parameter, improve efficiency.
Step S60 is performed, correlation is carried out with making technological parameter used in chip to the test item of yield loss most serious
Analysis, if the test item is uncorrelated to technological parameter used, yield unbecoming with technological level possessed by chip does not belong to
In special, systematic problem.
Above-mentioned technological parameter is, for example,：Critical size after development（After Develop Critical Dimension,
ADCD）, critical size after etching（After Etch Critical Dimension, AECD）, source-drain area ion implantation concentration,
Sacrificial oxide layer thickness.
It is above-mentioned that test item and technological parameter are carried out in correlation analysis, it can be counted by changing a certain technological parameter
The whether qualified probability of one test item of multiple chips, so as to learn, which technological parameter has for final test result
Significant impact.Certainly, above-mentioned correlation analysis can also be used in semiconductor technology, tested in existing electrical testing
The correlation analysis of item and technological parameter.
Experience have shown that smaller in test sample, i.e. the number of chip is less, and error is there may be based on test result, surveys
When the coefficient correlation for trying item and technological parameter is only not 0, both are just uncorrelated, but both coefficient correlations are less than a certain value
When, both are just uncorrelated, and above-mentioned value can be 0.3；It is larger in test sample, i.e. when the number of chip is enough, test item with
When the coefficient correlation of technological parameter is also only not 0, both are just uncorrelated, because when coefficient correlation is less than certain value
When, reduction limited extent of the technological parameter to yield loss is improved, based on cost consideration, above-mentioned coefficient correlation can set one
Empirical value, above-mentioned empirical value can be 0.3.
In one embodiment, after the coefficient correlation of critical size is 0.81, test item 1 and etched after test item 1 and development
The coefficient correlation of critical size is 0.82, the coefficient correlation of test item 1 and source-drain area ion implantation concentration is 0.7, test item 1 with
The coefficient correlation of sacrificial oxide layer thickness is 0.1, and the coefficient correlation of test item 2 and critical size after development is 0.81, test item 2
Coefficient correlation with critical size after etching is 0.82, the coefficient correlation of test item 2 and source-drain area ion implantation concentration is 0.75,
The coefficient correlation of test item 2 and sacrificial oxide layer thickness is 0.1, and the coefficient correlation of test item 3 and critical size after development is
0.84th, after test item 3 and etching the coefficient correlation of critical size for 0.82, the phase of test item 3 and source-drain area ion implantation concentration
Relation number is 0.66, the coefficient correlation of test item 3 and sacrificial oxide layer thickness is 0.1, test item 4 and critical size after development
Coefficient correlation is 0.86, the coefficient correlation of test item 4 and critical size after etching is 0.84, test item 4 and source-drain area ion are noted
The coefficient correlation for entering concentration is 0.78, the coefficient correlation of test item 4 and sacrificial oxide layer thickness is 0.2.
It is understood that ASDP chips include multiple metal-oxide-semiconductors, the access correctness of caching（Corresponding test item 1,2,3）
Related with critical size, source-drain area ion implantation concentration after critical size, etching after development, sacrificial oxide layer will be in metal-oxide-semiconductor
Removed after completing, thus access correctness and the sacrificial oxide layer cached and uncorrelated.The access speed of video memory（It is corresponding to survey
Try item 4）Related with critical size, source-drain area ion implantation concentration after critical size after development, etching, sacrificial oxide layer will be
Metal-oxide-semiconductor removes after completing, thus the access speed of video memory and sacrificial oxide layer and uncorrelated.
In test item and the 3sigma sections of the coefficient correlation of technological parameter（99.73%）It is interior, if the yield damage of the test item
Lose and be less than 1%（For COF patterns）Or 0.5%（For SOF patterns）, then the test item is uncorrelated to the technological parameter；In other words,
The coefficient correlation is fallen into【0,1】Interior probability is 100%, if in the case of 99.73%, the yield loss is both less than 1%（For COF
Pattern）Or 0.5%（For SOF patterns）, then it is assumed that improve technological parameter and low yield improvement is not helped, be i.e. the low yield
It is not belonging to special, systematic problem.
In another embodiment, flow chart as shown in Figure 2, find in every group after the test item of yield loss most serious, also
Carry out：Step S51：Judge most serious yield loss in the group（Highest yield loss）Whether 1% is less than（For COF patterns）Or
0.5%（For SOF patterns）, if so, performing step S52：Abandon entering the test item of the group with technological parameter used in making chip
Row correlation analysis, if it is not, following steps S60 is then performed, in other words, then to the test item of the group with making technique used in chip
Parameter carries out correlation analysis.
Operand of the above-mentioned effect for abandoning part group test item in the correlation analysis in step S60 is reduced, recognizes
If the yield loss for each test item in this group of test item is below 1%（For COF patterns）Or 0.5%（For SOF moulds
Formula）, then the test item in the group is insensitive to technological parameter, thus modified technique parameter is not helped low yield improvement,
I.e. the low yield is not belonging to special, systematic problem.
In another embodiment, flow chart shown in reference picture 3, step S50 finds the test of yield loss most serious in every group
, in addition to perform following steps：
Step S51 ', to carrying out correlation analysis between each technological parameter used in making chip.
Above-mentioned technological parameter is, for example,：Critical size after development, critical size after etching, source-drain area ion implantation concentration,
Sacrificial oxide layer thickness.
Above-mentioned correlation analysis, which can use, changes a technological parameter, records another technological parameter changing with the technological parameter
Change degree situation, it is of course also possible to use in semiconductor technology, the correlation point in existing electrical testing between technological parameter
Analysis method.
By analysis, in one embodiment, the coefficient correlation of critical size and critical size after etching is 0.99 after development,
The coefficient correlation of critical size and source-drain area ion implantation concentration is 0.21 after development, critical size and source-drain area ion after etching
The coefficient correlation of implantation concentration is 0.24, and the coefficient correlation of critical size and sacrificial oxide layer thickness is 0.11 after development, is sacrificed
The coefficient correlation of oxidated layer thickness and source-drain area ion implantation concentration is 0.15, source-drain area ion implantation concentration and sacrificial oxide layer
The coefficient correlation of thickness is 0.13.
Step S52 ', according to each technological parameter, whether above-mentioned all technological parameters are grouped by correlation.
Experience have shown that based on there may be error in test process, when two technological parameter coefficient correlations are only not 1,
Both just think related, but when both coefficient correlations are more than a certain empirical value, and both just think correlation, and above-mentioned empirical value can be with
For 0.98.
It is understood that after development critical size with critical size after etching due to causality, thus both
It is related.Source-drain area ion implantation concentration is uncorrelated to grid length thus all uncorrelated to above-mentioned two size.Sacrificial oxide layer exists
Metal-oxide-semiconductor removes after completing, thus with critical size, source-drain area ion implantation concentration after critical size, etching after development all
It is uncorrelated.
So, in step S60 ', test item is carried out in correlation analysis with making technological parameter used in chip, technique used
Parameter is a technological parameter in every group.In other words, to reduce the operand in correlation analysis, not only test item is carried out
Simplify, also technological parameter is simplified.
It should be noted that being not limited to one for simplifying the step S51 ' and step S52 ' of technological parameter is scheduled on step S50
Find in every group and carried out after the test item of yield loss most serious, the electricity of some chips at least in a wafer is obtained in step S10
Property test in each test item test result after, step S60 ' test item and technological parameter are carried out correlation analysis step it
Preceding progress.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (14)
- A kind of 1. sorting technique to the chip with yield unbecoming with technological level, it is characterised in that including：Obtain the test result of each test item in the electrical testing of some chips at least in a wafer；The yield loss of each test item according to corresponding to above-mentioned test result obtains the wafer；The yield loss of each test item carries out correlation analysis to each test item according to corresponding to the wafer；According to each test item, whether above-mentioned all test items are grouped by correlation；Find the test item of yield loss most serious in every group；Correlation analysis is carried out with making technological parameter used in chip to the test item of yield loss most serious, if the test item with Technological parameter used is uncorrelated, then yield unbecoming with technological level possessed by chip is not belonging to special, systematic Problem.
- 2. sorting technique according to claim 1, it is characterised in that some chips are included at least one in electrical testing The extreme chip of test item test result.
- 3. sorting technique according to claim 1, it is characterised in that if the coefficient correlation of test item and technological parameter is less than 0.3, then the test item is uncorrelated to the technological parameter.
- 4. sorting technique according to claim 1, it is characterised in that yield loss is obtained by calculating, and is specially：Statistics Unqualified core number, divided by total core number；And if the test result of each test item of each chip uses some test item Method that is unqualified, continuing to test remaining test item.
- 5. sorting technique according to claim 4, it is characterised in that the test result of each test item is " 0 " or " 1 ".
- 6. sorting technique according to claim 4, it is characterised in that the test result of each test item is concrete numerical value.
- 7. the sorting technique according to any one of claim 4 to 6, it is characterised in that in test item and technological parameter In the 3sigma sections of coefficient correlation, if the yield loss of the test item is less than 1%, the test item and the technological parameter not phase Close.
- 8. sorting technique according to claim 4, it is characterised in that find the test item of yield loss most serious in every group Afterwards, if most serious yield loss is less than 1% in the group, abandon carrying out the test item of the group with making technological parameter used in chip Correlation analysis.
- 9. sorting technique according to claim 1, it is characterised in that obtain in yield loss, each test of each chip If the test result of item uses some test item unqualified, stopping continues to test the method for remaining test item.
- 10. sorting technique according to claim 9, it is characterised in that in the coefficient correlation of test item and technological parameter In 3sigma sections, if the yield loss of the test item is less than 0.5%, the test item is uncorrelated to the technological parameter.
- 11. sorting technique according to claim 9, it is characterised in that find the test of yield loss most serious in every group Xiang Hou, if most serious yield loss is less than 0.5% in the group, abandon to the test item of the group with making technological parameter used in chip Carry out correlation analysis.
- 12. sorting technique according to claim 1, it is characterised in that after obtaining test result, in addition to：To carrying out correlation analysis between each technological parameter used in making chip；According to each technological parameter, whether above-mentioned all technological parameters are grouped by correlation；Wherein, test item is carried out in correlation analysis with making technological parameter used in chip, and technological parameter used is in every group One technological parameter.
- 13. sorting technique according to claim 1, it is characterised in that each test item of the electrical testing includes：Caching Functional test, video memory velocity test.
- 14. sorting technique according to claim 1, it is characterised in that technological parameter used in the making chip includes：It is aobvious Critical size, source-drain area ion implantation concentration, sacrificial oxide layer thickness after movie queen's critical size, etching.
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| US6393602B1 (en) * | 1998-10-21 | 2002-05-21 | Texas Instruments Incorporated | Method of a comprehensive sequential analysis of the yield losses of semiconductor wafers |
| US6445206B1 (en) * | 2000-05-31 | 2002-09-03 | Agere Systems Guardian Corp. | Method and apparatus for determining yield impacting tests at wafer level package level for semiconductor devices |
| CN101183399A (en) * | 2007-11-16 | 2008-05-21 | 浙江大学 | Method for analyzing and increasing yield of semi-conductor production line |
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| US6393602B1 (en) * | 1998-10-21 | 2002-05-21 | Texas Instruments Incorporated | Method of a comprehensive sequential analysis of the yield losses of semiconductor wafers |
| US6445206B1 (en) * | 2000-05-31 | 2002-09-03 | Agere Systems Guardian Corp. | Method and apparatus for determining yield impacting tests at wafer level package level for semiconductor devices |
| CN101183399A (en) * | 2007-11-16 | 2008-05-21 | 浙江大学 | Method for analyzing and increasing yield of semi-conductor production line |
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