CN101183399A - Method for analyzing and increasing yield of semi-conductor production line - Google Patents
Method for analyzing and increasing yield of semi-conductor production line Download PDFInfo
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Abstract
The invention discloses a method used for analyzing and improving yield of semiconductor production line. The invention is characterized in that a test chip is used for precisely determining the defect rate curves of various process modules of the production line and the failure rate of contact holes, and an effective area curve of power off, an effective area curve of leakage of each layer of product layout and the number of the contact holes are analyzed, and a model framework of the yield then can be built. The invention has the advantages that the invention can precisely calculate different effects of defect rates of various process modules on the yield and the invention enables production personnel to exactly know the effects of various process modules of the production line on the yield, thus the engineering personnel of the production line can be instructed to rapidly and effectively solve the deficiencies seriously affecting the yield, and the yield then can be improved rapidly and effectively.
Description
Technical field
The invention belongs to integrated circuit and make the field, especially relate to the method for analyzing and improving ic yield.
Background technology
Semi-conductive yield rate and and the progress speed of technology maturation determined whether a semiconductor maker gains.How improving yield rate faster and better is a urgent problem.It is very important wherein setting up the model of effective yield rate and can reducing fatal defective apace.The model of yield rate is to estimate yield rate with the whole area of chip with from every layer of optical measurement equipment estimation or the ratio of defects of each technical module traditionally.BOSE-EINSTEIN model commonly used as shown in Equation (1).
Wherein Y is a yield rate, Y
SBe an empirical constant, A
0Be chip area, D
LAYERIt is the ratio of defects of a technical module.D
LAYERUsually be from the result of optical measurement equipment and experience decision.This model has its weak point, mainly shows following two aspects:
1) this model can not quantitatively accurately calculate the influence of the ratio of defects of every layer and various technical modules to yield rate.D
LAYERMore just empirical constants.Usually people rule of thumb think in whole production line, and some layer and technical module are important as Poly and ground floor metal, again in conjunction with the data of optical measurement equipment to D
LAYERAssignment.To thinking important layer and technical module, D
LAYERWill be endowed bigger value, on the contrary, for unessential relatively layer such as image height layer metal, D
LAYERJust give a little value.From above process as can be seen, this assignment is mostly to be accumulations of experience, does not have concrete quantization method, therefore also just can't accurately calculate every layer with the influence of the defective of certain technical module to yield rate.
2) this yield model has only been considered the area of entire chip, does not consider the difference of layout design parameter.In order to estimate the yield rate of chip more accurately, not only the ratio of defects of the technical module of production line will be considered, the layout design of chip also will be considered.For instance, the chip of a same area, one is logical circuit, and one is memory circuit, and their yield rate can be a great difference.So it may be inaccurate estimating yield rate with same formula.
An important method that improves semiconductor yield traditionally is the various technical module ratio of defects that obtain production line by the measurement equipment of optics, and then reduces the purpose that improves yield rate that reaches of defective by various measures.When the minimum feature and the minimum spacing of integrated circuit becomes more and more littler, the limitation of this method for measurement is more and more obvious.This method mainly contains following problem:
1) not every defective workmanship can both be measured by optical device.The efficient of checkout equipment is difference with the susceptibility of its setting of work.If it is too high that susceptibility is set, can produce the false defective of a lot of vacations; If set too lowly, just having genuine defective can not be measured.So the setting of susceptibility is most important to the validity that detects.But all be to come under the more susceptible condition of this setting, necessarily make equipment can detect all defectives or most defective thereby can not accurately set this parameter theoretically from experience.The susceptibility difference of the defective of different materials in addition; The susceptibility that the metal level defective is set not necessarily is suitable for oxide layer.This has also increased the difficulty of setting effective susceptibility widely
2) the not all defective that measures all is fatal defective.Even susceptibility is set correct, all defectives are all measured, and not every defective all is fatal and is bound to make chip failure.The raising yield rate be the more important thing is and will be reduced fatal defective, so be bound to cause chip failure if can not distinguish which kind of defective, improves yield rate quickly thereby just can not reduce this defective better.
3) efficient of defect level measurement equipment is very low, need take a long time to measure a slice silicon chip.
The semiconductor maker also relies on manual some limited patterns of drawing to make technical research traditionally, but the characteristics of this handicraft workshop are that efficient is slow, and can not design complicated test chip.Then 1 advanced technologies (150nm following) is necessary exactly.The needs of particularly industrial designing for manufacturing DFM (Design for Manufacturing) need very complicated test chip to improve the technology of production line.Traditional test chip can only be checked the defective workmanship of part, and the factor that much influences yields must rely on real product to check, and will reduce the pulling speed of yields so widely.
Summary of the invention
The present invention proposes a kind of method can fast and effeciently analyze and improve the main ratio of defects that influences yield rate, can improve the pulling speed of yield rate so widely.
The present invention lacks by the various technical modules that utilize test chip to come accurately to determine production line that rate falls into the crash rate of curve and contact hole and in conjunction with the analysis to the number of the useful area curve of every layer of outage of product domain and electric leakage and contact hole, thereby sets up the method and system that the yield rate of semiconductor production line was analyzed and improved to the yield rate model framework.Described method comprises:
1) determines outage and the defective curve of electric leakage and the crash rate of every kind of contact hole of each technical module of production line by the electricity performance measurement of test chip.
Described test chip carries out the design test circuit according to the influence that defective lost efficacy to the outage and the electric leakage of circuit performance.
The test circuit that is used to measure outage and leak electricity defective in the test chip is preferably the aggregate of comb shape and P serpentine; Be used to measure the aggregate that the test circuit of the crash rate of contact hole is made up of a lot of contact holes and connecting line.The scope of general P is: P 〉=4.Because need come from the result of test match defective curve (with reference to below formula (1)), so will have at least 〉=3 data points come match. for the situation of P=4, the defect result of outage has 4 data points; Electric leakage has 3.
Obtaining of described every layer outage and electric leakage defective curve comprises:
(1) measure this layer every kind of test circuit outage and the electric leakage failure conditions;
(2) calculate the size of defective according to the number that lost efficacy between adjacent lines and live width and line-spacing;
(3) obtain the curve that cuts off the power supply and leak electricity defect size.
Obtaining of the crash rate of every kind of contact hole comprises:
(1) yield rate of the test circuit of every kind of contact hole of measurement;
(2) crash rate of calculating each contact hole according to number and its yield rate of every kind of contact hole.
2) by the analysis of product domain being obtained every layer outage and the useful area curve of electric leakage and the number of every kind of contact hole.
A kind of method of obtaining useful area is to shrink the outage useful area curve that obtains every layer and expand the electric leakage useful area curve that obtains every layer by figure by figure.
Shrink by figure, obtain every layer outage useful area curve, comprising:
(1) selects a circuit layer, such as ground floor metal M 1;
(2) M1 figure on the circuit layout is inwardly shunk the overlapping region that obtains after figure shrinks from the limit with a flaw size, the area of overlapping region in all domains is added just can obtain the outage useful area of the pairing M1 of this defective together then at this flaw size;
(3) select different flaw sizes to repeat for second step, just can obtain the outage useful area curve of M1 at different flaw sizes;
(4) select all circuit layers successively, repeat second and three steps and just can obtain every layer outage useful area curve.
Expand the electric leakage useful area curve that obtains every layer by figure, comprising:
(1) selects a circuit layer, such as ground floor metal M 1;
(2) M1 figure on the circuit layout is obtained overlapping region after the figure expansion with a flaw size from both sides expansions, the area of overlapping region in all domains is added just can obtain the electric leakage useful area of the pairing M1 of this defective together then at this flaw size;
(3) select different flaw sizes to repeat for second step, just can obtain the electric leakage useful area curve of M1 at different flaw sizes;
(4) select all circuit layers successively, repeat second and three steps and just can obtain every layer electric leakage useful area curve.
The another kind of method of obtaining useful area is to obtain every layer outage useful area curve and every layer electric leakage useful area curve by Monte Carlo (MONTO CARLO) simulation.
Obtain every layer outage useful area curve by Monte Carlo (MONTO CARLO) simulation, comprising:
(1) selects a circuit layer, such as ground floor metal M 1;
(2) a situation arises in circuit with the Monte Carlo simulation defective to select the defective of a size, the probability that the outage of calculating this defective then and being caused was lost efficacy; For instance, if defective has taken place 10,000 times, the number of times that wherein causes outage to lose efficacy is 100, and then the probability that causes of this defective is that the area that 1%. its outage useful area are entire chip multiply by 1%;
(3) select different flaw sizes to repeat for second step, just can obtain the outage useful area curve of M1 at different flaw sizes;
(4) select all circuit layers successively, repeat second and three steps and just can obtain every layer outage useful area curve.
Obtain every layer electric leakage useful area curve by Monte Carlo (MONTO CARLO) simulation, comprising:
(1) selects a circuit layer, such as ground floor metal M 1;
(2) a situation arises in circuit with this defective of Monte Carlo simulation to select the defective of a size, the probability that the electric leakage of calculating this defective then and being caused was lost efficacy; For instance, if defective has taken place 10,000 times, the number of times that wherein causes electric leakage to lose efficacy is 100, and then the probability that causes of this defective is 1%, and the area that its electric leakage useful area is an entire chip multiply by 1%.
(3) select different flaw sizes to repeat for second step, just can obtain the electric leakage useful area curve of M1 at different flaw sizes.
(4) select all circuit layers successively, repeat second and three steps and just can obtain every layer electric leakage useful area curve.
The number of every kind of contact hole is by the analysis of product domain is obtained. because every kind of contact hole all is positioned at certain interlayer. for instance, VIA1 is the contact hole that connects M1 and M2, by analyzing the number that situation that M1 is connected with the M2 interlayer just can obtain VIA1.
3) by the defective curve of outage and electric leakage and the integration of useful area curve are set up the yield model of outage and electric leakage, set up the yield model of every kind of contact hole by amber rapping type; Every layer of outage and electric leakage yield rate and every kind of contact hole yield model combine and have just constituted the yield model of entire chip.
4) calculate of the influence of the defective of each technical module by what-if to yield rate to the final defective curve of each technology.
5) by the yield rate of product reality and the analysis of yield model are obtained the influence of non-defect factors to the finished product rate.
In the inventive method, the most key is to set up yield model.This yield model is to have the outage of each layer and the yield rate of electric leakage yield rate and every kind of contact hole to form.For instance, suppose that a kind of design has following design level to constitute, AA, POLY, CONTACT, M1, VIA1, M2, VIA2, M3, VIA3, M4, VIA4, M5.Yield rate then comprises following content:
The yield rate of AA outage and electric leakage;
The yield rate of POLY outage and electric leakage;
The yield rate of M1 outage and electric leakage;
The yield rate of M2 outage and electric leakage;
The yield rate of M3 outage and electric leakage;
The yield rate of M4 outage and electric leakage;
The yield rate of M5 outage and electric leakage;
The yield rate of CONATCT;
The yield rate of VIA1;
The yield rate of VIA2;
The yield rate of VIA3;
The yield rate of VIA4.
Their all products are exactly the yield rate of last entire product.
Set up the yield model of the outage or the electric leakage of each layer, must obtain two curves.Article one, curve is exactly the defective curve of the outage and the electric leakage of this layer; Second is the outage and the electric leakage useful area curve of this layer.
Be that example illustrates how to set up M1 electric leakage yield model with M1 electric leakage yield model below.In general, the defective curve of outage or electric leakage is to become big and diminish along with flaw size, the defective curve of the M1 electric leakage shown in curve among Fig. 2 (1), and this curve can obtain by test circuit.
The useful area curve is that the domain from product obtains.So-called useful area can be understood from following example.Not that each defective all can cause chip failure.This defective must arrive certain size (minimum dimension the in＞chip), and this defective will drop on certain position and just can cause chip failure.So-called useful area is meant that as long as fall in this area at the center of this defective, this chip is bound to lose efficacy.As can be seen, useful area is relevant with the size of defective.For some technology, below minimum dimension, the useful area of every layer or certain technical module is zero, and this is because the size of defective is too little, is not enough to cause chip failure.But the size of working as defective arrives to a certain degree greatly, and no matter defective drops on chip Anywhere, as long as the incident that defective produces generation, chip just is bound to lose efficacy, and useful area at this moment is exactly the area of entire chip.Be illustrated with the example in Fig. 3 below.
Suppose that the live width among Fig. 3 is S, defective is circular, and radius is R.When R=S/2, as long as the middle part of two lines is dropped at the center of this defective, this defective will make two line electric leakages.When R=S/2+A, as long as the center of this defective is dropped within the middle grey area, this defective is bound to make two lines electric leakages.This grey area is exactly that its size is 2*L*A to electric leakage useful area that should flaw size.In above calculating, the useful area at two has been fallen suddenly.
From above simple computation, as can be seen, during less than the minimum dimension of domain, its value is zero to useful area at flaw size; During greater than minimum dimension, its value is relevant with the concrete domain of M1 at flaw size, and along with the change of flaw size is big, it is big that useful area also can become; After flaw size acquired a certain degree, useful area was exactly the area of entire chip, that is to say, as long as the defective of this size takes place, this chip necessarily returns inefficacy.
Actual product domain is very complicated.Usually there are two kinds of methods to obtain the outage and the electric leakage useful area curve of chip.The one, the useful area that the expansion by figure obtains leaking electricity, the useful area curve that the compression by figure obtains cutting off the power supply; The 2nd, the useful area curve that is cut off the power supply and leak electricity by the statistics of Monte Carlo (MONTOCARLO).
The useful area of M1 electric leakage can obtain from the synoptic diagram of Fig. 4.When two M1 line expansions, finally can overlap, overlapping area is exactly the useful area of electric leakage.Its useful area is the function of expansion size, and the size of this expansion is the size of flaw size just.
The useful area of M1 outage can obtain from the synoptic diagram of Fig. 5.When a M1 line inwardly shrinks from both sides and crosses medium line, finally can overlap, overlapping area is exactly the useful area of outage electricity.Its useful area is the function that shrinks size, and the size of this contraction is the size of flaw size just.
When the useful area of the M1 of counting yield outage and electric leakage, by to M1 wiredly do same operation simultaneously and realize.Similarly, can obtain the useful area curve of the outage and the electric leakage of other layer.
The method of another kind of Monte Carlo (MONTO CARLO) then is to obtain according to the method for adding up.Its method is the first defective of a certain size of hypothesis, and this defective can suppose it is circular or square, uses the method for Monte Carlo (MONTO CARLO) that this defective is fallen on the chip then, judges that then this defective causes the number of times of inefficacy.Specifically,, wherein caused inefficacy 10 times if fallen 10000 certain big or small defectives, then the useful area of the defective of this kind size be exactly entire chip area with 10/10000 become to amass.Actual product domain is very big, normally does the useful area that the simulation of Monte Carlo obtains the defective of different size by entire chip being divided into very little unit.
The electric leakage useful area curve of M1 is shown in the curve among Fig. 2 (2).
Generally speaking, for any semiconductor technology, undersized defective is more, and large-sized defective is few, uses following meter (1) to explain usually.
Wherein DD (x) is the outage of layer or the defective curve of electric leakage, and it is the function of defect size X.D0 is a ratio of defects, and K is a constant, and X is the size of defective, and P is the parameter of expression defective curve decline speed.P is big more, and the speed that this curve descends is fast more, that is to say that large-sized defective is few, and undersized defective is many.This curve is obtained by the match as a result of actual electrical measurement.
The number of the possible fatal electric leakage defective of certain one deck then is to have the integration of two curve products to decide, as shown in Equation (2):
CA (X) is the function that is used for representing useful area.The result of integration expresses with D0*aCA.
The yield formula of the outage of technical module (or every layer) and electric leakage defective is shown in (3).
Yield rate=e
-D 0 * aCA-------(3)
D in the formula
0With the meaning of aCA as shown in Figure 2.The process of whole integration as shown in Figure 2.
Repeat above process, just can obtain the outage and the electric leakage yield rate of each layer.
For the yield model of contact hole, then use following formula (4) and calculate.
Yield rate=e
-N* λ---------(4)
λ is the crash rate of contact hole in the formula, and N is the number of every layer of single contact hole.Must be noted that it is single contact hole, if contact hole＞=2 of using simultaneously a position, the number in this hole is not then counted.
This is because the probability that the contact hole in same position＞=2 lost efficacy simultaneously is very little, if take place continually, illustrates that the whole production line yield rate is zero substantially.This does not meet the hypothesis of the inefficacy that does not have feature.
N obtains from the actual domain of product.λ is obtained by test structure, its unit be generally in per 1,000,000,000 lost efficacy what.
Repeat above process, the yield rate of each contact hole just can obtain.
After the yield rate of the outage that obtains each layer and electric leakage yield rate and each contact hole, the yield rate of entire chip is exactly the product of all yield rates.
Generally speaking, the defective curve of every kind of production technology all can reach a final ripe level, and its curve generally can not be zero-fault.For instance, for 130 nanometer technologies of maturation, the D of M1 electric leakage
0(ratio of defects) may arrive 0.2 and lose efficacy every square centimeter.That is to say that every kind of defective workmanship curve can be saturated to certain situation.According to existing defective curve and final possible saturation curve, this kind defective just can accurately be calculated the influence of yield rate.This process can illustrate from Fig. 6.Curve (1) is existing M1 electric leakage defective curve; Curve (3) is final the defect level that can reach.By relatively these two curves and useful area curve (2) CA (X) respectively the difference behind the integration just can know of the influence of present ratio of defects yield rate.
By the analysis to existing defective curve and final saturated defective curve, each technical module just can accurately be calculated the influence of yield rate.
The front has been said from the defective curve result and the chip layout of test chip and has been calculated yield rate.Product also has actual yield rate aborning.Generally speaking, we can be divided into two big classes to the difference of actual product according to the yield rate feature.One class is the inefficacy that does not have feature, and another kind of is that feature lost efficacy.For instance, all lost efficacy if the failure characteristics of a silicon chip is all center sections, this illustrates this inefficacy owing to extraordinary reason causes, and is not because the unordered generation of defective causes.This characteristic inefficacy is because the defective of equipment is caused usually.
By comparing estimated yield rate and the actual yield rate of yield model, the yield rate influence that non-defective caused just can be calculated.For instance, according to yield model, under existing defect condition, this product is the highest can to reach 60%; There is not the yield rate that feature lost efficacy to have 50% in the reality; Middle difference 10% just is that non-defective causes.
Total the above, in the ratio of defects to every layer of production line and every technical module, the actual yield rate of the domain of product and product is made after the separate analysis, we just can put all results together and set up the failure reasons distribution.
Of the present invention have following advantage based on the method that improves the finished product rate:
(1) by can comparatively the calculate to a nicety ratio of defects of each technical module of test chip;
(2) in conjunction with the ratio of defects of each technical module and the design layout of product, the influence of each technical module to the entire product yield rate calculates to a nicety;
(3) in conjunction with the yield rate of the actual yield rate of product and yield model prediction, the yield rate forfeiture of accurately estimating non-defective and being caused.
Description of drawings
Fig. 1 is the process flow diagram that the present invention quantizes the yield rate reason;
Fig. 2 is by coming integration to set up the yield model synoptic diagram of M1 electric leakage to M1 electric leakage defective curve and M1 electric leakage useful area;
Fig. 3 is the synoptic diagram that calculates M1 electric leakage useful area;
Fig. 4 expands the synoptic diagram that obtains M1 electric leakage useful area by line;
Fig. 5 is the synoptic diagram that obtains M1 outage useful area by linear shrinkage;
Fig. 6 calculates the synoptic diagram of M1 electric leakage defective to the yield rate influence;
Fig. 7 measures the outage of ground floor metal M 1 and the test circuit synoptic diagram of electric leakage ratio of defects;
Fig. 8 is the electric leakage defective curve synoptic diagram of ground floor metal M 1;
Fig. 9 is the crash rate test circuit synoptic diagram of VIA1 contact hole;
What Figure 10 showed is the useful area curve synoptic diagram of the electric leakage of a product M1;
What Figure 11 showed is the number distribution plan of contact hole;
Figure 12 is the basic yield model of the present invention;
Figure 13 is the influence synoptic diagram of the defective of each technical module to yield rate.
Embodiment
Adopt the program circuit explanation the present invention of typical data now in conjunction with Fig. 1:
1. the various technical module defective curves of semiconductor production line obtains
Fig. 7 shows is the test circuit that obtains in the test chip of ratio of defects of 1 outage of ground floor metal M and electric leakage.This is the aggregate of a comb shape and P snakelike metal wire.
Here with P=4 the ratio of defects curve that how is cut off the power supply and leak electricity by electrical measurement is described.
Measurement to outage has 4 measurements--line 1, line 2, line 3 and line 4.
Measurement to electric leakage has 3 measurements--and line 1 is to the electric leakage of line 2, and line 2 is to the electric leakage of line 3, and line 3 is to the electric leakage of line 4.
Concerning the measurement of outage, in the circuit unit of a test, following several situation can appear:
1) single line disconnected (no adjacent lines is disconnected simultaneously), such as line 1, line 3 or line 2, line 4
2) the two-phase adjacent line is disconnected, and disconnected simultaneously such as line 1 and line 2, line 2 and line 3 are disconnected simultaneously, and line 3 and line 4 are disconnected simultaneously
3) three adjacent lines are disconnected, and are disconnected simultaneously such as line 1/ line 2/ line 3, and line 2/ line 3/ line 4 is disconnected simultaneously
4) four lines are disconnected simultaneously, and line 1/ line 2/ line 3/ line 4 is disconnected simultaneously
Can determine the size distribution of defective from the measurement result of outage.If a defective makes four lines disconnected simultaneously, the size of this defective can make the disconnected flaw size of three lines big than one simultaneously so; Same, be that the disconnected defective of single line is minimum.Certainly, when considering the flaw size size, also to consider the design parameter of measurement circuit itself.Generally speaking, measurement circuit includes the design size of all size, thereby can further obtain the accurate distribution of defect size.
Same reason, we can analyze the distribution curve of the electric defective of electric leakage.
Concerning the measurement of electric leakage, in the circuit unit of a test, following several situation can appear:
1) two-phase adjacent line electric leakage, such as line 1 and line 2,4 electric leakages of line 3/ line
2) three adjacent lines electric leakages are leaked electricity simultaneously such as line 1/ line 2/ line 3, and line 2/ line 3/ line 4 leaks electricity simultaneously
2) four lines leak electricity simultaneously, and line 1/ line 2/ line 3/ line 4 leaks electricity simultaneously
It must be noted that in above calculating, an implicit hypothesis is arranged, is exactly in the unit of a test, and a defective only takes place.Condition can satisfy by the size of control test cell in this.Here Guan Jian problem is the probability of the unordered generation of defective, a common test cell has only the hundreds of micron square, if it is very high to produce two probability with plural defective on so little area simultaneously, illustrate that entire chip does not have yield rate, not the unordered generation of defective just.As long as the forfeiture of yield rate is that such condition will satisfy because the unordered generation of defective causes.
What Fig. 8 showed is the distribution curve of M1 electric leakage defective.
For the crash rate of contact hole is to be obtained by as shown in Figure 9 test circuit.The contact pore chain that actual test circuit should include various design sizes reflects the various situations of design.
2. useful area curve and contact hole number obtains
Want accurately to set up the model of yield rate and estimate the yield rate of product, also must carefully analyze and study the design parameter of product domain according to the various technical module ratio of defects of technology.Different product has different layout design, and its yield rate relies on different to the various technical module ratio of defects of same production line.For instance, if the domain of a product has a lot of contact holes, this product will be very responsive to the crash rate of the contact hole module of production line; In contrast, if a product has only very a spot of contact hole, its yield rate just can be tolerated the crash rate of high contact hole.Generally speaking for setting up a simple yield model,, need to obtain every layer the outage of product domain and the number of electric leakage useful area and every layer of single contact hole by analysis and research to the product domain.
What Figure 10 showed is the useful area curve of the electric leakage of a product M1.
Figure 11 shows is the number distribution plan of the contact hole of this product of calculating from domain.
3. the foundation of yield model
What Figure 12 showed is a basic yield model.Wherein, X
0It is minimum dimension.Ratio of defects D
0Be the result's acquisition from test chip, aCA gets from the design layout integration of chip, and p is obtained by the defective curve fitting.
Yield model further refinement on this basis.For instance, if contact hole does not have other same contact hole at＜2 microns with interior, such contact hole can be divided into isolated contact hole, and as a rule, the crash rate of isolated contact hole is than the crash rate height of intensive contact hole.When doing the design layout analysis, the yield rate of isolated contact hole can separate analysis come out to estimate, remaining intensive contact hole will be estimated the yield rate of whole contact hole more exactly like this, thereby estimate the yield rate of entire chip more exactly in the nonoculture analysis.In addition, if a chip has the memory body zone, its yield rate also can be calculated separately.If this memory body also has as the restoring area that improves yield rate, this memory body has two kinds of yield rates, the one, and process is not repaired, and is lower usually; Another kind is through the yield rate after repairing.
4. the analysis of the actual yield rate of product
The front has been said from the chip layout of the result of test chip and production and has been calculated yield rate, the yield rate of product in the actual production.Generally speaking, we can be divided into two big classes to the difference of actual product according to the yield rate feature.One class is the inefficacy that does not have feature, and another kind of is that feature lost efficacy.For instance, all lost efficacy if the failure characteristics of a silicon chip is all center sections, this illustrates this inefficacy owing to extraordinary reason causes, and is not because the unordered generation of defective causes.This characteristic inefficacy is because the defective of equipment is caused usually.
5. influence the analysis-by-synthesis and the solution of the various defectives of yield rate
In the ratio of defects to every layer of production line and every technical module, the actual yield rate of the domain of product and product is made after the separate analysis, and we just can put all results together and set up the failure reasons distribution.As shown in Figure 1.
As can be seen from Figure 1, the reason of all yield rates forfeiture may be divided into three major types: a kind of is that the unordered generation of defective causes; Second kind is owing to causing with the irrelevant reason of defective; The third is because the defective of equipment causes.In order to improve yield rate better, the forfeiture of the yield rate that every kind of reason caused needs accurately to be determined.Utilize above method, just can accomplish this point.
In conjunction with the ratio of defects of the technical module of the production line that obtains from test chip and the layout analysis of product, two kinds of information can obtain, and the one, under the process conditions of existing production line, the finished product rate that its defective allowed; The 2nd, the ratio of defects of each technical module is to the influence of existing yield rate, thereby can know which module is bigger to the influence of yield rate, thereby reduces the defective of these modules, to reach the purpose of quick raising yield rate.
Actual yield rate by comparative product (part that does not have feature to lose efficacy) and the finished product rate of estimating that defective allowed will be known the numerical value that yield rate that non-defective causes is lost.Transistorized electric leakage, optical rectification (OPC) is bad or the like is the common yield rate that non-defective caused forfeiture.
Third part yield rate forfeiture be by equipment disappearance caused.Usually equipment is periodic maintenance, but equipment can be bad suddenly sometimes.The forfeiture of this class yield rate can be found by the analysis to the corresponding relation of the disabler feature of equipment and chip, also can and analyze which kind of equipment to the corresponding relation of silicon chip and may cause these features to lose efficacy by production equipment.Have problem if find certain equipment, also can identify with the result of test chip.
What Figure 13 showed is the influence of the defective of each technical module to the finished product rate. in this example, influence is 2.9% to M1 electric leakage defective to yield rate; AA/Poly is 6% to the influence of the contact hole of M1.
Claims (10)
1. method of analyzing and improving the yield rate of semiconductor production line comprises:
Determine outage and the defective curve of electric leakage and the crash rate of every kind of contact hole of each technical module of production line by the electricity performance measurement of test chip;
By the analysis of product domain being obtained every layer outage and the useful area curve of electric leakage and the number of every kind of contact hole;
By the defective curve of outage and electric leakage and the integration of useful area curve are set up the yield model of outage and electric leakage, set up the yield model of contact hole by amber rapping type; Every layer of outage and electric leakage yield rate and every kind of contact hole yield model combine and have just constituted the yield model of entire chip;
Just can know of the influence of the defective of each technical module by what-if to chip yield to the final defective curve of each technology;
Compared by the yield rate that the yield rate and the yield model of product reality are simulated and just can be obtained of the influence of non-defect factors the finished product rate.
2. method according to claim 1 is characterized in that: described test chip carries out the design test circuit according to the influence that defective lost efficacy to the outage and the electric leakage of circuit performance.
3. method according to claim 2 is characterized in that: the test circuit that is used in the described test chip measure outage and leak electricity defective is the aggregate of comb shape and P serpentine, the scope P of P 〉=3; Be used to measure the aggregate that the test circuit of the crash rate of contact hole is made up of a lot of contact holes and connecting line.
4. method according to claim 1 is characterized in that: expand the electric leakage useful area curve that obtains every layer by figure, comprising:
(1) selects a circuit layer;
(2) this circuit layer figure on the circuit layout is expanded the overlapping region that obtains after the figure expansion with a flaw size, the area of overlapping region in all domains is added just can obtain the electric leakage useful area of pairing this circuit layer of this defective together then at this flaw size;
(3) select different flaw sizes to repeat for second step, obtain the electric leakage useful area curve of this circuit layer at different flaw sizes;
(4) select all circuit layers successively, repeat second and three steps and obtain every layer electric leakage useful area curve.
5. method according to claim 1 is characterized in that: obtain every layer electric leakage useful area curve by Monte Carlo simulation, comprising:
(1) selects a circuit layer;
(2) a situation arises in circuit with the Monte Carlo simulation defective to select the defective of a size, and the probability that the electric leakage of calculating this defective then and being caused was lost efficacy multiply by the electric leakage useful area that area of chip obtains the defective of this size with this probability then;
(3) select different flaw sizes to repeat for second step, obtain the electric leakage useful area curve of this circuit layer at different flaw sizes;
(4) select all circuit layers successively, repeat second and three steps and obtain every layer electric leakage useful area curve.
6. method according to claim 1 is characterized in that: obtain every layer outage useful area curve by the contraction of figure, comprising:
(1) selects a circuit layer;
(2) this circuit layer figure on the circuit layout is shunk the overlapping region obtain after figure shrinks with a flaw size from both sides, the area of overlapping region in all domains is added just can obtain the outage useful area of pairing this circuit layer of this defective together then at this flaw size;
(3) select different flaw sizes to repeat for second step, obtain the outage useful area curve of this circuit layer at different flaw sizes;
(4) select all circuit layers successively, repeat second and three steps and just obtain every layer outage useful area curve.
7. method according to claim 1 is characterized in that: obtain every layer outage useful area curve by Monte Carlo simulation, comprising:
(1) selects a circuit layer;
(2) a situation arises in circuit with this defective of Monte Carlo simulation to select the defective of a size, and the probability that the outage of calculating this defective then and being caused was lost efficacy multiply by the outage useful area that area of chip obtains the defective of this size with this probability then;
(3) select different flaw sizes to repeat for second step, obtain the outage useful area curve of this circuit layer at different flaw sizes;
(4) select all circuit layers successively, repeat second and three steps and obtain every layer outage useful area curve.
8. method according to claim 1 is characterized in that: obtaining of every layer outage and electric leakage defective curve comprises:
(1) measure this layer every kind of test circuit outage and the electric leakage failure conditions;
(2) calculate the scope of the size of defective according to the number that lost efficacy between adjacent lines and live width and line-spacing;
(3) obtain the curve that cuts off the power supply and leak electricity defect size.
9. method according to claim 1 is characterized in that: obtaining of the crash rate of every kind of contact hole comprises:
(1) measures the yield rate of the test circuit of this kind contact hole;
(2) crash rate of calculating each contact hole according to number and its yield rate of every kind of contact hole.
10. one kind comprises the device of carrying out any one described method in aforementioned any claim.
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